aboutsummaryrefslogtreecommitdiff
path: root/include/dt-bindings/phy
AgeCommit message (Collapse)Author
2021-03-31dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock ↵Kishon Vijay Abraham I
provider Add #clock-cells binding to model Sierra as clock provider and include clock IDs for PLL_CMNLC and PLL_CMNLC1. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210319124128.13308-12-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Use a common header file for Cadence SERDESKishon Vijay Abraham I
No functional change. In order to have a single header file for all Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is in preparation for adding Cadence Sierra SERDES specific macros. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-17dt-bindings: phy: cadence-torrent: Add binding for refclk driverKishon Vijay Abraham I
Add binding for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210310112745.3445-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-17dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES WrapperKishon Vijay Abraham I
Add bindings for AM64 SERDES Wrapper. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210310112745.3445-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18dt-bindings: phy: Add PHY_TYPE_QSGMII definitionSwapnil Jakhade
Add definition for QSGMII phy type. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1600327846-9733-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18dt-bindings: phy: cadence-torrent: Add binding to specify SSC modeSwapnil Jakhade
Add binding to specify Spread Spectrum Clocking mode used. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1600280911-9214-7-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHYAnurag Kumar Vulisha
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed Processing System Gigabit Transceiver which provides PHY capabilities to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-19dt-bindings: phy: Add PHY_TYPE_XPCS definitionDilip Kota
Add definition for Ethernet PCS phy type. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Acked-by: Rob Herring <robh@kernel.org> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/6091f0d2a1046f1e3656d9e33b6cc433d5465eaf.1589868358.git.eswara.kota@linux.intel.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-17dt-bindings: phy: Add PHY_TYPE_DP definitionJyri Sarha
Add definition for DisplayPort phy type. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYsMartin Blumenstingl
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. The IP block contains settings for the PHY and a PLL. The PLL mode is configurable through a dedicated #phy-cell in .dts. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422Thomas Gleixner
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 101 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190113.822954939@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194Thomas Gleixner
Based on 1 normalized pattern(s): license terms gnu general public license gpl version 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-17dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoCKishon Vijay Abraham I
AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-10-22dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1Gustavo A. R. Silva
SERDES_MAX is a valid value to index ctrl->phys in drivers/phy/mscc/phy-ocelot-serdes.c. But, currently, there is an out-of-bounds bug in the mentioned driver when reading from ctrl->phys, because the size of array ctrl->phys is SERDES_MAX. Partially fix this by updating SERDES_MAX to be SERDES6G_MAX + 1. Notice that this is the first part of the solution to the out-of-bounds bug mentioned above. Although this change is not dependent on any other one. Suggested-by: Quentin Schulz <quentin.schulz@bootlin.com> Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-05dt-bindings: add constants for Microsemi Ocelot SerDes driverQuentin Schulz
The Microsemi Ocelot has multiple SerDes and requires that the SerDes be muxed accordingly to the hardware representation. Let's add a constant for each SerDes available in the Microsemi Ocelot. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-05-20dt-bindings: phy-qcom-usb2: Add support to override tuning valuesManu Gautam
To improve eye diagram for PHYs on different boards of same SOC, some parameters may need to be changed. Provide device tree properties to override these from board specific device tree files. While at it, replace "qcom,qusb2-v2-phy" with compatible string for USB2 PHY on sdm845 which was earlier added for sdm845 only. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-10-23dt-bindings: phy: Add PHY_TYPE_UFS definitionVivek Gautam
Add definition for UFS phy type. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-06-21phy: Add binding document for Pistachio USB2.0 PHYAndrew Bresticker
Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hartley <james.hartley@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03phy: miphy365x: Use the generic phy type constants in dt-bindings/phy/phy.hPeter Griffin
Now there are generic phy type constants declared in phy.h, migrate over to using them rather than defining our own. This change has been done as one atomic commit to be bisectable. Note: The values of the defines are the same, so there is no ABI breakage with this patch. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2014-11-26phy: add support for USB cluster on the Armada 375 SoCGregory CLEMENT
The Armada 375 SoC comes with an USB2 host and device controller and an USB3 controller. The USB cluster control register allows to manage common features of both USB controllers. This commit adds a driver integrated in the generic PHY framework to control this USB cluster feature. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [ kishon@ti.com : Made it to use the updated devm_phy_create API and soem cosmentic changes in Kconfig file.] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
2014-11-11phy: Add PHY header file for DT x Driver definesGabriel FERNANDEZ
This provides the shared header file which will be reference from both PHY driver and its associated Device Tree node(s). Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
2014-07-22phy: miphy365x: Add MiPHY365x header file for DT x Driver definesLee Jones
This provides the shared header file which will be reference from both the MiPHY365x driver and its associated Device Tree node(s). Cc: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 12:03:37 +0000