From 24ccfa06b7ea3c3f7f53f6bac9425d604ebce470 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 24 May 2015 16:11:30 +0100 Subject: MIPS: JZ4740: support newer SoC interrupt controllers Allow the interrupt controllers of the JZ4770, JZ4775 & JZ4780 SoCs to be probed via devicetree, supporting the 64 interrupts they provide. Signed-off-by: Paul Burton Cc: Lars-Peter Clausen Cc: Thomas Gleixner Cc: Jason Cooper Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris Patchwork: https://patchwork.linux-mips.org/patch/10155/ Signed-off-by: Ralf Baechle --- arch/mips/jz4740/irq.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c index 5887f379ff6e..64b4c3639280 100644 --- a/arch/mips/jz4740/irq.c +++ b/arch/mips/jz4740/irq.c @@ -167,3 +167,12 @@ static int __init intc_1chip_of_init(struct device_node *node, return ingenic_intc_of_init(node, 1); } IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init); + +static int __init intc_2chip_of_init(struct device_node *node, + struct device_node *parent) +{ + return ingenic_intc_of_init(node, 2); +} +IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); +IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); +IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); -- cgit v1.2.3