From d54348fbefcd006b2bf1db5c01159f2101b94a3f Mon Sep 17 00:00:00 2001 From: derek.fang Date: Fri, 12 Jun 2020 13:15:23 +0800 Subject: ASoC: rt5682: Let PLL2 support the freq conversion for 44100Hz sample rate PLL2 of rt5682 only supports the freq conversion for 48000Hz sample rate so far, this patch lets it support 44100Hz. Signed-off-by: derek.fang Link: https://lore.kernel.org/r/1591938925-1070-3-git-send-email-derek.fang@realtek.com Signed-off-by: Mark Brown --- sound/soc/codecs/rt5682.c | 9 ++++++++- sound/soc/codecs/rt5682.h | 4 ++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/rt5682.c b/sound/soc/codecs/rt5682.c index 3e9d2c6c51f9..8f4ab90207b5 100644 --- a/sound/soc/codecs/rt5682.c +++ b/sound/soc/codecs/rt5682.c @@ -2248,7 +2248,7 @@ static int rt5682_set_component_pll(struct snd_soc_component *component, { struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; - unsigned int pll2_fout1; + unsigned int pll2_fout1, pll2_ps_val; int ret; if (source == rt5682->pll_src[pll_id] && @@ -2317,8 +2317,15 @@ static int rt5682_set_component_pll(struct snd_soc_component *component, pll2b_code.n_code); snd_soc_component_write(component, RT5682_PLL2_CTRL_3, pll2f_code.n_code << RT5682_PLL2F_N_SFT); + + if (freq_out == 22579200) + pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; + else + pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, + RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, + pll2_ps_val | (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 0xf); diff --git a/sound/soc/codecs/rt5682.h b/sound/soc/codecs/rt5682.h index f172c9ebd227..6d94327beae5 100644 --- a/sound/soc/codecs/rt5682.h +++ b/sound/soc/codecs/rt5682.h @@ -1080,6 +1080,10 @@ #define RT5682_PLL2F_N_SFT 8 /* PLL2 M/N/K Code Control 2 (0x009e) */ +#define RT5682_PLL2B_SEL_PS_MASK (0x1 << 13) +#define RT5682_PLL2B_SEL_PS_SFT 13 +#define RT5682_PLL2B_PS_BYP_MASK (0x1 << 12) +#define RT5682_PLL2B_PS_BYP_SFT 12 #define RT5682_PLL2B_M_BP_MASK (0x1 << 11) #define RT5682_PLL2B_M_BP_SFT 11 #define RT5682_PLL2F_M_BP_MASK (0x1 << 7) -- cgit v1.2.3