From e5aba13da0cc598a5573ea059717949fbd7536ad Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 26 Feb 2013 11:20:22 +0800 Subject: i2c: i2c-mxs: move to use generic DMA helper With the generic DMA device tree helper supported by mxs-dma driver, client devices only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. Signed-off-by: Shawn Guo Reviewed-by: Arnd Bergmann Acked-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-mxs.txt | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree/bindings/i2c') diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt index 7a3fe9e5f4cb..4e1c8ac01eba 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt @@ -3,10 +3,13 @@ Required properties: - compatible: Should be "fsl,-i2c" - reg: Should contain registers location and length -- interrupts: Should contain ERROR and DMA interrupts +- interrupts: Should contain ERROR interrupt number - clock-frequency: Desired I2C bus clock frequency in Hz. Only 100000Hz and 400000Hz modes are supported. -- fsl,i2c-dma-channel: APBX DMA channel for the I2C +- dmas: DMA specifier, consisting of a phandle to DMA controller node + and I2C DMA channel ID. + Refer to dma.txt and fsl-mxs-dma.txt for details. +- dma-names: Must be "rx-tx". Examples: @@ -15,7 +18,8 @@ i2c0: i2c@80058000 { #size-cells = <0>; compatible = "fsl,imx28-i2c"; reg = <0x80058000 2000>; - interrupts = <111 68>; + interrupts = <111>; clock-frequency = <100000>; - fsl,i2c-dma-channel = <6>; + dmas = <&dma_apbx 6>; + dma-names = "rx-tx"; }; -- cgit v1.2.3 From dc7c59d7c9d06f588ca813f0365f4eb620229211 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Mon, 18 Mar 2013 15:05:50 +0530 Subject: ARM: tegra: add DT binding for i2c-tegra Add documentation for device tree binding of NVIDIA's Tegra I2C controller driver. Describing all compatible values used for different Tegra SoCs in details in this documentation. Signed-off-by: Laxman Dewangan [swarren: fixed a couple typos, trimmed examples] Signed-off-by: Stephen Warren --- .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt (limited to 'Documentation/devicetree/bindings/i2c') diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt new file mode 100644 index 000000000000..ef77cc7a0e46 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt @@ -0,0 +1,60 @@ +NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. + +Required properties: +- compatible : should be: + "nvidia,tegra114-i2c" + "nvidia,tegra30-i2c" + "nvidia,tegra20-i2c" + "nvidia,tegra20-i2c-dvc" + Details of compatible are as follows: + nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C + controller. This only support master mode of I2C communication. Register + interface/offset and interrupts handling are different than generic I2C + controller. Driver of DVC I2C controller is only compatible with + "nvidia,tegra20-i2c-dvc". + nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support + master and slave mode of I2C communication. The i2c-tegra driver only + support master mode of I2C communication. Driver of I2C controller is + only compatible with "nvidia,tegra20-i2c". + nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is + very much similar to Tegra20 I2C controller with additional feature: + Continue Transfer Support. This feature helps to implement M_NO_START + as per I2C core API transfer flags. Driver of I2C controller is + compatible with "nvidia,tegra30-i2c" to enable the continue transfer + support. This is also compatible with "nvidia,tegra20-i2c" without + continue transfer support. + nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is + very much similar to Tegra30 I2C controller with some hardware + modification: + - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and + fast-clk. Tegra114 has only one clock source called as div-clk and + hence clock mechanism is changed in I2C controller. + - Tegra30/Tegra20 I2C controller has enabled per packet transfer by + default and there is no way to disable it. Tegra114 has this + interrupt disable by default and SW need to enable explicitly. + Due to above changes, Tegra114 I2C driver makes incompatible with + previous hardware driver. Hence, tegra114 I2C controller is compatible + with "nvidia,tegra114-i2c". +- reg: Should contain I2C controller registers physical address and length. +- interrupts: Should contain I2C controller interrupts. +- address-cells: Address cells for I2C device address. +- size-cells: Size of the I2C device address. +- clocks: Clock ID as per + Documentation/devicetree/bindings/clock/tegra.txt + for I2C controller. +- clock-names: Name of the clock: + Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk". + Tegra114 I2C controller: "div-clk". + +Example: + + i2c@7000c000 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 12>, <&tegra_car 124>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; + }; -- cgit v1.2.3