From 657a06df993c92ca404da4c251f7f354f1069eaa Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Mon, 23 Mar 2020 22:53:56 +0300 Subject: dt-bindings: gpio: Convert snps,dw-apb-gpio to DT schema Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces Synopsys DW GPIO legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with generic DW I2C controller indicated by the "snps,dw-apb-gpio" compatible string and to provide a mandatory registers memory range. It may also have an optional clock and reset phandle references. There must be specified at least one subnode with "snps,dw-apb-gpio-port" compatible string indicating the GPIO port, which would actually export the GPIO controller functionality. Such nodes should have traditional GPIO controller properties together with optional interrupt-controller attributes if the corresponding controller was synthesized to detect and report the input values change to the parental IRQ controller. Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Reviewed-by: Andy Shevchenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200323195401.30338-2-Sergey.Semin@baikalelectronics.ru Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 129 +++++++++++++++++++++ .../devicetree/bindings/gpio/snps-dwapb-gpio.txt | 65 ----------- 2 files changed, 129 insertions(+), 65 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml delete mode 100644 Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml new file mode 100644 index 000000000000..f84f92c4dd53 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare APB GPIO controller + +description: | + Synopsys DesignWare GPIO controllers have a configurable number of ports, + each of which are intended to be represented as child nodes with the generic + GPIO-controller properties as desribed in this bindings file. + +maintainers: + - Hoan Tran + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: snps,dw-apb-gpio + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + items: + - description: APB interface clock source + + clock-names: + items: + - const: bus + + resets: + maxItems: 1 + +patternProperties: + "^gpio-(port|controller)@[0-9a-f]+$": + type: object + properties: + compatible: + const: snps,dw-apb-gpio-port + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + snps,nr-gpios: + description: The number of GPIO pins exported by the port. + default: 32 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + maximum: 32 + + interrupts: + description: | + The interrupts to the parent controller raised when GPIOs generate + the interrupts. If the controller provides one combined interrupt + for all GPIOs, specify a single interrupt. If the controller provides + one interrupt for each GPIO, provide a list of interrupts that + correspond to each of the GPIO pins. + minItems: 1 + maxItems: 32 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + + dependencies: + interrupt-controller: [ interrupts ] + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +examples: + - | + gpio: gpio@20000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&vic1>; + interrupts = <0>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt deleted file mode 100644 index 839dd32ffe11..000000000000 --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Synopsys DesignWare APB GPIO controller - -Required properties: -- compatible : Should contain "snps,dw-apb-gpio" -- reg : Address and length of the register set for the device. -- #address-cells : should be 1 (for addressing port subnodes). -- #size-cells : should be 0 (port subnodes). - -The GPIO controller has a configurable number of ports, each of which are -represented as child nodes with the following properties: - -Required properties: -- compatible : "snps,dw-apb-gpio-port" -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- reg : The integer port index of the port, a single cell. - -Optional properties: -- interrupt-controller : The first port may be configured to be an interrupt -controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt. Shall be set to 2. The first cell defines the interrupt number, - the second encodes the triger flags encoded as described in - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -- interrupts : The interrupts to the parent controller raised when GPIOs - generate the interrupts. If the controller provides one combined interrupt - for all GPIOs, specify a single interrupt. If the controller provides one - interrupt for each GPIO, provide a list of interrupts that correspond to each - of the GPIO pins. When specifying multiple interrupts, if any are unconnected, - use the interrupts-extended property to specify the interrupts and set the - interrupt controller handle for unused interrupts to 0. -- snps,nr-gpios : The number of pins in the port, a single cell. -- resets : Reset line for the controller. - -Example: - -gpio: gpio@20000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x20000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&vic1>; - interrupts = <0>; - }; - - portb: gpio@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <1>; - }; -}; -- cgit v1.2.3 From 4f18093743673d4e21a5619dc323adb1dc2021e9 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Mon, 23 Mar 2020 22:53:57 +0300 Subject: dt-bindings: gpio: Add DW GPIO debounce clock property Port A of the DW GPIO controller may optionally have a debounce logic enabled if it was synthesized with that functionality enabled. In this case a dedicated reference clock should be declared in the node with corresponding "db" name presented in the clock-names property. Signed-off-by: Serge Semin Reviewed-by: Andy Shevchenko Acked-by: Rob Herring Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Link: https://lore.kernel.org/r/20200323195401.30338-3-Sergey.Semin@baikalelectronics.ru Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml index f84f92c4dd53..58a8df367623 100644 --- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml @@ -31,12 +31,16 @@ properties: maxItems: 1 clocks: + minItems: 1 items: - description: APB interface clock source + - description: DW GPIO debounce reference clock source clock-names: + minItems: 1 items: - const: bus + - const: db resets: maxItems: 1 -- cgit v1.2.3 From c55812afd3954c20c0d06b00ee9271ca6a3d8eab Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Mon, 23 Mar 2020 22:53:58 +0300 Subject: dt-bindings: gpio: Add Sergey Semin to DW APB GPIO driver maintainers Seeing Hoan has been silent for a long time Linus suggested to me to be also maintaining the driver. This patch adds myself to the list of maintainers in the DT schema of the driver. Suggested-by: Linus Walleij Signed-off-by: Serge Semin Reviewed-by: Andy Shevchenko Acked-by: Rob Herring Cc: Hoan Tran Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Link: https://lore.kernel.org/r/20200323195401.30338-4-Sergey.Semin@baikalelectronics.ru Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml index 58a8df367623..04a3c51e1dc1 100644 --- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml @@ -13,6 +13,7 @@ description: | maintainers: - Hoan Tran + - Serge Semin properties: $nodename: -- cgit v1.2.3 From c22fc62b516de5eeea7b518a68e258948e6276ce Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 May 2020 10:11:57 +0200 Subject: dt-bindings: gpio: Add renesas,em-gio bindings Document Device Tree bindings for the Renesas EMMA Mobile General Purpose I/O Interface. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20200519081157.29095-1-geert+renesas@glider.be Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/renesas,em-gio.yaml | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml b/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml new file mode 100644 index 000000000000..8bdef812c87c --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/renesas,em-gio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas EMMA Mobile General Purpose I/O Interface + +maintainers: + - Magnus Damm + +properties: + compatible: + const: renesas,em-gio + + reg: + items: + - description: First set of contiguous registers + - description: Second set of contiguous registers + + interrupts: + items: + - description: Interrupt for the first set of 16 GPIO ports + - description: Interrupt for the second set of 16 GPIO ports + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + ngpios: + minimum: 1 + maximum: 32 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupts + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - ngpios + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + #include + gpio0: gpio@e0050000 { + compatible = "renesas,em-gio"; + reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 32>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + }; -- cgit v1.2.3