From 5986453b7fe495687e4eafad8a3dd1ffd106bc80 Mon Sep 17 00:00:00 2001 From: Stuart Yoder Date: Tue, 5 Mar 2013 16:39:08 -0600 Subject: powerpc/e6500: Add architecture categories for e6500 cores -also define a binding for fsl,eref-* properties Signed-off-by: Stuart Yoder Signed-off-by: Kumar Gala --- .../devicetree/bindings/powerpc/fsl/cpus.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/cpus.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt new file mode 100644 index 000000000000..922c30ad90d1 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt @@ -0,0 +1,22 @@ +=================================================================== +Power Architecture CPU Binding +Copyright 2013 Freescale Semiconductor Inc. + +Power Architecture CPUs in Freescale SOCs are represented in device trees as +per the definition in ePAPR. + +In addition to the ePAPR definitions, the properties defined below may be +present on CPU nodes. + +PROPERTIES + + - fsl,eref-* + Usage: optional + Value type: + Definition: The EREF (EREF: A Programmer.s Reference Manual for + Freescale Power Architecture) defines the architecture for Freescale + Power CPUs. The EREF defines some architecture categories not defined + by the Power ISA. For these EREF-specific categories, the existence of + a property named fsl,eref-[CAT], where [CAT] is the abbreviated category + name with all uppercase letters converted to lowercase, indicates that + the category is supported by the implementation. -- cgit v1.2.3