From 45361a4fe4464180815157654aabbd2afb4848ad Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 May 2013 17:55:22 +0200 Subject: pci: PCIe driver for Marvell Armada 370/XP systems This driver implements the support for the PCIe interfaces on the Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to cover earlier families of Marvell SoCs, such as Dove, Orion and Kirkwood. The driver implements the hw_pci operations needed by the core ARM PCI code to setup PCI devices and get their corresponding IRQs, and the pci_ops operations that are used by the PCI core to read/write the configuration space of PCI devices. Since the PCIe interfaces of Marvell SoCs are completely separate and not linked together in a bus, this driver sets up an emulated PCI host bridge, with one PCI-to-PCI bridge as child for each hardware PCIe interface. In addition, this driver enumerates the different PCIe slots, and for those having a device plugged in, it sets up the necessary address decoding windows, using the mvebu-mbus driver. Signed-off-by: Thomas Petazzoni Acked-by: Bjorn Helgaas Signed-off-by: Jason Cooper --- .../devicetree/bindings/pci/mvebu-pci.txt | 220 +++++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt new file mode 100644 index 000000000000..eb69d92c23e1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -0,0 +1,220 @@ +* Marvell EBU PCIe interfaces + +Mandatory properties: +- compatible: one of the following values: + marvell,armada-370-pcie + marvell,armada-xp-pcie +- #address-cells, set to <3> +- #size-cells, set to <2> +- #interrupt-cells, set to <1> +- bus-range: PCI bus numbers covered +- device_type, set to "pci" +- ranges: ranges for the PCI memory and I/O regions, as well as the + MMIO registers to control the PCIe interfaces. + +In addition, the Device Tree node must have sub-nodes describing each +PCIe interface, having the following mandatory properties: +- reg: used only for interrupt mapping, so only the first four bytes + are used to refer to the correct bus number and device number. +- assigned-addresses: reference to the MMIO registers used to control + this PCIe interface. +- clocks: the clock associated to this PCIe interface +- marvell,pcie-port: the physical PCIe port number +- status: either "disabled" or "okay" +- device_type, set to "pci" +- #address-cells, set to <3> +- #size-cells, set to <2> +- #interrupt-cells, set to <1> +- ranges, empty property. +- interrupt-map-mask and interrupt-map, standard PCI properties to + define the mapping of the PCIe interface to interrupt numbers. + +and the following optional properties: +- marvell,pcie-lane: the physical PCIe lane number, for ports having + multiple lanes. If this property is not found, we assume that the + value is 0. + +Example: + +pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + }; + + pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + }; + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; +}; -- cgit v1.2.3 From 0ee52b157b8ed88550ddd6291e54bb4bfabde364 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Mon, 13 May 2013 10:46:37 -0700 Subject: clk: zynq: Add clock controller driver Add a clock controller driver and documentation. Signed-off-by: Soren Brinkmann Cc: Grant Likely Cc: Rob Herring Cc: Rob Landley Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-doc@vger.kernel.org Signed-off-by: Michal Simek Acked-by: Mike Turquette --- .../devicetree/bindings/clock/zynq-7000.txt | 97 ++++ drivers/clk/zynq/clkc.c | 533 +++++++++++++++++++++ 2 files changed, 630 insertions(+) create mode 100644 drivers/clk/zynq/clkc.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt index 23ae1db1bc13..1049a313933c 100644 --- a/Documentation/devicetree/bindings/clock/zynq-7000.txt +++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt @@ -6,6 +6,103 @@ The purpose of this document is to document their usage. See clock_bindings.txt for more information on the generic clock bindings. See Chapter 25 of Zynq TRM for more information about Zynq clocks. +== Clock Controller == +The clock controller is a logical abstraction of Zynq's clock tree. It reads +required input clock frequencies from the devicetree and acts as clock provider +for all clock consumers of PS clocks. + +Required properties: + - #clock-cells : Must be 1 + - compatible : "xlnx,ps7-clkc" + - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ + (usually 33 MHz oscillators are used for Zynq platforms) + - clock-output-names : List of strings used to name the clock outputs. Shall be + a list of the outputs given below. + +Optional properties: + - clocks : as described in the clock bindings + - clock-names : as described in the clock bindings + +Clock inputs: +The following strings are optional parameters to the 'clock-names' property in +order to provide an optional (E)MIO clock source. + - swdt_ext_clk + - gem0_emio_clk + - gem1_emio_clk + - mio_clk_XX # with XX = 00..53 +... + +Clock outputs: + 0: armpll + 1: ddrpll + 2: iopll + 3: cpu_6or4x + 4: cpu_3or2x + 5: cpu_2x + 6: cpu_1x + 7: ddr2x + 8: ddr3x + 9: dci + 10: lqspi + 11: smc + 12: pcap + 13: gem0 + 14: gem1 + 15: fclk0 + 16: fclk1 + 17: fclk2 + 18: fclk3 + 19: can0 + 20: can1 + 21: sdio0 + 22: sdio1 + 23: uart0 + 24: uart1 + 25: spi0 + 26: spi1 + 27: dma + 28: usb0_aper + 29: usb1_aper + 30: gem0_aper + 31: gem1_aper + 32: sdio0_aper + 33: sdio1_aper + 34: spi0_aper + 35: spi1_aper + 36: can0_aper + 37: can1_aper + 38: i2c0_aper + 39: i2c1_aper + 40: uart0_aper + 41: uart1_aper + 42: gpio_aper + 43: lqspi_aper + 44: smc_aper + 45: swdt + 46: dbg_trc + 47: dbg_apb + +Example: + clkc: clkc { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + # optional props + clocks = <&clkc 16>, <&clk_foo>; + clock-names = "gem1_emio_clk", "can_mio_clk_23"; + }; + == PLLs == Used to describe the ARM_PLL, DDR_PLL, and IO_PLL. diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c new file mode 100644 index 000000000000..5c205b60a82a --- /dev/null +++ b/drivers/clk/zynq/clkc.c @@ -0,0 +1,533 @@ +/* + * Zynq clock controller + * + * Copyright (C) 2012 - 2013 Xilinx + * + * Sören Brinkmann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +static void __iomem *zynq_slcr_base_priv; + +#define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100) +#define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104) +#define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108) +#define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c) +#define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120) +#define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124) +#define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128) +#define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c) +#define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140) +#define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144) +#define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148) +#define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c) +#define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150) +#define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154) +#define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158) +#define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c) +#define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160) +#define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164) +#define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168) +#define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170) +#define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4) +#define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304) + +#define NUM_MIO_PINS 54 + +enum zynq_clk { + armpll, ddrpll, iopll, + cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, + ddr2x, ddr3x, dci, + lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, + sdio0, sdio1, uart0, uart1, spi0, spi1, dma, + usb0_aper, usb1_aper, gem0_aper, gem1_aper, + sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, + i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, + smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; + +static struct clk *ps_clk; +static struct clk *clks[clk_max]; +static struct clk_onecell_data clk_data; + +static DEFINE_SPINLOCK(armpll_lock); +static DEFINE_SPINLOCK(ddrpll_lock); +static DEFINE_SPINLOCK(iopll_lock); +static DEFINE_SPINLOCK(armclk_lock); +static DEFINE_SPINLOCK(ddrclk_lock); +static DEFINE_SPINLOCK(dciclk_lock); +static DEFINE_SPINLOCK(gem0clk_lock); +static DEFINE_SPINLOCK(gem1clk_lock); +static DEFINE_SPINLOCK(canclk_lock); +static DEFINE_SPINLOCK(canmioclk_lock); +static DEFINE_SPINLOCK(dbgclk_lock); +static DEFINE_SPINLOCK(aperclk_lock); + +static const char dummy_nm[] __initconst = "dummy_name"; + +static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"}; +static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"}; +static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"}; +static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm}; +static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm}; +static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate", + "can0_mio_mux"}; +static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate", + "can1_mio_mux"}; +static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", + dummy_nm}; + +static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"}; +static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"}; +static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"}; +static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; + +static void __init zynq_clk_register_fclk(enum zynq_clk fclk, + const char *clk_name, void __iomem *fclk_ctrl_reg, + const char **parents) +{ + struct clk *clk; + char *mux_name; + char *div0_name; + char *div1_name; + spinlock_t *fclk_lock; + spinlock_t *fclk_gate_lock; + void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; + + fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); + if (!fclk_lock) + goto err; + fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); + if (!fclk_gate_lock) + goto err; + spin_lock_init(fclk_lock); + spin_lock_init(fclk_gate_lock); + + mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); + div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); + div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); + + clk = clk_register_mux(NULL, mux_name, parents, 4, 0, + fclk_ctrl_reg, 4, 2, 0, fclk_lock); + + clk = clk_register_divider(NULL, div0_name, mux_name, + 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, fclk_lock); + + clk = clk_register_divider(NULL, div1_name, div0_name, + CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + fclk_lock); + + clks[fclk] = clk_register_gate(NULL, clk_name, + div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, + 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); + kfree(mux_name); + kfree(div0_name); + kfree(div1_name); + + return; + +err: + clks[fclk] = ERR_PTR(-ENOMEM); +} + +static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, + enum zynq_clk clk1, const char *clk_name0, + const char *clk_name1, void __iomem *clk_ctrl, + const char **parents, unsigned int two_gates) +{ + struct clk *clk; + char *mux_name; + char *div_name; + spinlock_t *lock; + + lock = kmalloc(sizeof(*lock), GFP_KERNEL); + if (!lock) + goto err; + spin_lock_init(lock); + + mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); + div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); + + clk = clk_register_mux(NULL, mux_name, parents, 4, 0, + clk_ctrl, 4, 2, 0, lock); + + clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); + + clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, + CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); + if (two_gates) + clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, + CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); + + kfree(mux_name); + kfree(div_name); + + return; + +err: + clks[clk0] = ERR_PTR(-ENOMEM); + if (two_gates) + clks[clk1] = ERR_PTR(-ENOMEM); +} + +static void __init zynq_clk_setup(struct device_node *np) +{ + int i; + u32 tmp; + int ret; + struct clk *clk; + char *clk_name; + const char *clk_output_name[clk_max]; + const char *cpu_parents[4]; + const char *periph_parents[4]; + const char *swdt_ext_clk_mux_parents[2]; + const char *can_mio_mux_parents[NUM_MIO_PINS]; + + pr_info("Zynq clock init\n"); + + /* get clock output names from DT */ + for (i = 0; i < clk_max; i++) { + if (of_property_read_string_index(np, "clock-output-names", + i, &clk_output_name[i])) { + pr_err("%s: clock output name not in DT\n", __func__); + BUG(); + } + } + cpu_parents[0] = clk_output_name[armpll]; + cpu_parents[1] = clk_output_name[armpll]; + cpu_parents[2] = clk_output_name[ddrpll]; + cpu_parents[3] = clk_output_name[iopll]; + periph_parents[0] = clk_output_name[iopll]; + periph_parents[1] = clk_output_name[iopll]; + periph_parents[2] = clk_output_name[armpll]; + periph_parents[3] = clk_output_name[ddrpll]; + + /* ps_clk */ + ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); + if (ret) { + pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); + tmp = 33333333; + } + ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, + tmp); + + /* PLLs */ + clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, + SLCR_PLL_STATUS, 0, &armpll_lock); + clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], + armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0, + &armpll_lock); + + clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, + SLCR_PLL_STATUS, 1, &ddrpll_lock); + clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], + ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0, + &ddrpll_lock); + + clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, + SLCR_PLL_STATUS, 2, &iopll_lock); + clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], + iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0, + &iopll_lock); + + /* CPU clocks */ + tmp = readl(SLCR_621_TRUE) & 1; + clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0, + SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock); + clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, + SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); + + clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], + "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); + + clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, + 1, 2); + clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], + "cpu_3or2x_div", CLK_IGNORE_UNUSED, + SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); + + clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, + 2 + tmp); + clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], + "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, + 26, 0, &armclk_lock); + + clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, + 4 + 2 * tmp); + clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], + "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, + 0, &armclk_lock); + + /* Timers */ + swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; + for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { + int idx = of_property_match_string(np, "clock-names", + swdt_ext_clk_input_names[i]); + if (idx >= 0) + swdt_ext_clk_mux_parents[i + 1] = + of_clk_get_parent_name(np, idx); + else + swdt_ext_clk_mux_parents[i + 1] = dummy_nm; + } + clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], + swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, + SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock); + + /* DDR clocks */ + clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, + SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); + clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], + "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); + clk_prepare_enable(clks[ddr2x]); + clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, + SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); + clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], + "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); + clk_prepare_enable(clks[ddr3x]); + + clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, + SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); + clk = clk_register_divider(NULL, "dci_div1", "dci_div0", + CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &dciclk_lock); + clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", + CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, + &dciclk_lock); + clk_prepare_enable(clks[dci]); + + /* Peripheral clocks */ + for (i = fclk0; i <= fclk3; i++) + zynq_clk_register_fclk(i, clk_output_name[i], + SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), + periph_parents); + + zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, + SLCR_LQSPI_CLK_CTRL, periph_parents, 0); + + zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, + SLCR_SMC_CLK_CTRL, periph_parents, 0); + + zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, + SLCR_PCAP_CLK_CTRL, periph_parents, 0); + + zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], + clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, + periph_parents, 1); + + zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], + clk_output_name[uart1], SLCR_UART_CLK_CTRL, + periph_parents, 1); + + zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], + clk_output_name[spi1], SLCR_SPI_CLK_CTRL, + periph_parents, 1); + + for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { + int idx = of_property_match_string(np, "clock-names", + gem0_emio_input_names[i]); + if (idx >= 0) + gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, + idx); + } + clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0, + SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock); + clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, + SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); + clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", + CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &gem0clk_lock); + clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0, + SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock); + clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], + "gem0_emio_mux", CLK_SET_RATE_PARENT, + SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); + + for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { + int idx = of_property_match_string(np, "clock-names", + gem1_emio_input_names[i]); + if (idx >= 0) + gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, + idx); + } + clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0, + SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock); + clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, + SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); + clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", + CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &gem1clk_lock); + clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0, + SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock); + clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], + "gem1_emio_mux", CLK_SET_RATE_PARENT, + SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); + + tmp = strlen("mio_clk_00x"); + clk_name = kmalloc(tmp, GFP_KERNEL); + for (i = 0; i < NUM_MIO_PINS; i++) { + int idx; + + snprintf(clk_name, tmp, "mio_clk_%2.2d", i); + idx = of_property_match_string(np, "clock-names", clk_name); + if (idx >= 0) + can_mio_mux_parents[i] = of_clk_get_parent_name(np, + idx); + else + can_mio_mux_parents[i] = dummy_nm; + } + kfree(clk_name); + clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0, + SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock); + clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, + SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); + clk = clk_register_divider(NULL, "can_div1", "can_div0", + CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &canclk_lock); + clk = clk_register_gate(NULL, "can0_gate", "can_div1", + CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, + &canclk_lock); + clk = clk_register_gate(NULL, "can1_gate", "can_div1", + CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, + &canclk_lock); + clk = clk_register_mux(NULL, "can0_mio_mux", + can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, + SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock); + clk = clk_register_mux(NULL, "can1_mio_mux", + can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, + SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock); + clks[can0] = clk_register_mux(NULL, clk_output_name[can0], + can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, + SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock); + clks[can1] = clk_register_mux(NULL, clk_output_name[can1], + can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, + SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock); + + for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { + int idx = of_property_match_string(np, "clock-names", + dbgtrc_emio_input_names[i]); + if (idx >= 0) + dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, + idx); + } + clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0, + SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock); + clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, + SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); + clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0, + SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock); + clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], + "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, + 0, 0, &dbgclk_lock); + clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], + clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, + &dbgclk_lock); + + /* One gated clock for all APER clocks. */ + clks[dma] = clk_register_gate(NULL, clk_output_name[dma], + clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, + &aperclk_lock); + clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, + &aperclk_lock); + clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, + &aperclk_lock); + clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, + &aperclk_lock); + clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, + &aperclk_lock); + clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, + &aperclk_lock); + clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, + &aperclk_lock); + clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, + &aperclk_lock); + clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, + &aperclk_lock); + clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, + &aperclk_lock); + clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, + &aperclk_lock); + clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, + &aperclk_lock); + clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, + &aperclk_lock); + clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, + &aperclk_lock); + clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, + &aperclk_lock); + clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, + &aperclk_lock); + clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, + &aperclk_lock); + clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, + &aperclk_lock); + + for (i = 0; i < ARRAY_SIZE(clks); i++) { + if (IS_ERR(clks[i])) { + pr_err("Zynq clk %d: register failed with %ld\n", + i, PTR_ERR(clks[i])); + BUG(); + } + } + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} + +CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); + +void __init zynq_clock_init(void __iomem *slcr_base) +{ + zynq_slcr_base_priv = slcr_base; + of_clk_init(NULL); +} -- cgit v1.2.3 From 97c4e87d45498fb4d18c995721bba72345a7d257 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Mon, 13 May 2013 10:46:39 -0700 Subject: clk: zynq: Remove deprecated clock code Signed-off-by: Soren Brinkmann Cc: Grant Likely Cc: Rob Herring Cc: Rob Landley Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-doc@vger.kernel.org Signed-off-by: Michal Simek Acked-by: Mike Turquette --- .../devicetree/bindings/clock/zynq-7000.txt | 48 --- drivers/clk/clk-zynq.c | 378 --------------------- 2 files changed, 426 deletions(-) delete mode 100644 drivers/clk/clk-zynq.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt index 1049a313933c..d99af878f5d7 100644 --- a/Documentation/devicetree/bindings/clock/zynq-7000.txt +++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt @@ -102,51 +102,3 @@ Example: clocks = <&clkc 16>, <&clk_foo>; clock-names = "gem1_emio_clk", "can_mio_clk_23"; }; - -== PLLs == - -Used to describe the ARM_PLL, DDR_PLL, and IO_PLL. - -Required properties: -- #clock-cells : shall be 0 (only one clock is output from this node) -- compatible : "xlnx,zynq-pll" -- reg : pair of u32 values, which are the address offsets within the SLCR - of the relevant PLL_CTRL register and PLL_CFG register respectively -- clocks : phandle for parent clock. should be the phandle for ps_clk - -Optional properties: -- clock-output-names : name of the output clock - -Example: - armpll: armpll { - #clock-cells = <0>; - compatible = "xlnx,zynq-pll"; - clocks = <&ps_clk>; - reg = <0x100 0x110>; - clock-output-names = "armpll"; - }; - -== Peripheral clocks == - -Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks. - -Required properties: -- #clock-cells : shall be 1 -- compatible : "xlnx,zynq-periph-clock" -- reg : a single u32 value, describing the offset within the SLCR where - the CLK_CTRL register is found for this peripheral -- clocks : phandle for parent clocks. should hold phandles for - the IO_PLL, ARM_PLL, and DDR_PLL in order -- clock-output-names : names of the output clock(s). For peripherals that have - two output clocks (for example, the UART), two clocks - should be listed. - -Example: - uart_clk: uart_clk { - #clock-cells = <1>; - compatible = "xlnx,zynq-periph-clock"; - clocks = <&iopll &armpll &ddrpll>; - reg = <0x154>; - clock-output-names = "uart0_ref_clk", - "uart1_ref_clk"; - }; diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c deleted file mode 100644 index 32062977f453..000000000000 --- a/drivers/clk/clk-zynq.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (c) 2012 National Instruments - * - * Josh Cartwright - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ -#include -#include -#include -#include -#include -#include - -static void __iomem *slcr_base; - -struct zynq_pll_clk { - struct clk_hw hw; - void __iomem *pll_ctrl; - void __iomem *pll_cfg; -}; - -#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw) - -#define CTRL_PLL_FDIV(x) ((x) >> 12) - -static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct zynq_pll_clk *pll = to_zynq_pll_clk(hw); - return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl)); -} - -static const struct clk_ops zynq_pll_clk_ops = { - .recalc_rate = zynq_pll_recalc_rate, -}; - -static void __init zynq_pll_clk_setup(struct device_node *np) -{ - struct clk_init_data init; - struct zynq_pll_clk *pll; - const char *parent_name; - struct clk *clk; - u32 regs[2]; - int ret; - - ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs)); - if (WARN_ON(ret)) - return; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (WARN_ON(!pll)) - return; - - pll->pll_ctrl = slcr_base + regs[0]; - pll->pll_cfg = slcr_base + regs[1]; - - of_property_read_string(np, "clock-output-names", &init.name); - - init.ops = &zynq_pll_clk_ops; - parent_name = of_clk_get_parent_name(np, 0); - init.parent_names = &parent_name; - init.num_parents = 1; - - pll->hw.init = &init; - - clk = clk_register(NULL, &pll->hw); - if (WARN_ON(IS_ERR(clk))) - return; - - ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); - if (WARN_ON(ret)) - return; -} -CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup); - -struct zynq_periph_clk { - struct clk_hw hw; - struct clk_onecell_data onecell_data; - struct clk *gates[2]; - void __iomem *clk_ctrl; - spinlock_t clkact_lock; -}; - -#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw) - -static const u8 periph_clk_parent_map[] = { - 0, 0, 1, 2 -}; -#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4]) -#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) - -static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); - return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl)); -} - -static u8 zynq_periph_get_parent(struct clk_hw *hw) -{ - struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); - return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl)); -} - -static const struct clk_ops zynq_periph_clk_ops = { - .recalc_rate = zynq_periph_recalc_rate, - .get_parent = zynq_periph_get_parent, -}; - -static void __init zynq_periph_clk_setup(struct device_node *np) -{ - struct zynq_periph_clk *periph; - const char *parent_names[3]; - struct clk_init_data init; - int clk_num = 0, err; - const char *name; - struct clk *clk; - u32 reg; - int i; - - err = of_property_read_u32(np, "reg", ®); - if (WARN_ON(err)) - return; - - periph = kzalloc(sizeof(*periph), GFP_KERNEL); - if (WARN_ON(!periph)) - return; - - periph->clk_ctrl = slcr_base + reg; - spin_lock_init(&periph->clkact_lock); - - init.name = np->name; - init.ops = &zynq_periph_clk_ops; - for (i = 0; i < ARRAY_SIZE(parent_names); i++) - parent_names[i] = of_clk_get_parent_name(np, i); - init.parent_names = parent_names; - init.num_parents = ARRAY_SIZE(parent_names); - - periph->hw.init = &init; - - clk = clk_register(NULL, &periph->hw); - if (WARN_ON(IS_ERR(clk))) - return; - - err = of_clk_add_provider(np, of_clk_src_simple_get, clk); - if (WARN_ON(err)) - return; - - err = of_property_read_string_index(np, "clock-output-names", 0, - &name); - if (WARN_ON(err)) - return; - - periph->gates[0] = clk_register_gate(NULL, name, np->name, 0, - periph->clk_ctrl, 0, 0, - &periph->clkact_lock); - if (WARN_ON(IS_ERR(periph->gates[0]))) - return; - clk_num++; - - /* some periph clks have 2 downstream gates */ - err = of_property_read_string_index(np, "clock-output-names", 1, - &name); - if (err != -ENODATA) { - periph->gates[1] = clk_register_gate(NULL, name, np->name, 0, - periph->clk_ctrl, 1, 0, - &periph->clkact_lock); - if (WARN_ON(IS_ERR(periph->gates[1]))) - return; - clk_num++; - } - - periph->onecell_data.clks = periph->gates; - periph->onecell_data.clk_num = clk_num; - - err = of_clk_add_provider(np, of_clk_src_onecell_get, - &periph->onecell_data); - if (WARN_ON(err)) - return; -} -CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup); - -/* CPU Clock domain is modelled as a mux with 4 children subclks, whose - * derivative rates depend on CLK_621_TRUE - */ - -struct zynq_cpu_clk { - struct clk_hw hw; - struct clk_onecell_data onecell_data; - struct clk *subclks[4]; - void __iomem *clk_ctrl; - spinlock_t clkact_lock; -}; - -#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw) - -static const u8 zynq_cpu_clk_parent_map[] = { - 1, 1, 2, 0 -}; -#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)]) -#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) - -static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw) -{ - struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); - return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl)); -} - -static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); - return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl)); -} - -static const struct clk_ops zynq_cpu_clk_ops = { - .get_parent = zynq_cpu_clk_get_parent, - .recalc_rate = zynq_cpu_clk_recalc_rate, -}; - -struct zynq_cpu_subclk { - struct clk_hw hw; - void __iomem *clk_621; - enum { - CPU_SUBCLK_6X4X, - CPU_SUBCLK_3X2X, - CPU_SUBCLK_2X, - CPU_SUBCLK_1X, - } which; -}; - -#define CLK_621_TRUE(x) ((x) & 1) - -#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw); - -static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - unsigned long uninitialized_var(rate); - struct zynq_cpu_subclk *subclk; - bool is_621; - - subclk = to_zynq_cpu_subclk(hw) - is_621 = CLK_621_TRUE(ioread32(subclk->clk_621)); - - switch (subclk->which) { - case CPU_SUBCLK_6X4X: - rate = parent_rate; - break; - case CPU_SUBCLK_3X2X: - rate = parent_rate / 2; - break; - case CPU_SUBCLK_2X: - rate = parent_rate / (is_621 ? 3 : 2); - break; - case CPU_SUBCLK_1X: - rate = parent_rate / (is_621 ? 6 : 4); - break; - }; - - return rate; -} - -static const struct clk_ops zynq_cpu_subclk_ops = { - .recalc_rate = zynq_cpu_subclk_recalc_rate, -}; - -static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which, - void __iomem *clk_621) -{ - struct zynq_cpu_subclk *subclk; - struct clk_init_data init; - struct clk *clk; - int err; - - err = of_property_read_string_index(np, "clock-output-names", - which, &init.name); - if (WARN_ON(err)) - goto err_read_output_name; - - subclk = kzalloc(sizeof(*subclk), GFP_KERNEL); - if (!subclk) - goto err_subclk_alloc; - - subclk->clk_621 = clk_621; - subclk->which = which; - - init.ops = &zynq_cpu_subclk_ops; - init.parent_names = &np->name; - init.num_parents = 1; - - subclk->hw.init = &init; - - clk = clk_register(NULL, &subclk->hw); - if (WARN_ON(IS_ERR(clk))) - goto err_clk_register; - - return clk; - -err_clk_register: - kfree(subclk); -err_subclk_alloc: -err_read_output_name: - return ERR_PTR(-EINVAL); -} - -static void __init zynq_cpu_clk_setup(struct device_node *np) -{ - struct zynq_cpu_clk *cpuclk; - const char *parent_names[3]; - struct clk_init_data init; - void __iomem *clk_621; - struct clk *clk; - u32 reg[2]; - int err; - int i; - - err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); - if (WARN_ON(err)) - return; - - cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); - if (WARN_ON(!cpuclk)) - return; - - cpuclk->clk_ctrl = slcr_base + reg[0]; - clk_621 = slcr_base + reg[1]; - spin_lock_init(&cpuclk->clkact_lock); - - init.name = np->name; - init.ops = &zynq_cpu_clk_ops; - for (i = 0; i < ARRAY_SIZE(parent_names); i++) - parent_names[i] = of_clk_get_parent_name(np, i); - init.parent_names = parent_names; - init.num_parents = ARRAY_SIZE(parent_names); - - cpuclk->hw.init = &init; - - clk = clk_register(NULL, &cpuclk->hw); - if (WARN_ON(IS_ERR(clk))) - return; - - err = of_clk_add_provider(np, of_clk_src_simple_get, clk); - if (WARN_ON(err)) - return; - - for (i = 0; i < 4; i++) { - cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621); - if (WARN_ON(IS_ERR(cpuclk->subclks[i]))) - return; - } - - cpuclk->onecell_data.clks = cpuclk->subclks; - cpuclk->onecell_data.clk_num = i; - - err = of_clk_add_provider(np, of_clk_src_onecell_get, - &cpuclk->onecell_data); - if (WARN_ON(err)) - return; -} -CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup); - -void __init xilinx_zynq_clocks_init(void __iomem *slcr) -{ - slcr_base = slcr; - of_clk_init(NULL); -} -- cgit v1.2.3 From 005625fc5d62220242ec488d112e0a97e7fcd7bc Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 May 2013 15:36:54 +0200 Subject: pci: mvebu: enable driver usage on Kirkwood We allow the pci-mvebu driver to be compiled on the Kirkwood platform, and add the 'marvell,kirkwood-pcie' as a compatible string supported by the driver. Signed-off-by: Thomas Petazzoni Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- Documentation/devicetree/bindings/pci/mvebu-pci.txt | 1 + drivers/pci/host/Kconfig | 2 +- drivers/pci/host/pci-mvebu.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index eb69d92c23e1..f8d405897a94 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -4,6 +4,7 @@ Mandatory properties: - compatible: one of the following values: marvell,armada-370-pcie marvell,armada-xp-pcie + marvell,kirkwood-pcie - #address-cells, set to <3> - #size-cells, set to <2> - #interrupt-cells, set to <1> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 6918fbc92c02..1f1d67fec8b2 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -3,6 +3,6 @@ menu "PCI host controller drivers" config PCI_MVEBU bool "Marvell EBU PCIe controller" - depends on ARCH_MVEBU + depends on ARCH_MVEBU || ARCH_KIRKWOOD endmenu diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index 9236ac0bd17b..c8397c416a71 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -854,6 +854,7 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev) static const struct of_device_id mvebu_pcie_of_match_table[] = { { .compatible = "marvell,armada-xp-pcie", }, { .compatible = "marvell,armada-370-pcie", }, + { .compatible = "marvell,kirkwood-pcie", }, {}, }; MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); -- cgit v1.2.3 From ed69bdd8fd9b2db68b915ce5f60fc51d4744a9b1 Mon Sep 17 00:00:00 2001 From: Lorenzo Pieralisi Date: Fri, 13 Jul 2012 15:55:52 +0100 Subject: drivers: bus: add ARM CCI support On ARM multi-cluster systems coherency between cores running on different clusters is managed by the cache-coherent interconnect (CCI). It allows broadcasting of TLB invalidates and memory barriers and it guarantees cache coherency at system level through snooping of slave interfaces connected to it. This patch enables the basic infrastructure required in Linux to handle and programme the CCI component. Non-local variables used by the CCI management functions called by power down function calls after disabling the cache must be flushed out to main memory in advance, otherwise incoherency of those values may occur if they are sitting in the cache of some other CPU when power down functions execute. Driver code ensures that relevant data structures are flushed from inner and outer caches after the driver probe is completed. CCI slave port resources are linked to set of CPUs through bus masters phandle properties that link the interface resources to masters node in the device tree. Documentation describing the CCI DT bindings is provided with the patch. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Nicolas Pitre --- Documentation/devicetree/bindings/arm/cci.txt | 172 +++++++++++ drivers/bus/Kconfig | 7 + drivers/bus/Makefile | 2 + drivers/bus/arm-cci.c | 426 ++++++++++++++++++++++++++ include/linux/arm-cci.h | 61 ++++ 5 files changed, 668 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cci.txt create mode 100644 drivers/bus/arm-cci.c create mode 100644 include/linux/arm-cci.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt new file mode 100644 index 000000000000..92d36e2aa877 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cci.txt @@ -0,0 +1,172 @@ +======================================================= +ARM CCI cache coherent interconnect binding description +======================================================= + +ARM multi-cluster systems maintain intra-cluster coherency through a +cache coherent interconnect (CCI) that is capable of monitoring bus +transactions and manage coherency, TLB invalidations and memory barriers. + +It allows snooping and distributed virtual memory message broadcast across +clusters, through memory mapped interface, with a global control register +space and multiple sets of interface control registers, one per slave +interface. + +Bindings for the CCI node follow the ePAPR standard, available from: + +www.power.org/documentation/epapr-version-1-1/ + +with the addition of the bindings described in this document which are +specific to ARM. + +* CCI interconnect node + + Description: Describes a CCI cache coherent Interconnect component + + Node name must be "cci". + Node's parent must be the root node /, and the address space visible + through the CCI interconnect is the same as the one seen from the + root node (ie from CPUs perspective as per DT standard). + Every CCI node has to define the following properties: + + - compatible + Usage: required + Value type: + Definition: must be set to + "arm,cci-400" + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies base physical + address of CCI control registers common to all + interfaces. + + - ranges: + Usage: required + Value type: + Definition: A standard property. Follow rules in the ePAPR for + hierarchical bus addressing. CCI interfaces + addresses refer to the parent node addressing + scheme to declare their register bases. + + CCI interconnect node can define the following child nodes: + + - CCI control interface nodes + + Node name must be "slave-if". + Parent node must be CCI interconnect node. + + A CCI control interface node must contain the following + properties: + + - compatible + Usage: required + Value type: + Definition: must be set to + "arm,cci-400-ctrl-if" + + - interface-type: + Usage: required + Value type: + Definition: must be set to one of {"ace", "ace-lite"} + depending on the interface type the node + represents. + + - reg: + Usage: required + Value type: + Definition: the base address and size of the + corresponding interface programming + registers. + +* CCI interconnect bus masters + + Description: masters in the device tree connected to a CCI port + (inclusive of CPUs and their cpu nodes). + + A CCI interconnect bus master node must contain the following + properties: + + - cci-control-port: + Usage: required + Value type: + Definition: a phandle containing the CCI control interface node + the master is connected to. + +Example: + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + cci-control-port = <&cci_control1>; + reg = <0x0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + cci-control-port = <&cci_control1>; + reg = <0x1>; + }; + + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + cci-control-port = <&cci_control2>; + reg = <0x100>; + }; + + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + cci-control-port = <&cci_control2>; + reg = <0x101>; + }; + + }; + + dma0: dma@3000000 { + compatible = "arm,pl330", "arm,primecell"; + cci-control-port = <&cci_control0>; + reg = <0x0 0x3000000 0x0 0x1000>; + interrupts = <10>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + cci@2c090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x6000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + +This CCI node corresponds to a CCI component whose control registers sits +at address 0x000000002c090000. +CCI slave interface @0x000000002c091000 is connected to dma controller dma0. +CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1}; +CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3}; diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index b05ecab915c4..5286e2d333b0 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -26,4 +26,11 @@ config OMAP_INTERCONNECT help Driver to enable OMAP interconnect error handling driver. + +config ARM_CCI + bool "ARM CCI driver support" + depends on ARM + help + Driver supporting the CCI cache coherent interconnect for ARM + platforms. endmenu diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 3c7b53c12091..670cea443802 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -7,3 +7,5 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o # Interconnect bus driver for OMAP SoCs. obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o +# CCI cache coherent interconnect for ARM platforms +obj-$(CONFIG_ARM_CCI) += arm-cci.o diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c new file mode 100644 index 000000000000..ea81fa4a28db --- /dev/null +++ b/drivers/bus/arm-cci.c @@ -0,0 +1,426 @@ +/* + * CCI cache coherent interconnect driver + * + * Copyright (C) 2013 ARM Ltd. + * Author: Lorenzo Pieralisi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define CCI_PORT_CTRL 0x0 +#define CCI_CTRL_STATUS 0xc + +#define CCI_ENABLE_SNOOP_REQ 0x1 +#define CCI_ENABLE_DVM_REQ 0x2 +#define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ) + +struct cci_nb_ports { + unsigned int nb_ace; + unsigned int nb_ace_lite; +}; + +enum cci_ace_port_type { + ACE_INVALID_PORT = 0x0, + ACE_PORT, + ACE_LITE_PORT, +}; + +struct cci_ace_port { + void __iomem *base; + enum cci_ace_port_type type; + struct device_node *dn; +}; + +static struct cci_ace_port *ports; +static unsigned int nb_cci_ports; + +static void __iomem *cci_ctrl_base; + +struct cpu_port { + u64 mpidr; + u32 port; +}; +/* + * Use the port MSB as valid flag, shift can be made dynamic + * by computing number of bits required for port indexes. + * Code disabling CCI cpu ports runs with D-cache invalidated + * and SCTLR bit clear so data accesses must be kept to a minimum + * to improve performance; for now shift is left static to + * avoid one more data access while disabling the CCI port. + */ +#define PORT_VALID_SHIFT 31 +#define PORT_VALID (0x1 << PORT_VALID_SHIFT) + +static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr) +{ + port->port = PORT_VALID | index; + port->mpidr = mpidr; +} + +static inline bool cpu_port_is_valid(struct cpu_port *port) +{ + return !!(port->port & PORT_VALID); +} + +static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr) +{ + return port->mpidr == (mpidr & MPIDR_HWID_BITMASK); +} + +static struct cpu_port cpu_port[NR_CPUS]; + +/** + * __cci_ace_get_port - Function to retrieve the port index connected to + * a cpu or device. + * + * @dn: device node of the device to look-up + * @type: port type + * + * Return value: + * - CCI port index if success + * - -ENODEV if failure + */ +static int __cci_ace_get_port(struct device_node *dn, int type) +{ + int i; + bool ace_match; + struct device_node *cci_portn; + + cci_portn = of_parse_phandle(dn, "cci-control-port", 0); + for (i = 0; i < nb_cci_ports; i++) { + ace_match = ports[i].type == type; + if (ace_match && cci_portn == ports[i].dn) + return i; + } + return -ENODEV; +} + +int cci_ace_get_port(struct device_node *dn) +{ + return __cci_ace_get_port(dn, ACE_LITE_PORT); +} +EXPORT_SYMBOL_GPL(cci_ace_get_port); + +static void __init cci_ace_init_ports(void) +{ + int port, ac, cpu; + u64 hwid; + const u32 *cell; + struct device_node *cpun, *cpus; + + cpus = of_find_node_by_path("/cpus"); + if (WARN(!cpus, "Missing cpus node, bailing out\n")) + return; + + if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac))) + ac = of_n_addr_cells(cpus); + + /* + * Port index look-up speeds up the function disabling ports by CPU, + * since the logical to port index mapping is done once and does + * not change after system boot. + * The stashed index array is initialized for all possible CPUs + * at probe time. + */ + for_each_child_of_node(cpus, cpun) { + if (of_node_cmp(cpun->type, "cpu")) + continue; + cell = of_get_property(cpun, "reg", NULL); + if (WARN(!cell, "%s: missing reg property\n", cpun->full_name)) + continue; + + hwid = of_read_number(cell, ac); + cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK); + + if (cpu < 0 || !cpu_possible(cpu)) + continue; + port = __cci_ace_get_port(cpun, ACE_PORT); + if (port < 0) + continue; + + init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu)); + } + + for_each_possible_cpu(cpu) { + WARN(!cpu_port_is_valid(&cpu_port[cpu]), + "CPU %u does not have an associated CCI port\n", + cpu); + } +} +/* + * Functions to enable/disable a CCI interconnect slave port + * + * They are called by low-level power management code to disable slave + * interfaces snoops and DVM broadcast. + * Since they may execute with cache data allocation disabled and + * after the caches have been cleaned and invalidated the functions provide + * no explicit locking since they may run with D-cache disabled, so normal + * cacheable kernel locks based on ldrex/strex may not work. + * Locking has to be provided by BSP implementations to ensure proper + * operations. + */ + +/** + * cci_port_control() - function to control a CCI port + * + * @port: index of the port to setup + * @enable: if true enables the port, if false disables it + */ +static void notrace cci_port_control(unsigned int port, bool enable) +{ + void __iomem *base = ports[port].base; + + writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL); + /* + * This function is called from power down procedures + * and must not execute any instruction that might + * cause the processor to be put in a quiescent state + * (eg wfi). Hence, cpu_relax() can not be added to this + * read loop to optimize power, since it might hide possibly + * disruptive operations. + */ + while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1) + ; +} + +/** + * cci_disable_port_by_cpu() - function to disable a CCI port by CPU + * reference + * + * @mpidr: mpidr of the CPU whose CCI port should be disabled + * + * Disabling a CCI port for a CPU implies disabling the CCI port + * controlling that CPU cluster. Code disabling CPU CCI ports + * must make sure that the CPU running the code is the last active CPU + * in the cluster ie all other CPUs are quiescent in a low power state. + * + * Return: + * 0 on success + * -ENODEV on port look-up failure + */ +int notrace cci_disable_port_by_cpu(u64 mpidr) +{ + int cpu; + bool is_valid; + for (cpu = 0; cpu < nr_cpu_ids; cpu++) { + is_valid = cpu_port_is_valid(&cpu_port[cpu]); + if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) { + cci_port_control(cpu_port[cpu].port, false); + return 0; + } + } + return -ENODEV; +} +EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu); + +/** + * __cci_control_port_by_device() - function to control a CCI port by device + * reference + * + * @dn: device node pointer of the device whose CCI port should be + * controlled + * @enable: if true enables the port, if false disables it + * + * Return: + * 0 on success + * -ENODEV on port look-up failure + */ +int notrace __cci_control_port_by_device(struct device_node *dn, bool enable) +{ + int port; + + if (!dn) + return -ENODEV; + + port = __cci_ace_get_port(dn, ACE_LITE_PORT); + if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n", + dn->full_name)) + return -ENODEV; + cci_port_control(port, enable); + return 0; +} +EXPORT_SYMBOL_GPL(__cci_control_port_by_device); + +/** + * __cci_control_port_by_index() - function to control a CCI port by port index + * + * @port: port index previously retrieved with cci_ace_get_port() + * @enable: if true enables the port, if false disables it + * + * Return: + * 0 on success + * -ENODEV on port index out of range + * -EPERM if operation carried out on an ACE PORT + */ +int notrace __cci_control_port_by_index(u32 port, bool enable) +{ + if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT) + return -ENODEV; + /* + * CCI control for ports connected to CPUS is extremely fragile + * and must be made to go through a specific and controlled + * interface (ie cci_disable_port_by_cpu(); control by general purpose + * indexing is therefore disabled for ACE ports. + */ + if (ports[port].type == ACE_PORT) + return -EPERM; + + cci_port_control(port, enable); + return 0; +} +EXPORT_SYMBOL_GPL(__cci_control_port_by_index); + +static const struct cci_nb_ports cci400_ports = { + .nb_ace = 2, + .nb_ace_lite = 3 +}; + +static const struct of_device_id arm_cci_matches[] = { + {.compatible = "arm,cci-400", .data = &cci400_ports }, + {}, +}; + +static const struct of_device_id arm_cci_ctrl_if_matches[] = { + {.compatible = "arm,cci-400-ctrl-if", }, + {}, +}; + +static int __init cci_probe(void) +{ + struct cci_nb_ports const *cci_config; + int ret, i, nb_ace = 0, nb_ace_lite = 0; + struct device_node *np, *cp; + const char *match_str; + bool is_ace; + + np = of_find_matching_node(NULL, arm_cci_matches); + if (!np) + return -ENODEV; + + cci_config = of_match_node(arm_cci_matches, np)->data; + if (!cci_config) + return -ENODEV; + + nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite; + + ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL); + if (!ports) + return -ENOMEM; + + cci_ctrl_base = of_iomap(np, 0); + + if (!cci_ctrl_base) { + WARN(1, "unable to ioremap CCI ctrl\n"); + ret = -ENXIO; + goto memalloc_err; + } + + for_each_child_of_node(np, cp) { + if (!of_match_node(arm_cci_ctrl_if_matches, cp)) + continue; + + i = nb_ace + nb_ace_lite; + + if (i >= nb_cci_ports) + break; + + if (of_property_read_string(cp, "interface-type", + &match_str)) { + WARN(1, "node %s missing interface-type property\n", + cp->full_name); + continue; + } + is_ace = strcmp(match_str, "ace") == 0; + if (!is_ace && strcmp(match_str, "ace-lite")) { + WARN(1, "node %s containing invalid interface-type property, skipping it\n", + cp->full_name); + continue; + } + + ports[i].base = of_iomap(cp, 0); + + if (!ports[i].base) { + WARN(1, "unable to ioremap CCI port %d\n", i); + continue; + } + + if (is_ace) { + if (WARN_ON(nb_ace >= cci_config->nb_ace)) + continue; + ports[i].type = ACE_PORT; + ++nb_ace; + } else { + if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite)) + continue; + ports[i].type = ACE_LITE_PORT; + ++nb_ace_lite; + } + ports[i].dn = cp; + } + + /* initialize a stashed array of ACE ports to speed-up look-up */ + cci_ace_init_ports(); + + /* + * Multi-cluster systems may need this data when non-coherent, during + * cluster power-up/power-down. Make sure it reaches main memory. + */ + sync_cache_w(&cci_ctrl_base); + sync_cache_w(&ports); + sync_cache_w(&cpu_port); + __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports); + pr_info("ARM CCI driver probed\n"); + return 0; + +memalloc_err: + + kfree(ports); + return ret; +} + +static int cci_init_status = -EAGAIN; +static DEFINE_MUTEX(cci_probing); + +static int __init cci_init(void) +{ + if (cci_init_status != -EAGAIN) + return cci_init_status; + + mutex_lock(&cci_probing); + if (cci_init_status == -EAGAIN) + cci_init_status = cci_probe(); + mutex_unlock(&cci_probing); + return cci_init_status; +} + +/* + * To sort out early init calls ordering a helper function is provided to + * check if the CCI driver has beed initialized. Function check if the driver + * has been initialized, if not it calls the init function that probes + * the driver and updates the return value. + */ +bool __init cci_probed(void) +{ + return cci_init() == 0; +} +EXPORT_SYMBOL_GPL(cci_probed); + +early_initcall(cci_init); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ARM CCI support"); diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h new file mode 100644 index 000000000000..79d6edf446d5 --- /dev/null +++ b/include/linux/arm-cci.h @@ -0,0 +1,61 @@ +/* + * CCI cache coherent interconnect support + * + * Copyright (C) 2013 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_ARM_CCI_H +#define __LINUX_ARM_CCI_H + +#include +#include + +struct device_node; + +#ifdef CONFIG_ARM_CCI +extern bool cci_probed(void); +extern int cci_ace_get_port(struct device_node *dn); +extern int cci_disable_port_by_cpu(u64 mpidr); +extern int __cci_control_port_by_device(struct device_node *dn, bool enable); +extern int __cci_control_port_by_index(u32 port, bool enable); +#else +static inline bool cci_probed(void) { return false; } +static inline int cci_ace_get_port(struct device_node *dn) +{ + return -ENODEV; +} +static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; } +static inline int __cci_control_port_by_device(struct device_node *dn, + bool enable) +{ + return -ENODEV; +} +static inline int __cci_control_port_by_index(u32 port, bool enable) +{ + return -ENODEV; +} +#endif +#define cci_disable_port_by_device(dev) \ + __cci_control_port_by_device(dev, false) +#define cci_enable_port_by_device(dev) \ + __cci_control_port_by_device(dev, true) +#define cci_disable_port_by_index(dev) \ + __cci_control_port_by_index(dev, false) +#define cci_enable_port_by_index(dev) \ + __cci_control_port_by_index(dev, true) + +#endif -- cgit v1.2.3 From 1e904e1bf6f1285cc2dd5696c44b7cf78cda643f Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 2 May 2012 20:56:52 -0400 Subject: ARM: vexpress: introduce DCSCB support This adds basic CPU and cluster reset controls on RTSM for the A15x4-A7x4 model configuration using the Dual Cluster System Configuration Block (DCSCB). The cache coherency interconnect (CCI) is not handled yet. Signed-off-by: Nicolas Pitre Reviewed-by: Santosh Shilimkar Acked-by: Pawel Moll --- .../devicetree/bindings/arm/rtsm-dcscb.txt | 19 +++ arch/arm/mach-vexpress/Kconfig | 8 + arch/arm/mach-vexpress/Makefile | 1 + arch/arm/mach-vexpress/dcscb.c | 164 +++++++++++++++++++++ 4 files changed, 192 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/rtsm-dcscb.txt create mode 100644 arch/arm/mach-vexpress/dcscb.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt new file mode 100644 index 000000000000..3b8fbf3c00c5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt @@ -0,0 +1,19 @@ +ARM Dual Cluster System Configuration Block +------------------------------------------- + +The Dual Cluster System Configuration Block (DCSCB) provides basic +functionality for controlling clocks, resets and configuration pins in +the Dual Cluster System implemented by the Real-Time System Model (RTSM). + +Required properties: + +- compatible : should be "arm,rtsm,dcscb" + +- reg : physical base address and the size of the registers window + +Example: + + dcscb@60000000 { + compatible = "arm,rtsm,dcscb"; + reg = <0x60000000 0x1000>; + }; diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 5907e10c37fd..2f46385c2819 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -57,4 +57,12 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA config ARCH_VEXPRESS_CA9X4 bool "Versatile Express Cortex-A9x4 tile" +config ARCH_VEXPRESS_DCSCB + bool "Dual Cluster System Control Block (DCSCB) support" + depends on MCPM + help + Support for the Dual Cluster System Configuration Block (DCSCB). + This is needed to provide CPU and cluster power management + on RTSM implementing big.LITTLE. + endmenu diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index 42703e8b4d3b..518519f57a5e 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile @@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ obj-y := v2m.o obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c new file mode 100644 index 000000000000..2ca4bbce530c --- /dev/null +++ b/arch/arm/mach-vexpress/dcscb.c @@ -0,0 +1,164 @@ +/* + * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block + * + * Created by: Nicolas Pitre, May 2012 + * Copyright: (C) 2012-2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +#define RST_HOLD0 0x0 +#define RST_HOLD1 0x4 +#define SYS_SWRESET 0x8 +#define RST_STAT0 0xc +#define RST_STAT1 0x10 +#define EAG_CFG_R 0x20 +#define EAG_CFG_W 0x24 +#define KFC_CFG_R 0x28 +#define KFC_CFG_W 0x2c +#define DCS_CFG_R 0x30 + +/* + * We can't use regular spinlocks. In the switcher case, it is possible + * for an outbound CPU to call power_down() while its inbound counterpart + * is already live using the same logical CPU number which trips lockdep + * debugging. + */ +static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED; + +static void __iomem *dcscb_base; + +static int dcscb_power_up(unsigned int cpu, unsigned int cluster) +{ + unsigned int rst_hold, cpumask = (1 << cpu); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cpu >= 4 || cluster >= 2) + return -EINVAL; + + /* + * Since this is called with IRQs enabled, and no arch_spin_lock_irq + * variant exists, we need to disable IRQs manually here. + */ + local_irq_disable(); + arch_spin_lock(&dcscb_lock); + + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + if (rst_hold & (1 << 8)) { + /* remove cluster reset and add individual CPU's reset */ + rst_hold &= ~(1 << 8); + rst_hold |= 0xf; + } + rst_hold &= ~(cpumask | (cpumask << 4)); + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); + + arch_spin_unlock(&dcscb_lock); + local_irq_enable(); + + return 0; +} + +static void dcscb_power_down(void) +{ + unsigned int mpidr, cpu, cluster, rst_hold, cpumask, last_man; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + cpumask = (1 << cpu); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cpu >= 4 || cluster >= 2); + + arch_spin_lock(&dcscb_lock); + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + rst_hold |= cpumask; + if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf) + rst_hold |= (1 << 8); + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); + arch_spin_unlock(&dcscb_lock); + last_man = (rst_hold & (1 << 8)); + + /* + * Now let's clean our L1 cache and shut ourself down. + * If we're the last CPU in this cluster then clean L2 too. + */ + + /* + * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need + * a preliminary flush here for those CPUs. At least, that's + * the theory -- without the extra flush, Linux explodes on + * RTSM (to be investigated).. + */ + flush_cache_louis(); + set_cr(get_cr() & ~CR_C); + + if (!last_man) { + flush_cache_louis(); + } else { + flush_cache_all(); + outer_flush_all(); + } + + /* Disable local coherency by clearing the ACTLR "SMP" bit: */ + set_auxcr(get_auxcr() & ~(1 << 6)); + + /* Now we are prepared for power-down, do it: */ + dsb(); + wfi(); + + /* Not dead at this point? Let our caller cope. */ +} + +static const struct mcpm_platform_ops dcscb_power_ops = { + .power_up = dcscb_power_up, + .power_down = dcscb_power_down, +}; + +static int __init dcscb_init(void) +{ + struct device_node *node; + int ret; + + node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb"); + if (!node) + return -ENODEV; + dcscb_base = of_iomap(node, 0); + if (!dcscb_base) + return -EADDRNOTAVAIL; + + ret = mcpm_platform_register(&dcscb_power_ops); + if (ret) { + iounmap(dcscb_base); + return ret; + } + + pr_info("VExpress DCSCB support installed\n"); + + /* + * Future entries into the kernel can now go + * through the cluster entry vectors. + */ + vexpress_flags_set(virt_to_phys(mcpm_entry_point)); + + return 0; +} + +early_initcall(dcscb_init); -- cgit v1.2.3 From 5a5056cccfb0479f52a0464a6b371b441c84aa0c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 8 Apr 2013 10:50:11 +0200 Subject: ARM: u300: device tree support for the timer This adds device tree support for the U300 timer, by making the memory base offset and IRQ dynamically assigned, then optionally looking them up from the device tree. Since the timer needs to be registered before any platform devices are created, we will go into the device tree and look up the "/timer@c0014000" node and read our base address and IRQ from there. Signed-off-by: Linus Walleij --- .../bindings/timer/stericsson-u300-apptimer.txt | 18 ++++ arch/arm/Kconfig | 1 + arch/arm/mach-u300/timer.c | 109 ++++++++++++++------- arch/arm/mach-u300/timer.h | 1 + 4 files changed, 91 insertions(+), 38 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt new file mode 100644 index 000000000000..9499bc8ee9e3 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt @@ -0,0 +1,18 @@ +ST-Ericsson U300 apptimer + +Required properties: + +- compatible : should be "stericsson,u300-apptimer" +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 4 interrupts; one for each subtimer. These + are, in order: OS (operating system), DD (device driver) both + adopted for EPOC/Symbian with two specific IRQs for these tasks, + then GP1 and GP2, which are general-purpose timers. + +Example: + +timer { + compatible = "stericsson,u300-apptimer"; + reg = <0xc0014000 0x1000>; + interrupts = <24 25 26 27>; +}; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d423d58f938d..fbad3337a838 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -821,6 +821,7 @@ config ARCH_U300 select ARM_VIC select CLKDEV_LOOKUP select CLKSRC_MMIO + select CLKSRC_OF select COMMON_CLK select CPU_ARM926T select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index c3d3802b46a0..df1e3b5427b6 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include @@ -190,6 +192,8 @@ #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) #define US_PER_TICK ((1000000 + (HZ/2)) / HZ) +static void __iomem *u300_timer_base; + /* * The u300_set_mode() function is always called first, if we * have oneshot timer active, the oneshot scheduling function @@ -202,28 +206,28 @@ static void u300_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_PERIODIC: /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* * Set the periodic mode to a certain number of ticks per * jiffy. */ writel(TICKS_PER_JIFFY, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + u300_timer_base + U300_TIMER_APP_GPT1TC); /* * Set continuous mode, so the timer keeps triggering * interrupts. */ writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable timer interrupts */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Then enable the OS timer again */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); break; case CLOCK_EVT_MODE_ONESHOT: /* Just break; here? */ @@ -234,33 +238,33 @@ static void u300_set_mode(enum clock_event_mode mode, */ /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* * Expire far in the future, u300_set_next_event() will be * called soon... */ - writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); /* We run one shot per tick here! */ writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable interrupts for this timer */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Enable timer */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: /* Disable interrupts on GP1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); break; case CLOCK_EVT_MODE_RESUME: /* Ignore this call */ @@ -282,27 +286,27 @@ static int u300_set_next_event(unsigned long cycles, { /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* Reset the General Purpose timer 1. */ writel(U300_TIMER_APP_RGPT1_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); + u300_timer_base + U300_TIMER_APP_RGPT1); /* IRQ in n * cycles */ - writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC); /* * We run one shot per tick here! (This is necessary to reconfigure, * the timer will tilt if you don't!) */ writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable timer interrupts */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Then enable the OS timer again */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); return 0; } @@ -321,8 +325,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = &clockevent_u300_1mhz; /* ACK/Clear timer IRQ for the APP GPT1 Timer */ + writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA); + u300_timer_base + U300_TIMER_APP_GPT1IA); evt->event_handler(evt); return IRQ_HANDLED; } @@ -343,12 +348,12 @@ static struct irqaction u300_timer_irq = { static u32 notrace u300_read_sched_clock(void) { - return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); + return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); } static unsigned long u300_read_current_timer(void) { - return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); + return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); } static struct delay_timer u300_delay_timer; @@ -356,11 +361,14 @@ static struct delay_timer u300_delay_timer; /* * This sets up the system timers, clock source and clock event. */ -void __init u300_timer_init(void) +static void __init u300_timer_setup(void __iomem *base, int irq) { struct clk *clk; unsigned long rate; + u300_timer_base = base; + pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq); + /* Clock the interrupt controller */ clk = clk_get_sys("apptimer", NULL); BUG_ON(IS_ERR(clk)); @@ -378,40 +386,40 @@ void __init u300_timer_init(void) * Example usage in cnh1601578 cpu subsystem pd_timer_app.c */ writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC); + u300_timer_base + U300_TIMER_APP_CRC); writel(U300_TIMER_APP_ROST_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST); + u300_timer_base + U300_TIMER_APP_ROST); writel(U300_TIMER_APP_DOST_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST); + u300_timer_base + U300_TIMER_APP_DOST); writel(U300_TIMER_APP_RDDT_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT); + u300_timer_base + U300_TIMER_APP_RDDT); writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT); + u300_timer_base + U300_TIMER_APP_DDDT); /* Reset the General Purpose timer 1. */ writel(U300_TIMER_APP_RGPT1_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); + u300_timer_base + U300_TIMER_APP_RGPT1); /* Set up the IRQ handler */ - setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq); + setup_irq(irq, &u300_timer_irq); /* Reset the General Purpose timer 2 */ writel(U300_TIMER_APP_RGPT2_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2); + u300_timer_base + U300_TIMER_APP_RGPT2); /* Set this timer to run around forever */ - writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC); + writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC); /* Set continuous mode so it wraps around */ writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M); + u300_timer_base + U300_TIMER_APP_SGPT2M); /* Disable timer interrupts */ writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE); + u300_timer_base + U300_TIMER_APP_GPT2IE); /* Then enable the GP2 timer to use as a free running us counter */ writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); + u300_timer_base + U300_TIMER_APP_EGPT2); /* Use general purpose timer 2 as clock source */ - if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, + if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC, "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) pr_err("timer: failed to initialize U300 clock source\n"); @@ -424,3 +432,28 @@ void __init u300_timer_init(void) * used by hrtimers! */ } + + +void __init u300_timer_init() +{ + u300_timer_setup(U300_TIMER_APP_VBASE, IRQ_U300_TIMER_APP_GP1); +} + +#ifdef CONFIG_OF + +static void __init u300_timer_init_of(struct device_node *np) +{ + void __iomem *base; + struct resource irq_res; + int irq; + + base = of_iomap(np, 0); + /* Get the IRQ for the GP1 timer */ + irq = of_irq_to_resource(np, 2, &irq_res); + u300_timer_setup(base, irq); +} + +CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer", + u300_timer_init_of); + +#endif diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h index d34287bc34f5..7766dfa6979d 100644 --- a/arch/arm/mach-u300/timer.h +++ b/arch/arm/mach-u300/timer.h @@ -1 +1,2 @@ extern void u300_timer_init(void); + -- cgit v1.2.3 From 351c2163f918e2a4218e0206f854dbec7799fda8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 10 Apr 2013 10:49:31 +0200 Subject: pinctrl: coh901: add device tree support This makes it possible to probe the COH901 pinctrl driver from the device tree, and assigned the device tree node in the gpio_chip so we can look up cross-references from the device tree. Start grabbing the per-port (bank) IRQs by index instead of by name so we don't have to look up the IRQs by name going forward. Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-stericsson-coh901.txt | 7 +++++++ drivers/pinctrl/pinctrl-coh901.c | 12 ++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt new file mode 100644 index 000000000000..fd665b44d767 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt @@ -0,0 +1,7 @@ +ST-Ericsson COH 901 571/3 GPIO controller + +Required properties: +- compatible: Compatible property value should be "stericsson,gpio-coh901" +- reg: Physical base address of the controller and length of memory mapped + region. +- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks. diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index edde3acc4186..d4f8afdad1ad 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -773,8 +773,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev) port->number = portno; port->gpio = gpio; - port->irq = platform_get_irq_byname(pdev, - port->name); + port->irq = platform_get_irq(pdev, portno); dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, port->name); @@ -811,6 +810,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev) } dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); +#ifdef CONFIG_OF_GPIO + gpio->chip.of_node = pdev->dev.of_node; +#endif err = gpiochip_add(&gpio->chip); if (err) { dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); @@ -864,9 +866,15 @@ static int __exit u300_gpio_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id u300_gpio_match[] = { + { .compatible = "stericsson,gpio-coh901" }, + {}, +}; + static struct platform_driver u300_gpio_driver = { .driver = { .name = "u300-gpio", + .of_match_table = u300_gpio_match, }, .remove = __exit_p(u300_gpio_remove), }; -- cgit v1.2.3 From 978577ea21fb05c12511c25b71e493859e36892f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 8 Apr 2013 11:38:50 +0200 Subject: ARM: u300: basic device tree support This register the most basic peripherals and makes the U300 boot to prompt from a device tree. Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/ste-u300.txt | 9 +++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/ste-u300.dts | 86 ++++++++++++++++++++++ arch/arm/mach-u300/core.c | 81 ++++++++++++++++++++ 4 files changed, 177 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/ste-u300.txt create mode 100644 arch/arm/boot/dts/ste-u300.dts (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt new file mode 100644 index 000000000000..222dca558576 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ste-u300.txt @@ -0,0 +1,9 @@ +ST-Ericsson U300 Device Tree Bindings + +For various board the "board" node may contain specific properties +that pertain to this particular board, such as board-specific GPIOs +or board power regulator supplies. + +Required root node property: + +compatible="stericsson,u300"; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9f7121e6ecf..3dd1316a5a27 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -197,6 +197,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra114-pluto.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ versatile-pb.dtb +dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts new file mode 100644 index 000000000000..9e423eb5aa0a --- /dev/null +++ b/arch/arm/boot/dts/ste-u300.dts @@ -0,0 +1,86 @@ +/* + * Device Tree for the ST-Ericsson U300 Machine and SoC + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "ST-Ericsson U300"; + compatible = "stericsson,u300"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory { + reg = <0x48000000 0x03c00000>; + }; + + timer: timer@c0014000 { + compatible = "stericsson,u300-apptimer"; + reg = <0xc0014000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <24 25 26 27>; + }; + + gpio: gpio@c0016000 { + compatible = "stericsson,gpio-coh901"; + reg = <0xc0016000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <0 1 2 18 21 22 23>; + interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pinctrl: pinctrl@c0011000 { + compatible = "stericsson,pinctrl-u300"; + reg = <0xc0011000 0x1000>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vica: interrupt-controller@a0001000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xa0001000 0x20>; + }; + + vicb: interrupt-controller@a0002000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xa0002000 0x20>; + }; + + uart0: serial@c0013000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xc0013000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <22>; + }; + + uart1: serial@c0007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xc0007000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <20>; + }; + }; +}; diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index a683d17b2ce4..a210b1c4ccf4 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -33,6 +33,9 @@ #include #include #include +#include +#include +#include #include #include @@ -698,3 +701,81 @@ MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board") .init_machine = u300_init_machine, .restart = u300_restart, MACHINE_END + +#ifdef CONFIG_OF + +/* These are mostly to get the right device names for the clock lookups */ +static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE, + "pinctrl-u300", NULL), + OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE, + "u300-gpio", &u300_gpio_plat), + OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE, + "uart0", &uart0_plat_data), + OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE, + "uart1", &uart1_plat_data), + OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE, + "mmci", &mmcsd_platform_data), + { /* sentinel */ }, +}; + +static void __init u300_init_irq_dt(void) +{ + struct clk *clk; + + /* initialize clocking early, we want to clock the INTCON */ + u300_clk_init(U300_SYSCON_VBASE); + + /* Bootstrap EMIF and SEMI clocks */ + clk = clk_get_sys("pl172", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + clk = clk_get_sys("semi", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + + /* Clock the interrupt controller */ + clk = clk_get_sys("intcon", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + + irqchip_init(); +} + +static void __init u300_init_machine_dt(void) +{ + u16 val; + + /* Check what platform we run and print some status information */ + u300_init_check_chip(); + + u300_assign_physmem(); + + /* Initialize pinmuxing */ + pinctrl_register_mappings(u300_pinmux_map, + ARRAY_SIZE(u300_pinmux_map)); + + of_platform_populate(NULL, of_default_bus_match_table, + u300_auxdata_lookup, NULL); + + /* Enable SEMI self refresh */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) | + U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR); +} + +static const char * u300_board_compat[] = { + "stericsson,u300", + NULL, +}; + +DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)") + .map_io = u300_map_io, + .init_irq = u300_init_irq_dt, + .init_time = clocksource_of_init, + .init_machine = u300_init_machine_dt, + .restart = u300_restart, + .dt_compat = u300_board_compat, +MACHINE_END + +#endif /* CONFIG_OF */ -- cgit v1.2.3 From 8c58d891576c726bb8217842e955827ba8bb405a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 11 Apr 2013 14:59:47 +0200 Subject: i2c: stu300: device tree support This adds device tree support for the ST DDC I2C driver known as "stu300" in the kernel tree. Reviewed-by: Wolfram Sang Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt | 15 +++++++++++++++ drivers/i2c/busses/i2c-stu300.c | 12 ++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt new file mode 100644 index 000000000000..bd81a482634f --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt @@ -0,0 +1,15 @@ +ST Microelectronics DDC I2C + +Required properties : +- compatible : Must be "st,ddci2c" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: interrupt number to the cpu. +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties: +- Child nodes conforming to i2c bus binding + +Examples : + diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c index 0a6f941133f6..1beaa05a3d2c 100644 --- a/drivers/i2c/busses/i2c-stu300.c +++ b/drivers/i2c/busses/i2c-stu300.c @@ -17,6 +17,7 @@ #include #include #include +#include /* the name of this kernel module */ #define NAME "stu300" @@ -923,6 +924,7 @@ stu300_probe(struct platform_device *pdev) adap->nr = bus_nr; adap->algo = &stu300_algo; adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; i2c_set_adapdata(adap, dev); /* i2c device drivers may be active on return from add_adapter() */ @@ -934,6 +936,10 @@ stu300_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, dev); + dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n", + dev->virtbase, dev->irq); + of_i2c_register_devices(adap); + return 0; } @@ -978,11 +984,17 @@ stu300_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id stu300_dt_match[] = { + { .compatible = "st,ddci2c" }, + {}, +}; + static struct platform_driver stu300_i2c_driver = { .driver = { .name = NAME, .owner = THIS_MODULE, .pm = STU300_I2C_PM, + .of_match_table = stu300_dt_match, }, .remove = __exit_p(stu300_remove), -- cgit v1.2.3 From c83c199199b9d68c56b5cc53b01b8f513f91b93a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 19 Apr 2013 12:56:36 +0200 Subject: watchdog: coh901327: devicetree support This adds support for probing the COH 901 327 watchdog from the device tree and also adds associated bindings. Acked-by: Wim Van Sebroeck Reviewed-by: Guenter Roeck Signed-off-by: Linus Walleij --- .../bindings/watchdog/stericsson-coh901327.txt | 19 +++++++++++++++++++ drivers/watchdog/coh901327_wdt.c | 12 +++++++++--- 2 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt new file mode 100644 index 000000000000..8ffb88e39e76 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt @@ -0,0 +1,19 @@ +ST-Ericsson COH 901 327 Watchdog timer + +Required properties: +- compatible: must be "stericsson,coh901327". +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: the interrupt used for the watchdog timeout warning. + +Optional properties: +- timeout-sec: contains the watchdog timeout in seconds. + +Example: + +watchdog: watchdog@c0012000 { + compatible = "stericsson,coh901327"; + reg = <0xc0012000 0x1000>; + interrupts = <3>; + timeout-sec = <60>; +}; diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c index b9b8a8be6f12..4bd070f524e5 100644 --- a/drivers/watchdog/coh901327_wdt.c +++ b/drivers/watchdog/coh901327_wdt.c @@ -354,9 +354,9 @@ static int __init coh901327_probe(struct platform_device *pdev) clk_disable(clk); - if (margin < 1 || margin > 327) - margin = 60; - coh901327_wdt.timeout = margin; + ret = watchdog_init_timeout(&coh901327_wdt, margin, &pdev->dev); + if (ret < 0) + coh901327_wdt.timeout = 60; ret = watchdog_register_device(&coh901327_wdt); if (ret == 0) @@ -441,10 +441,16 @@ void coh901327_watchdog_reset(void) /* Return and await doom */ } +static const struct of_device_id coh901327_dt_match[] = { + { .compatible = "stericsson,coh901327" }, + {}, +}; + static struct platform_driver coh901327_driver = { .driver = { .owner = THIS_MODULE, .name = "coh901327_wdog", + .of_match_table = coh901327_dt_match, }, .remove = __exit_p(coh901327_remove), .suspend = coh901327_suspend, -- cgit v1.2.3 From 301d2d87cb4f826a38548f692e1b3c8c23590a9f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Feb 2013 15:21:21 +0100 Subject: Documentation/devicetree: add a small note on PCI Throw in a file with references to the IEEE binding documents. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pci/pci.txt | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/pci.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt new file mode 100644 index 000000000000..41aeed38926d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -0,0 +1,9 @@ +PCI bus bridges have standardized Device Tree bindings: + +PCI Bus Binding to: IEEE Std 1275-1994 +http://www.openfirmware.org/ofwg/bindings/pci/pci2_1.pdf + +And for the interrupt mapping part: + +Open Firmware Recommended Practice: Interrupt Mapping +http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf -- cgit v1.2.3 From a180132f270a96d3b0e1e290b2911647abe9ed8e Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Fri, 26 Apr 2013 19:47:30 +0400 Subject: GPIO: clps711x: Add DT support Add DT support to the CLPS711X GPIO driver. Signed-off-by: Alexander Shiyan Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Olof Johansson --- .../devicetree/bindings/gpio/gpio-clps711x.txt | 28 ++++++++++++++++++++++ drivers/gpio/gpio-clps711x.c | 14 ++++++++--- 2 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-clps711x.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt new file mode 100644 index 000000000000..e0d0446a6b78 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt @@ -0,0 +1,28 @@ +Cirrus Logic CLPS711X GPIO controller + +Required properties: +- compatible: Should be "cirrus,clps711x-gpio" +- reg: Physical base GPIO controller registers location and length. + There should be two registers, first is DATA register, the second + is DIRECTION. +- gpio-controller: Marks the device node as a gpio controller. +- #gpio-cells: Should be two. The first cell is the pin number and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low + +Note: Each GPIO port should have an alias correctly numbered in "aliases" +node. + +Example: + +aliases { + gpio0 = &porta; +}; + +porta: gpio@80000000 { + compatible = "cirrus,clps711x-gpio"; + reg = <0x80000000 0x1>, <0x80000040 0x1>; + gpio-controller; + #gpio-cells = <2>; +}; diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c index 6ce8a8c1669e..0edaf2ce9266 100644 --- a/drivers/gpio/gpio-clps711x.c +++ b/drivers/gpio/gpio-clps711x.c @@ -17,10 +17,11 @@ static int clps711x_gpio_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; void __iomem *dat, *dir; struct bgpio_chip *bgc; struct resource *res; - int err, id = pdev->id; + int err, id = np ? of_alias_get_id(np, "gpio") : pdev->id; if ((id < 0) || (id > 4)) return -ENODEV; @@ -76,10 +77,17 @@ static int clps711x_gpio_remove(struct platform_device *pdev) return bgpio_remove(bgc); } +static const struct of_device_id clps711x_gpio_ids[] = { + { .compatible = "cirrus,clps711x-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, clps711x_gpio_ids); + static struct platform_driver clps711x_gpio_driver = { .driver = { - .name = "clps711x-gpio", - .owner = THIS_MODULE, + .name = "clps711x-gpio", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(clps711x_gpio_ids), }, .probe = clps711x_gpio_probe, .remove = clps711x_gpio_remove, -- cgit v1.2.3 From a8b447f2bbbba737ff4478f498d7f83c75a9461b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 4 Jun 2013 11:37:36 +0200 Subject: clocksource: dw_apb_timer_of: add clock-handling Add the possibility to get the clock-frequency from a timer clock instead of specifying it as dt property. Additionally also add the possibility to also define a controlling periphal clock for the timer block. The clock-frequency property is kept to act as fallback if no clocks are specified. Signed-off-by: Heiko Stuebner Acked-by: Jamie Iles --- Documentation/devicetree/bindings/rtc/dw-apb.txt | 19 +++++++++++++++++ drivers/clocksource/dw_apb_timer_of.c | 26 +++++++++++++++++++++++- 2 files changed, 44 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt index 93e2b0f048e6..eb2327b2bdb3 100644 --- a/Documentation/devicetree/bindings/rtc/dw-apb.txt +++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt @@ -5,9 +5,20 @@ Required properties: - reg: physical base address of the controller and length of memory mapped region. - interrupts: IRQ line for the timer. +- either clocks+clock-names or clock-frequency properties + +Optional properties: +- clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +- clock-names : should contain "timer" and "pclk" entries, matching entries + in the clocks property. - clock-frequency: The frequency in HZ of the timer. - clock-freq: For backwards compatibility with picoxcell +If using the clock specifiers, the pclk clock is optional, as not all +systems may use one. + + Example: timer1: timer@ffc09000 { @@ -23,3 +34,11 @@ Example: clock-frequency = <200000000>; reg = <0xffd00000 0x1000>; }; + + timer3: timer@ffe00000 { + compatible = "snps,dw-apb-timer-osc"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clocks = <&timer_clk>, <&timer_pclk>; + clock-names = "timer", "pclk"; + }; diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c index d6c0fda76a7e..1964f8716966 100644 --- a/drivers/clocksource/dw_apb_timer_of.c +++ b/drivers/clocksource/dw_apb_timer_of.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -27,14 +28,37 @@ static void timer_get_base_and_rate(struct device_node *np, void __iomem **base, u32 *rate) { + struct clk *timer_clk; + struct clk *pclk; + *base = of_iomap(np, 0); if (!*base) panic("Unable to map regs for %s", np->name); + /* + * Not all implementations use a periphal clock, so don't panic + * if it's not present + */ + pclk = of_clk_get_by_name(np, "pclk"); + if (!IS_ERR(pclk)) + if (clk_prepare_enable(pclk)) + pr_warn("pclk for %s is present, but could not be activated\n", + np->name); + + timer_clk = of_clk_get_by_name(np, "timer"); + if (IS_ERR(timer_clk)) + goto try_clock_freq; + + if (!clk_prepare_enable(timer_clk)) { + *rate = clk_get_rate(timer_clk); + return; + } + +try_clock_freq: if (of_property_read_u32(np, "clock-freq", rate) && of_property_read_u32(np, "clock-frequency", rate)) - panic("No clock-frequency property for %s", np->name); + panic("No clock nor clock-frequency property for %s", np->name); } static void add_clockevent(struct device_node *event_timer) -- cgit v1.2.3 From f55b2b56cd37fa8bcfcb75248c27094eaf09e04c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 1 Mar 2013 02:20:55 +0100 Subject: ARM: integrator: basic PCIv3 device tree support This registers the memory ranges for I/O, non-prefetched and prefetched memory and configuration space for the PCIv3 bridge and let us fetch these basic memory resources from the device tree in the device tree boot path. Remove the stepping stone platform device. This is an either/or approach - the platform data path is mutually exclusive to the plain platform data path and provided addresses from the device tree have to be correct. This adds the interrupt-map property to the PCIv3 DTS file and makes the bridge obtain mappings from the device tree. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- .../devicetree/bindings/pci/v3-v360epc-pci.txt | 15 ++ .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/integratorap.dts | 41 +++++ arch/arm/mach-integrator/integrator_ap.c | 11 -- arch/arm/mach-integrator/pci_v3.c | 177 ++++++++++++++++++--- 5 files changed, 209 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt new file mode 100644 index 000000000000..30b364e504ba --- /dev/null +++ b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt @@ -0,0 +1,15 @@ +V3 Semiconductor V360 EPC PCI bridge + +This bridge is found in the ARM Integrator/AP (Application Platform) + +Integrator-specific notes: + +- syscon: should contain a link to the syscon device node (since + on the Integrator, some registers in the syscon are required to + operate the V3). + +V360 EPC specific notes: + +- reg: should contain the base address of the V3 adapter. +- interrupts: should contain a reference to the V3 error interrupt + as routed on the system. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 6931c4348d24..d247d1003987 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -59,6 +59,7 @@ ste ST-Ericsson stericsson ST-Ericsson ti Texas Instruments toshiba Toshiba Corporation +v3 V3 Semiconductor via VIA Technologies, Inc. wlf Wolfson Microelectronics wm Wondermedia Technologies, Inc. diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index c9c3fa344647..03f23b7a0ab5 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -39,6 +39,47 @@ valid-mask = <0x003fffff>; }; + pci: pciv3@62000000 { + compatible = "v3,v360epc-pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x62000000 0x10000>; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + ranges = <0x00000000 0 0x61000000 /* config space */ + 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ + 0x01000000 0 0x60000000 /* I/O space */ + 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ + 0x02000000 0 0x40000000 /* non-prefectable memory */ + 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ + 0x42000000 0 0x50000000 /* prefetchable memory */ + 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = < + /* IDSEL 9 */ + 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ + 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ + 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ + 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ + 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ + 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ + 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ + 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ + 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ + 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ + 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ + 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ + 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ + >; + }; + fpga { /* * The Integator/AP predates the idea to have magic numbers diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 16f3196efdb4..a5b15c4e8def 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -473,15 +473,6 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { { /* sentinel */ }, }; -/* - * This is a placeholder that will get deleted when we move the PCI - * device over to the device tree. - */ -static struct platform_device pci_v3_device_of = { - .name = "pci-v3", - .id = 0, -}; - static void __init ap_init_of(void) { unsigned long sc_dec; @@ -536,8 +527,6 @@ static void __init ap_init_of(void) of_platform_populate(root, of_default_bus_match_table, ap_auxdata_lookup, parent); - platform_device_register(&pci_v3_device_of); - sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); for (i = 0; i < 4; i++) { struct lm_device *lmdev; diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index a3cefdebd136..a0e069d37e14 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -28,6 +28,10 @@ #include #include #include +#include +#include +#include +#include #include