From 26f95c4ae2b1fd1b03531b3d662fc21beedce955 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Sun, 10 Dec 2006 21:21:28 +0100 Subject: i2c: Fix documentation typos Fix typos in i2c bus drivers documentation. Signed-off-by: Jean Delvare --- Documentation/i2c/busses/i2c-amd8111 | 2 +- Documentation/i2c/busses/i2c-nforce2 | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/i2c/busses/i2c-amd8111 b/Documentation/i2c/busses/i2c-amd8111 index db294ee7455a..460dd6635fd2 100644 --- a/Documentation/i2c/busses/i2c-amd8111 +++ b/Documentation/i2c/busses/i2c-amd8111 @@ -5,7 +5,7 @@ Supported adapters: Datasheets: AMD datasheet not yet available, but almost everything can be found - in publically available ACPI 2.0 specification, which the adapter + in the publicly available ACPI 2.0 specification, which the adapter follows. Author: Vojtech Pavlik diff --git a/Documentation/i2c/busses/i2c-nforce2 b/Documentation/i2c/busses/i2c-nforce2 index cd49c428a3ab..5465ed0f4379 100644 --- a/Documentation/i2c/busses/i2c-nforce2 +++ b/Documentation/i2c/busses/i2c-nforce2 @@ -10,7 +10,7 @@ Supported adapters: * nForce4 MCP51 10de:0264 * nForce4 MCP55 10de:0368 -Datasheet: not publically available, but seems to be similar to the +Datasheet: not publicly available, but seems to be similar to the AMD-8111 SMBus 2.0 adapter. Authors: @@ -38,7 +38,7 @@ Notes ----- The SMBus adapter in the nForce2 chipset seems to be very similar to the -SMBus 2.0 adapter in the AMD-8111 southbridge. However, I could only get +SMBus 2.0 adapter in the AMD-8111 south bridge. However, I could only get the driver to work with direct I/O access, which is different to the EC interface of the AMD-8111. Tested on Asus A7N8X. The ACPI DSDT table of the Asus A7N8X lists two SMBuses, both of which are supported by this driver. -- cgit v1.2.3 From 51fd554b6547b74c7e6d1f52885ba8532b531023 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Sun, 10 Dec 2006 21:21:29 +0100 Subject: i2c: Delete the broken i2c-ite bus driver The rest of the ITE8172 support was already removed from MIPS tree. Signed-off-by: Jean Delvare Signed-off-by: Yoichi Yuasa Acked-by: Ralf Baechle --- Documentation/feature-removal-schedule.txt | 11 - drivers/i2c/algos/Kconfig | 11 - drivers/i2c/algos/Makefile | 1 - drivers/i2c/algos/i2c-algo-ite.c | 806 ----------------------------- drivers/i2c/algos/i2c-algo-ite.h | 117 ----- drivers/i2c/busses/Kconfig | 12 - drivers/i2c/busses/Makefile | 1 - drivers/i2c/busses/i2c-ite.c | 278 ---------- include/linux/i2c-algo-ite.h | 72 --- include/linux/i2c-id.h | 3 - 10 files changed, 1312 deletions(-) delete mode 100644 drivers/i2c/algos/i2c-algo-ite.c delete mode 100644 drivers/i2c/algos/i2c-algo-ite.h delete mode 100644 drivers/i2c/busses/i2c-ite.c delete mode 100644 include/linux/i2c-algo-ite.h (limited to 'Documentation') diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 46f2a559b27c..031029e89fd9 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -216,17 +216,6 @@ Who: Thomas Gleixner --------------------------- -What: i2c-ite and i2c-algo-ite drivers -When: September 2006 -Why: These drivers never compiled since they were added to the kernel - tree 5 years ago. This feature removal can be reevaluated if - someone shows interest in the drivers, fixes them and takes over - maintenance. - http://marc.theaimsgroup.com/?l=linux-mips&m=115040510817448 -Who: Jean Delvare - ---------------------------- - What: Bridge netfilter deferred IPv4/IPv6 output hook calling When: January 2007 Why: The deferred output hooks are a layering violation causing unusual diff --git a/drivers/i2c/algos/Kconfig b/drivers/i2c/algos/Kconfig index c034820615bb..af0203409dd1 100644 --- a/drivers/i2c/algos/Kconfig +++ b/drivers/i2c/algos/Kconfig @@ -38,17 +38,6 @@ config I2C_ALGOPCA This support is also available as a module. If so, the module will be called i2c-algo-pca. -config I2C_ALGOITE - tristate "ITE I2C Algorithm" - depends on MIPS_ITE8172 && I2C - help - This supports the use of the ITE8172 I2C interface found on some MIPS - systems. Say Y if you have one of these. You should also say Y for - the ITE I2C peripheral driver support below. - - This support is also available as a module. If so, the module - will be called i2c-algo-ite. - config I2C_ALGO8XX tristate "MPC8xx CPM I2C interface" depends on 8xx && I2C diff --git a/drivers/i2c/algos/Makefile b/drivers/i2c/algos/Makefile index 208be04a3dbd..cac1051bd4f1 100644 --- a/drivers/i2c/algos/Makefile +++ b/drivers/i2c/algos/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_I2C_ALGOBIT) += i2c-algo-bit.o obj-$(CONFIG_I2C_ALGOPCF) += i2c-algo-pcf.o obj-$(CONFIG_I2C_ALGOPCA) += i2c-algo-pca.o -obj-$(CONFIG_I2C_ALGOITE) += i2c-algo-ite.o obj-$(CONFIG_I2C_ALGO_SGI) += i2c-algo-sgi.o ifeq ($(CONFIG_I2C_DEBUG_ALGO),y) diff --git a/drivers/i2c/algos/i2c-algo-ite.c b/drivers/i2c/algos/i2c-algo-ite.c deleted file mode 100644 index 70d8eefb5efc..000000000000 --- a/drivers/i2c/algos/i2c-algo-ite.c +++ /dev/null @@ -1,806 +0,0 @@ -/* - ------------------------------------------------------------------------- - i2c-algo-ite.c i2c driver algorithms for ITE adapters - - Hai-Pao Fan, MontaVista Software, Inc. - hpfan@mvista.com or source@mvista.com - - Copyright 2000 MontaVista Software Inc. - - --------------------------------------------------------------------------- - This file was highly leveraged from i2c-algo-pcf.c, which was created - by Simon G. Vogl and Hans Berglund: - - - Copyright (C) 1995-1997 Simon G. Vogl - 1998-2000 Hans Berglund - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -/* ------------------------------------------------------------------------- */ - -/* With some changes from Kyösti Mälkki and - Frodo Looijaard ,and also from Martin Bailey - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "i2c-algo-ite.h" - -#define PM_DSR IT8172_PCI_IO_BASE + IT_PM_DSR -#define PM_IBSR IT8172_PCI_IO_BASE + IT_PM_DSR + 0x04 -#define GPIO_CCR IT8172_PCI_IO_BASE + IT_GPCCR - -#define DEB2(x) if (i2c_debug>=2) x -#define DEB3(x) if (i2c_debug>=3) x /* print several statistical values*/ -#define DEF_TIMEOUT 16 - - -/* module parameters: - */ -static int i2c_debug; -static int iic_test; /* see if the line-setting functions work */ - -/* --- setting states on the bus with the right timing: --------------- */ - -#define get_clock(adap) adap->getclock(adap->data) -#define iic_outw(adap, reg, val) adap->setiic(adap->data, reg, val) -#define iic_inw(adap, reg) adap->getiic(adap->data, reg) - - -/* --- other auxiliary functions -------------------------------------- */ - -static void iic_start(struct i2c_algo_iic_data *adap) -{ - iic_outw(adap,ITE_I2CHCR,ITE_CMD); -} - -static void iic_stop(struct i2c_algo_iic_data *adap) -{ - iic_outw(adap,ITE_I2CHCR,0); - iic_outw(adap,ITE_I2CHSR,ITE_I2CHSR_TDI); -} - -static void iic_reset(struct i2c_algo_iic_data *adap) -{ - iic_outw(adap, PM_IBSR, iic_inw(adap, PM_IBSR) | 0x80); -} - - -static int wait_for_bb(struct i2c_algo_iic_data *adap) -{ - int timeout = DEF_TIMEOUT; - short status; - - status = iic_inw(adap, ITE_I2CHSR); -#ifndef STUB_I2C - while (timeout-- && (status & ITE_I2CHSR_HB)) { - udelay(1000); /* How much is this? */ - status = iic_inw(adap, ITE_I2CHSR); - } -#endif - if (timeout<=0) { - printk(KERN_ERR "Timeout, host is busy\n"); - iic_reset(adap); - } - return(timeout<=0); -} - -/* After we issue a transaction on the IIC bus, this function - * is called. It puts this process to sleep until we get an interrupt from - * from the controller telling us that the transaction we requested in complete. - */ -static int wait_for_pin(struct i2c_algo_iic_data *adap, short *status) { - - int timeout = DEF_TIMEOUT; - - timeout = wait_for_bb(adap); - if (timeout) { - DEB2(printk("Timeout waiting for host not busy\n");) - return -EIO; - } - timeout = DEF_TIMEOUT; - - *status = iic_inw(adap, ITE_I2CHSR); -#ifndef STUB_I2C - while (timeout-- && !(*status & ITE_I2CHSR_TDI)) { - adap->waitforpin(); - *status = iic_inw(adap, ITE_I2CHSR); - } -#endif - if (timeout <= 0) - return(-1); - else - return(0); -} - -static int wait_for_fe(struct i2c_algo_iic_data *adap, short *status) -{ - int timeout = DEF_TIMEOUT; - - *status = iic_inw(adap, ITE_I2CFSR); -#ifndef STUB_I2C - while (timeout-- && (*status & ITE_I2CFSR_FE)) { - udelay(1000); - iic_inw(adap, ITE_I2CFSR); - } -#endif - if (timeout <= 0) - return(-1); - else - return(0); -} - -static int iic_init (struct i2c_algo_iic_data *adap) -{ - short i; - - /* Clear bit 7 to set I2C to normal operation mode */ - i=iic_inw(adap, PM_DSR)& 0xff7f; - iic_outw(adap, PM_DSR, i); - - /* set IT_GPCCR port C bit 2&3 as function 2 */ - i = iic_inw(adap, GPIO_CCR) & 0xfc0f; - iic_outw(adap,GPIO_CCR,i); - - /* Clear slave address/sub-address */ - iic_outw(adap,ITE_I2CSAR, 0); - iic_outw(adap,ITE_I2CSSAR, 0); - - /* Set clock counter register */ - iic_outw(adap,ITE_I2CCKCNT, get_clock(adap)); - - /* Set START/reSTART/STOP time registers */ - iic_outw(adap,ITE_I2CSHDR, 0x0a); - iic_outw(adap,ITE_I2CRSUR, 0x0a); - iic_outw(adap,ITE_I2CPSUR, 0x0a); - - /* Enable interrupts on completing the current transaction */ - iic_outw(adap,ITE_I2CHCR, ITE_I2CHCR_IE | ITE_I2CHCR_HCE); - - /* Clear transfer count */ - iic_outw(adap,ITE_I2CFBCR, 0x0); - - DEB2(printk("iic_init: Initialized IIC on ITE 0x%x\n", - iic_inw(adap, ITE_I2CHSR))); - return 0; -} - - -/* - * Sanity check for the adapter hardware - check the reaction of - * the bus lines only if it seems to be idle. - */ -static int test_bus(struct i2c_algo_iic_data *adap, char *name) { -#if 0 - int scl,sda; - sda=getsda(adap); - if (adap->getscl==NULL) { - printk("test_bus: Warning: Adapter can't read from clock line - skipping test.\n"); - return 0; - } - scl=getscl(adap); - printk("test_bus: Adapter: %s scl: %d sda: %d -- testing...\n", - name,getscl(adap),getsda(adap)); - if (!scl || !sda ) { - printk("test_bus: %s seems to be busy.\n",adap->name); - goto bailout; - } - sdalo(adap); - printk("test_bus:1 scl: %d sda: %d\n", getscl(adap), - getsda(adap)); - if ( 0 != getsda(adap) ) { - printk("test_bus: %s SDA stuck high!\n",name); - sdahi(adap); - goto bailout; - } - if ( 0 == getscl(adap) ) { - printk("test_bus: %s SCL unexpected low while pulling SDA low!\n", - name); - goto bailout; - } - sdahi(adap); - printk("test_bus:2 scl: %d sda: %d\n", getscl(adap), - getsda(adap)); - if ( 0 == getsda(adap) ) { - printk("test_bus: %s SDA stuck low!\n",name); - sdahi(adap); - goto bailout; - } - if ( 0 == getscl(adap) ) { - printk("test_bus: %s SCL unexpected low while SDA high!\n", - adap->name); - goto bailout; - } - scllo(adap); - printk("test_bus:3 scl: %d sda: %d\n", getscl(adap), - getsda(adap)); - if ( 0 != getscl(adap) ) { - - sclhi(adap); - goto bailout; - } - if ( 0 == getsda(adap) ) { - printk("test_bus: %s SDA unexpected low while pulling SCL low!\n", - name); - goto bailout; - } - sclhi(adap); - printk("test_bus:4 scl: %d sda: %d\n", getscl(adap), - getsda(adap)); - if ( 0 == getscl(adap) ) { - printk("test_bus: %s SCL stuck low!\n",name); - sclhi(adap); - goto bailout; - } - if ( 0 == getsda(adap) ) { - printk("test_bus: %s SDA unexpected low while SCL high!\n", - name); - goto bailout; - } - printk("test_bus: %s passed test.\n",name); - return 0; -bailout: - sdahi(adap); - sclhi(adap); - return -ENODEV; -#endif - return (0); -} - -/* ----- Utility functions - */ - - -/* Verify the device we want to talk to on the IIC bus really exists. */ -static inline int try_address(struct i2c_algo_iic_data *adap, - unsigned int addr, int retries) -{ - int i, ret = -1; - short status; - - for (i=0;iudelay); - } - DEB2(if (i) printk("try_address: needed %d retries for 0x%x\n",i, - addr)); - return ret; -} - - -static int iic_sendbytes(struct i2c_adapter *i2c_adap,const char *buf, - int count) -{ - struct i2c_algo_iic_data *adap = i2c_adap->algo_data; - int wrcount=0, timeout; - short status; - int loops, remainder, i, j; - union { - char byte[2]; - unsigned short word; - } tmp; - - iic_outw(adap, ITE_I2CSSAR, (unsigned short)buf[wrcount++]); - count--; - if (count == 0) - return -EIO; - - loops = count / 32; /* 32-byte FIFO */ - remainder = count % 32; - - if(loops) { - for(i=0; iname); - return -EREMOTEIO; /* got a better one ?? */ - } - if (status & ITE_I2CHSR_DB) { - iic_stop(adap); - printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name); - return -EREMOTEIO; /* got a better one ?? */ - } - } - } - if(remainder) { - iic_outw(adap, ITE_I2CFBCR, remainder); - for(i=0; iname); - return -EREMOTEIO; /* got a better one ?? */ - } -#ifndef STUB_I2C - if (status & ITE_I2CHSR_DB) { - iic_stop(adap); - printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name); - return -EREMOTEIO; /* got a better one ?? */ - } -#endif - } - iic_stop(adap); - return wrcount; -} - - -static int iic_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count, - int sread) -{ - int rdcount=0, i, timeout; - short status; - struct i2c_algo_iic_data *adap = i2c_adap->algo_data; - int loops, remainder, j; - union { - char byte[2]; - unsigned short word; - } tmp; - - loops = count / 32; /* 32-byte FIFO */ - remainder = count % 32; - - if(loops) { - for(i=0; iname); - return (-1); - } -#ifndef STUB_I2C - if (status & ITE_I2CHSR_DB) { - iic_stop(adap); - printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name); - return (-1); - } -#endif - - timeout = wait_for_fe(adap, &status); - if(timeout) { - iic_stop(adap); - printk("iic_readbytes: %s FIFO is empty\n", i2c_adap->name); - return (-1); - } - - for(j=0; j<32/2; j++) { - tmp.word = iic_inw(adap, ITE_I2CFDR); - buf[rdcount++] = tmp.byte[1]; - buf[rdcount++] = tmp.byte[0]; - } - - /* status FIFO underrun */ - iic_inw(adap, ITE_I2CFSR); - - } - } - - - if(remainder) { - remainder=(remainder+1)/2 * 2; - iic_outw(adap, ITE_I2CFBCR, remainder); - if (sread) - iic_outw(adap, ITE_I2CHCR, ITE_SREAD); - else - iic_outw(adap, ITE_I2CHCR, ITE_READ); /* Issue READ command */ - - timeout = wait_for_pin(adap, &status); - if(timeout) { - iic_stop(adap); - printk("iic_readbytes: %s read timeout.\n", i2c_adap->name); - return (-1); - } -#ifndef STUB_I2C - if (status & ITE_I2CHSR_DB) { - iic_stop(adap); - printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name); - return (-1); - } -#endif - timeout = wait_for_fe(adap, &status); - if(timeout) { - iic_stop(adap); - printk("iic_readbytes: %s FIFO is empty\n", i2c_adap->name); - return (-1); - } - - for(i=0; i<(remainder+1)/2; i++) { - tmp.word = iic_inw(adap, ITE_I2CFDR); - buf[rdcount++] = tmp.byte[1]; - buf[rdcount++] = tmp.byte[0]; - } - - /* status FIFO underrun */ - iic_inw(adap, ITE_I2CFSR); - - } - - iic_stop(adap); - return rdcount; -} - - -/* This function implements combined transactions. Combined - * transactions consist of combinations of reading and writing blocks of data. - * Each transfer (i.e. a read or a write) is separated by a repeated start - * condition. - */ -#if 0 -static int iic_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) -{ - int i; - struct i2c_msg *pmsg; - int ret; - - DEB2(printk("Beginning combined transaction\n")); - - for(i=0; i<(num-1); i++) { - pmsg = &msgs[i]; - if(pmsg->flags & I2C_M_RD) { - DEB2(printk(" This one is a read\n")); - ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER); - } - else if(!(pmsg->flags & I2C_M_RD)) { - DEB2(printk("This one is a write\n")); - ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER); - } - } - /* Last read or write segment needs to be terminated with a stop */ - pmsg = &msgs[i]; - - if(pmsg->flags & I2C_M_RD) { - DEB2(printk("Doing the last read\n")); - ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER); - } - else if(!(pmsg->flags & I2C_M_RD)) { - DEB2(printk("Doing the last write\n")); - ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER); - } - - return ret; -} -#endif - - -/* Whenever we initiate a transaction, the first byte clocked - * onto the bus after the start condition is the address (7 bit) of the - * device we want to talk to. This function manipulates the address specified - * so that it makes sense to the hardware when written to the IIC peripheral. - * - * Note: 10 bit addresses are not supported in this driver, although they are - * supported by the hardware. This functionality needs to be implemented. - */ -static inline int iic_doAddress(struct i2c_algo_iic_data *adap, - struct i2c_msg *msg, int retries) -{ - unsigned short flags = msg->flags; - unsigned int addr; - int ret; - -/* Ten bit addresses not supported right now */ - if ( (flags & I2C_M_TEN) ) { -#if 0 - addr = 0xf0 | (( msg->addr >> 7) & 0x03); - DEB2(printk("addr0: %d\n",addr)); - ret = try_address(adap, addr, retries); - if (ret!=1) { - printk("iic_doAddress: died at extended address code.\n"); - return -EREMOTEIO; - } - iic_outw(adap,msg->addr & 0x7f); - if (ret != 1) { - printk("iic_doAddress: died at 2nd address code.\n"); - return -EREMOTEIO; - } - if ( flags & I2C_M_RD ) { - i2c_repstart(adap); - addr |= 0x01; - ret = try_address(adap, addr, retries); - if (ret!=1) { - printk("iic_doAddress: died at extended address code.\n"); - return -EREMOTEIO; - } - } -#endif - } else { - - addr = ( msg->addr << 1 ); - -#if 0 - if (flags & I2C_M_RD ) - addr |= 1; - if (flags & I2C_M_REV_DIR_ADDR ) - addr ^= 1; -#endif - - if (iic_inw(adap, ITE_I2CSAR) != addr) { - iic_outw(adap, ITE_I2CSAR, addr); - ret = try_address(adap, addr, retries); - if (ret!=1) { - printk("iic_doAddress: died at address code.\n"); - return -EREMOTEIO; - } - } - - } - - return 0; -} - - -/* Description: Prepares the controller for a transaction (clearing status - * registers, data buffers, etc), and then calls either iic_readbytes or - * iic_sendbytes to do the actual transaction. - * - * still to be done: Before we issue a transaction, we should - * verify that the bus is not busy or in some unknown state. - */ -static int iic_xfer(struct i2c_adapter *i2c_adap, - struct i2c_msg *msgs, - int num) -{ - struct i2c_algo_iic_data *adap = i2c_adap->algo_data; - struct i2c_msg *pmsg; - int i = 0; - int ret, timeout; - - pmsg = &msgs[i]; - - if(!pmsg->len) { - DEB2(printk("iic_xfer: read/write length is 0\n");) - return -EIO; - } - if(!(pmsg->flags & I2C_M_RD) && (!(pmsg->len)%2) ) { - DEB2(printk("iic_xfer: write buffer length is not odd\n");) - return -EIO; - } - - /* Wait for any pending transfers to complete */ - timeout = wait_for_bb(adap); - if (timeout) { - DEB2(printk("iic_xfer: Timeout waiting for host not busy\n");) - return -EIO; - } - - /* Flush FIFO */ - iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH); - - /* Load address */ - ret = iic_doAddress(adap, pmsg, i2c_adap->retries); - if (ret) - return -EIO; - -#if 0 - /* Combined transaction (read and write) */ - if(num > 1) { - DEB2(printk("iic_xfer: Call combined transaction\n")); - ret = iic_combined_transaction(i2c_adap, msgs, num); - } -#endif - - DEB3(printk("iic_xfer: Msg %d, addr=0x%x, flags=0x%x, len=%d\n", - i, msgs[i].addr, msgs[i].flags, msgs[i].len);) - - if(pmsg->flags & I2C_M_RD) /* Read */ - ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, 0); - else { /* Write */ - udelay(1000); - ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len); - } - - if (ret != pmsg->len) - DEB3(printk("iic_xfer: error or fail on read/write %d bytes.\n",ret)); - else - DEB3(printk("iic_xfer: read/write %d bytes.\n",ret)); - - return ret; -} - - -/* Implements device specific ioctls. Higher level ioctls can - * be found in i2c-core.c and are typical of any i2c controller (specifying - * slave address, timeouts, etc). These ioctls take advantage of any hardware - * features built into the controller for which this algorithm-adapter set - * was written. These ioctls allow you to take control of the data and clock - * lines and set the either high or low, - * similar to a GPIO pin. - */ -static int algo_control(struct i2c_adapter *adapter, - unsigned int cmd, unsigned long arg) -{ - - struct i2c_algo_iic_data *adap = adapter->algo_data; - struct i2c_iic_msg s_msg; - char *buf; - int ret; - - if (cmd == I2C_SREAD) { - if(copy_from_user(&s_msg, (struct i2c_iic_msg *)arg, - sizeof(struct i2c_iic_msg))) - return -EFAULT; - buf = kmalloc(s_msg.len, GFP_KERNEL); - if (buf== NULL) - return -ENOMEM; - - /* Flush FIFO */ - iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH); - - /* Load address */ - iic_outw(adap, ITE_I2CSAR,s_msg.addr<<1); - iic_outw(adap, ITE_I2CSSAR,s_msg.waddr & 0xff); - - ret = iic_readbytes(adapter, buf, s_msg.len, 1); - if (ret>=0) { - if(copy_to_user( s_msg.buf, buf, s_msg.len) ) - ret = -EFAULT; - } - kfree(buf); - } - return 0; -} - - -static u32 iic_func(struct i2c_adapter *adap) -{ - return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | - I2C_FUNC_PROTOCOL_MANGLING; -} - -/* -----exported algorithm data: ------------------------------------- */ - -static struct i2c_algorithm iic_algo = { - .master_xfer = iic_xfer, - .algo_control = algo_control, /* ioctl */ - .functionality = iic_func, -}; - - -/* - * registering functions to load algorithms at runtime - */ -int i2c_iic_add_bus(struct i2c_adapter *adap) -{ - struct i2c_algo_iic_data *iic_adap = adap->algo_data; - - if (iic_test) { - int ret = test_bus(iic_adap, adap->name); - if (ret<0) - return -ENODEV; - } - - DEB2(printk("i2c-algo-ite: hw routines for %s registered.\n", - adap->name)); - - /* register new adapter to i2c module... */ - adap->algo = &iic_algo; - - adap->timeout = 100; /* default values, should */ - adap->retries = 3; /* be replaced by defines */ - adap->flags = 0; - - iic_init(iic_adap); - return i2c_add_adapter(adap); -} - - -int i2c_iic_del_bus(struct i2c_adapter *adap) -{ - int res; - if ((res = i2c_del_adapter(adap)) < 0) - return res; - DEB2(printk("i2c-algo-ite: adapter unregistered: %s\n",adap->name)); - - return 0; -} - - -int __init i2c_algo_iic_init (void) -{ - printk(KERN_INFO "ITE iic (i2c) algorithm module\n"); - return 0; -} - - -void i2c_algo_iic_exit(void) -{ - return; -} - - -EXPORT_SYMBOL(i2c_iic_add_bus); -EXPORT_SYMBOL(i2c_iic_del_bus); - -/* The MODULE_* macros resolve to nothing if MODULES is not defined - * when this file is compiled. - */ -MODULE_AUTHOR("MontaVista Software "); -MODULE_DESCRIPTION("ITE iic algorithm"); -MODULE_LICENSE("GPL"); - -module_param(iic_test, bool, 0); -module_param(i2c_debug, int, S_IRUGO | S_IWUSR); - -MODULE_PARM_DESC(iic_test, "Test if the I2C bus is available"); -MODULE_PARM_DESC(i2c_debug, - "debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol"); - - -/* This function resolves to init_module (the function invoked when a module - * is loaded via insmod) when this file is compiled with MODULES defined. - * Otherwise (i.e. if you want this driver statically linked to the kernel), - * a pointer to this function is stored in a table and called - * during the initialization of the kernel (in do_basic_setup in /init/main.c) - * - * All this functionality is complements of the macros defined in linux/init.h - */ -module_init(i2c_algo_iic_init); - - -/* If MODULES is defined when this file is compiled, then this function will - * resolved to cleanup_module. - */ -module_exit(i2c_algo_iic_exit); diff --git a/drivers/i2c/algos/i2c-algo-ite.h b/drivers/i2c/algos/i2c-algo-ite.h deleted file mode 100644 index a8ca3c9b546a..000000000000 --- a/drivers/i2c/algos/i2c-algo-ite.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - -------------------------------------------------------------------- - i2c-ite.h: Global defines for the I2C controller on board the - ITE MIPS processor. - -------------------------------------------------------------------- - Hai-Pao Fan, MontaVista Software, Inc. - hpfan@mvista.com or source@mvista.com - - Copyright 2001 MontaVista Software Inc. - - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - - */ - -#ifndef I2C_ITE_H -#define I2C_ITE_H 1 - -#include - -/* I2C Registers */ -#define ITE_I2CHCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x30 -#define ITE_I2CHSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x34 -#define ITE_I2CSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x38 -#define ITE_I2CSSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x3c -#define ITE_I2CCKCNT IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x48 -#define ITE_I2CSHDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x4c -#define ITE_I2CRSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x50 -#define ITE_I2CPSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x54 - -#define ITE_I2CFDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x70 -#define ITE_I2CFBCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x74 -#define ITE_I2CFCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x78 -#define ITE_I2CFSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x7c - - -/* Host Control Register ITE_I2CHCR */ -#define ITE_I2CHCR_HCE 0x01 /* Enable I2C Host Controller */ -#define ITE_I2CHCR_IE 0x02 /* Enable the interrupt after completing - the current transaction */ -#define ITE_I2CHCR_CP_W 0x00 /* bit2-4 000 - Write */ -#define ITE_I2CHCR_CP_R 0x08 /* 010 - Current address read */ -#define ITE_I2CHCR_CP_S 0x10 /* 100 - Sequential read */ -#define ITE_I2CHCR_ST 0x20 /* Initiates the I2C host controller to execute - the command and send the data programmed in - all required registers to I2C bus */ -#define ITE_CMD ITE_I2CHCR_HCE | ITE_I2CHCR_IE | ITE_I2CHCR_ST -#define ITE_WRITE ITE_CMD | ITE_I2CHCR_CP_W -#define ITE_READ ITE_CMD | ITE_I2CHCR_CP_R -#define ITE_SREAD ITE_CMD | ITE_I2CHCR_CP_S - -/* Host Status Register ITE_I2CHSR */ -#define ITE_I2CHSR_DB 0x01 /* Device is busy, receives NACK response except - in the first and last bytes */ -#define ITE_I2CHSR_DNE 0x02 /* Target address on I2C bus does not exist */ -#define ITE_I2CHSR_TDI 0x04 /* R/W Transaction on I2C bus was completed */ -#define ITE_I2CHSR_HB 0x08 /* Host controller is processing transactions */ -#define ITE_I2CHSR_FER 0x10 /* Error occurs in the FIFO */ - -/* Slave Address Register ITE_I2CSAR */ -#define ITE_I2CSAR_SA_MASK 0xfe /* Target I2C device address */ -#define ITE_I2CSAR_ASO 0x0100 /* Output 1/0 to I2CAS port when the - next slave address is addressed */ - -/* Slave Sub-address Register ITE_I2CSSAR */ -#define ITE_I2CSSAR_SUBA_MASK 0xff /* Target I2C device sub-address */ - -/* Clock Counter Register ITE_I2CCKCNT */ -#define ITE_I2CCKCNT_STOP 0x00 /* stop I2C clock */ -#define ITE_I2CCKCNT_HPCC_MASK 0x7f /* SCL high period counter */ -#define ITE_I2CCKCNT_LPCC_MASK 0x7f00 /* SCL low period counter */ - -/* START Hold Time Register ITE_I2CSHDR */ -/* value is counted based on 16 MHz internal clock */ -#define ITE_I2CSHDR_FM 0x0a /* START condition at fast mode */ -#define ITE_I2CSHDR_SM 0x47 /* START contition at standard mode */ - -/* (Repeated) START Setup Time Register ITE_I2CRSUR */ -/* value is counted based on 16 MHz internal clock */ -#define ITE_I2CRSUR_FM 0x0a /* repeated START condition at fast mode */ -#define ITE_I2CRSUR_SM 0x50 /* repeated START condition at standard mode */ - -/* STOP setup Time Register ITE_I2CPSUR */ - -/* FIFO Data Register ITE_I2CFDR */ -#define ITE_I2CFDR_MASK 0xff - -/* FIFO Byte Count Register ITE_I2CFBCR */ -#define ITE_I2CFBCR_MASK 0x3f - -/* FIFO Control Register ITE_I2CFCR */ -#define ITE_I2CFCR_FLUSH 0x01 /* Flush FIFO and reset the FIFO point - and I2CFSR */ -/* FIFO Status Register ITE_I2CFSR */ -#define ITE_I2CFSR_FO 0x01 /* FIFO is overrun when write */ -#define ITE_I2CFSR_FU 0x02 /* FIFO is underrun when read */ -#define ITE_I2CFSR_FF 0x04 /* FIFO is full when write */ -#define ITE_I2CFSR_FE 0x08 /* FIFO is empty when read */ - -#endif /* I2C_ITE_H */ diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 90f91d039ee2..7c9ab337d180 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -209,18 +209,6 @@ config I2C_ISA tristate depends on I2C -config I2C_ITE - tristate "ITE I2C Adapter" - depends on I2C && MIPS_ITE8172 - select I2C_ALGOITE - help - This supports the ITE8172 I2C peripheral found on some MIPS - systems. Say Y if you have one of these. You should also say Y for - the ITE I2C driver algorithm support above. - - This support is also available as a module. If so, the module - will be called i2c-ite. - config I2C_IXP4XX tristate "IXP4xx GPIO-Based I2C Interface" depends on I2C && ARCH_IXP4XX diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 493c87289b62..bf5fd078b292 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_I2C_I810) += i2c-i810.o obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o obj-$(CONFIG_I2C_ISA) += i2c-isa.o -obj-$(CONFIG_I2C_ITE) += i2c-ite.o obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o obj-$(CONFIG_I2C_IXP4XX) += i2c-ixp4xx.o obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o diff --git a/drivers/i2c/busses/i2c-ite.c b/drivers/i2c/busses/i2c-ite.c deleted file mode 100644 index f7d71869b3b9..000000000000 --- a/drivers/i2c/busses/i2c-ite.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - ------------------------------------------------------------------------- - i2c-adap-ite.c i2c-hw access for the IIC peripheral on the ITE MIPS system - ------------------------------------------------------------------------- - Hai-Pao Fan, MontaVista Software, Inc. - hpfan@mvista.com or source@mvista.com - - Copyright 2001 MontaVista Software Inc. - - ---------------------------------------------------------------------------- - This file was highly leveraged from i2c-elektor.c, which was created - by Simon G. Vogl and Hans Berglund: - - - Copyright (C) 1995-97 Simon G. Vogl - 1998-99 Hans Berglund - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -/* ------------------------------------------------------------------------- */ - -/* With some changes from Kyösti Mälkki and even - Frodo Looijaard */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include "../i2c-ite.h" - -#define DEFAULT_BASE 0x14014030 -#define ITE_IIC_IO_SIZE 0x40 -#define DEFAULT_IRQ 0 -#define DEFAULT_CLOCK 0x1b0e /* default 16MHz/(27+14) = 400KHz */ -#define DEFAULT_OWN 0x55 - -static int base; -static int irq; -static int clock; -static int own; - -static struct iic_ite gpi; -static wait_queue_head_t iic_wait; -static int iic_pending; -static spinlock_t lock; - -/* ----- local functions ---------------------------------------------- */ - -static void iic_ite_setiic(void *data, int ctl, short val) -{ - unsigned long j = jiffies + 10; - - pr_debug(" Write 0x%02x to 0x%x\n",(unsigned short)val, ctl&0xff); -#ifdef DEBUG - while (time_before(jiffies, j)) - schedule(); -#endif - outw(val,ctl); -} - -static short iic_ite_getiic(void *data, int ctl) -{ - short val; - - val = inw(ctl); - pr_debug("Read 0x%02x from 0x%x\n",(unsigned short)val, ctl&0xff); - return (val); -} - -/* Return our slave address. This is the address - * put on the I2C bus when another master on the bus wants to address us - * as a slave - */ -static int iic_ite_getown(void *data) -{ - return (gpi.iic_own); -} - - -static int iic_ite_getclock(void *data) -{ - return (gpi.iic_clock); -} - - -/* Put this process to sleep. We will wake up when the - * IIC controller interrupts. - */ -static void iic_ite_waitforpin(void) { - DEFINE_WAIT(wait); - int timeout = 2; - unsigned long flags; - - /* If interrupts are enabled (which they are), then put the process to - * sleep. This process will be awakened by two events -- either the - * the IIC peripheral interrupts or the timeout expires. - * If interrupts are not enabled then delay for a reasonable amount - * of time and return. - */ - if (gpi.iic_irq > 0) { - spin_lock_irqsave(&lock, flags); - if (iic_pending == 0) { - spin_unlock_irqrestore(&lock, flags); - prepare_to_wait(&iic_wait, &wait, TASK_INTERRUPTIBLE); - if (schedule_timeout(timeout*HZ)) { - spin_lock_irqsave(&lock, flags); - if (iic_pending == 1) { - iic_pending = 0; - } - spin_unlock_irqrestore(&lock, flags); - } - finish_wait(&iic_wait, &wait); - } else { - iic_pending = 0; - spin_unlock_irqrestore(&lock, flags); - } - } else { - udelay(100); - } -} - - -static irqreturn_t iic_ite_handler(int this_irq, void *dev_id) -{ - spin_lock(&lock); - iic_pending = 1; - spin_unlock(&lock); - - wake_up_interruptible(&iic_wait); - - return IRQ_HANDLED; -} - - -/* Lock the region of memory where I/O registers exist. Request our - * interrupt line and register its associated handler. - */ -static int iic_hw_resrc_init(void) -{ - if (!request_region(gpi.iic_base, ITE_IIC_IO_SIZE, "i2c")) - return -ENODEV; - - if (gpi.iic_irq <= 0) - return 0; - - if (request_irq(gpi.iic_irq, iic_ite_handler, 0, "ITE IIC", 0) < 0) - gpi.iic_irq = 0; - else - enable_irq(gpi.iic_irq); - - return 0; -} - - -static void iic_ite_release(void) -{ - if (gpi.iic_irq > 0) { - disable_irq(gpi.iic_irq); - free_irq(gpi.iic_irq, 0); - } - release_region(gpi.iic_base , 2); -} - -/* ------------------------------------------------------------------------ - * Encapsulate the above functions in the correct operations structure. - * This is only done when more than one hardware adapter is supported. - */ -static struct i2c_algo_iic_data iic_ite_data = { - NULL, - iic_ite_setiic, - iic_ite_getiic, - iic_ite_getown, - iic_ite_getclock, - iic_ite_waitforpin, - 80, 80, 100, /* waits, timeout */ -}; - -static struct i2c_adapter iic_ite_ops = { - .owner = THIS_MODULE, - .id = I2C_HW_I_IIC, - .algo_data = &iic_ite_data, - .name = "ITE IIC adapter", -}; - -/* Called when the module is loaded. This function starts the - * cascade of calls up through the hierarchy of i2c modules (i.e. up to the - * algorithm layer and into to the core layer) - */ -static int __init iic_ite_init(void) -{ - - struct iic_ite *piic = &gpi; - - printk(KERN_INFO "Initialize ITE IIC adapter module\n"); - if (base == 0) - piic->iic_base = DEFAULT_BASE; - else - piic->iic_base = base; - - if (irq == 0) - piic->iic_irq = DEFAULT_IRQ; - else - piic->iic_irq = irq; - - if (clock == 0) - piic->iic_clock = DEFAULT_CLOCK; - else - piic->iic_clock = clock; - - if (own == 0) - piic->iic_own = DEFAULT_OWN; - else - piic->iic_own = own; - - iic_ite_data.data = (void *)piic; - init_waitqueue_head(&iic_wait); - spin_lock_init(&lock); - if (iic_hw_resrc_init() == 0) { - if (i2c_iic_add_bus(&iic_ite_ops) < 0) - return -ENODEV; - } else { - return -ENODEV; - } - printk(KERN_INFO " found device at %#x irq %d.\n", - piic->iic_base, piic->iic_irq); - return 0; -} - - -static void iic_ite_exit(void) -{ - i2c_iic_del_bus(&iic_ite_ops); - iic_ite_release(); -} - -/* If modules is NOT defined when this file is compiled, then the MODULE_* - * macros will resolve to nothing - */ -MODULE_AUTHOR("MontaVista Software "); -MODULE_DESCRIPTION("I2C-Bus adapter routines for ITE IIC bus adapter"); -MODULE_LICENSE("GPL"); - -module_param(base, int, 0); -module_param(irq, int, 0); -module_param(clock, int, 0); -module_param(own, int, 0); - - -/* Called when module is loaded or when kernel is initialized. - * If MODULES is defined when this file is compiled, then this function will - * resolve to init_module (the function called when insmod is invoked for a - * module). Otherwise, this function is called early in the boot, when the - * kernel is intialized. Check out /include/init.h to see how this works. - */ -module_init(iic_ite_init); - -/* Resolves to module_cleanup when MODULES is defined. */ -module_exit(iic_ite_exit); diff --git a/include/linux/i2c-algo-ite.h b/include/linux/i2c-algo-ite.h deleted file mode 100644 index 0073fe96c76e..000000000000 --- a/include/linux/i2c-algo-ite.h +++ /dev/null @@ -1,72 +0,0 @@ -/* ------------------------------------------------------------------------- */ -/* i2c-algo-ite.h i2c driver algorithms for ITE IIC adapters */ -/* ------------------------------------------------------------------------- */ -/* Copyright (C) 1995-97 Simon G. Vogl - 1998-99 Hans Berglund - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -/* ------------------------------------------------------------------------- */ - -/* With some changes from Kyösti Mälkki and even - Frodo Looijaard */ - -/* Modifications by MontaVista Software, 2001 - Changes made to support the ITE IIC peripheral */ - - -#ifndef I2C_ALGO_ITE_H -#define I2C_ALGO_ITE_H 1 - -#include - -/* Example of a sequential read request: - struct i2c_iic_msg s_msg; - - s_msg.addr=device_address; - s_msg.len=length; - s_msg.buf=buffer; - s_msg.waddr=word_address; - ioctl(file,I2C_SREAD, &s_msg); - */ -#define I2C_SREAD 0x780 /* SREAD ioctl command */ - -struct i2c_iic_msg { - __u16 addr; /* device address */ - __u16 waddr; /* word address */ - short len; /* msg length */ - char *buf; /* pointer to msg data */ -}; - -#ifdef __KERNEL__ -struct i2c_adapter; - -struct i2c_algo_iic_data { - void *data; /* private data for lolevel routines */ - void (*setiic) (void *data, int ctl, int val); - int (*getiic) (void *data, int ctl); - int (*getown) (void *data); - int (*getclock) (void *data); - void (*waitforpin) (void); - - /* local settings */ - int udelay; - int mdelay; - int timeout; -}; - -int i2c_iic_add_bus(struct i2c_adapter *); -int i2c_iic_del_bus(struct i2c_adapter *); -#endif /* __KERNEL__ */ -#endif /* I2C_ALGO_ITE_H */ diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h index 36f0c5b0cbf7..00da370bbcd6 100644 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h @@ -210,9 +210,6 @@ /* --- MPC8xx PowerPC adapters */ #define I2C_HW_MPC8XX_EPON 0x110000 /* Eponymous MPC8xx I2C adapter */ -/* --- ITE based algorithms */ -#define I2C_HW_I_IIC 0x080000 /* controller on the ITE */ - /* --- PowerPC on-chip adapters */ #define I2C_HW_OCP 0x120000 /* IBM on-chip I2C adapter */ -- cgit v1.2.3 From ad04d5c3879dcf79ba0fa1826eab991f7b7a2de8 Mon Sep 17 00:00:00 2001 From: Hans-Frieder Vogt Date: Sun, 10 Dec 2006 21:21:29 +0100 Subject: i2c: Cleanups to the i2c-nforce2 bus driver Summary of changes: - fixes: o legacy I/O region size is 64 bytes, not 8 bytes - general cleanup: o removed code for the unsupported I2C block data, block data, proc call and block proc call transfer modes o removed detail warnings about unsupported modes that are covered in a general warning (unsupported transaction...) anyway o removed necessity of a definition of struct i2c_adapter o moved definition of struct i2c_algorithm, making forward declarations of nforce2_access and nforce2_func unnecessary - minor changes: o in the description mention the nForce 5xx chipsets o changes my e-mail address in MODULE_AUTHOR Theses cleanups shrink the driver binary size from 4.0 kB to 2.7 kB on i386. Signed-off-by: Hans-Frieder Vogt Signed-off-by: Jean Delvare --- Documentation/i2c/busses/i2c-nforce2 | 2 +- drivers/i2c/busses/i2c-nforce2.c | 89 ++++++------------------------------ 2 files changed, 15 insertions(+), 76 deletions(-) (limited to 'Documentation') diff --git a/Documentation/i2c/busses/i2c-nforce2 b/Documentation/i2c/busses/i2c-nforce2 index 5465ed0f4379..7f61fbc03f7f 100644 --- a/Documentation/i2c/busses/i2c-nforce2 +++ b/Documentation/i2c/busses/i2c-nforce2 @@ -14,7 +14,7 @@ Datasheet: not publicly available, but seems to be similar to the AMD-8111 SMBus 2.0 adapter. Authors: - Hans-Frieder Vogt , + Hans-Frieder Vogt , Thomas Leibold , Patrick Dreker diff --git a/drivers/i2c/busses/i2c-nforce2.c b/drivers/i2c/busses/i2c-nforce2.c index e0292e414ab2..ad37c10e7fec 100644 --- a/drivers/i2c/busses/i2c-nforce2.c +++ b/drivers/i2c/busses/i2c-nforce2.c @@ -35,7 +35,7 @@ nForce4 MCP55 0368 This driver supports the 2 SMBuses that are included in the MCP of the - nForce2/3/4 chipsets. + nForce2/3/4/5xx chipsets. */ /* Note: we assume there can only be one nForce2, with two SMBus interfaces */ @@ -52,8 +52,8 @@ #include MODULE_LICENSE("GPL"); -MODULE_AUTHOR ("Hans-Frieder Vogt "); -MODULE_DESCRIPTION("nForce2 SMBus driver"); +MODULE_AUTHOR ("Hans-Frieder Vogt "); +MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver"); struct nforce2_smbus { @@ -80,9 +80,6 @@ struct nforce2_smbus { #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */ #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */ #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */ -#define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data bytes */ -#define NVIDIA_SMB_ALRM_A (smbus->base + 0x25) /* alarm address */ -#define NVIDIA_SMB_ALRM_D (smbus->base + 0x26) /* 2 bytes alarm data */ #define NVIDIA_SMB_STS_DONE 0x80 #define NVIDIA_SMB_STS_ALRM 0x40 @@ -95,40 +92,17 @@ struct nforce2_smbus { #define NVIDIA_SMB_PRTCL_BYTE 0x04 #define NVIDIA_SMB_PRTCL_BYTE_DATA 0x06 #define NVIDIA_SMB_PRTCL_WORD_DATA 0x08 -#define NVIDIA_SMB_PRTCL_BLOCK_DATA 0x0a -#define NVIDIA_SMB_PRTCL_PROC_CALL 0x0c -#define NVIDIA_SMB_PRTCL_BLOCK_PROC_CALL 0x0d -#define NVIDIA_SMB_PRTCL_I2C_BLOCK_DATA 0x4a #define NVIDIA_SMB_PRTCL_PEC 0x80 static struct pci_driver nforce2_driver; -static s32 nforce2_access(struct i2c_adapter *adap, u16 addr, - unsigned short flags, char read_write, - u8 command, int size, union i2c_smbus_data *data); -static u32 nforce2_func(struct i2c_adapter *adapter); - - -static const struct i2c_algorithm smbus_algorithm = { - .smbus_xfer = nforce2_access, - .functionality = nforce2_func, -}; - -static struct i2c_adapter nforce2_adapter = { - .owner = THIS_MODULE, - .class = I2C_CLASS_HWMON, - .algo = &smbus_algorithm, -}; - -/* Return -1 on error. See smbus.h for more information */ +/* Return -1 on error */ static s32 nforce2_access(struct i2c_adapter * adap, u16 addr, unsigned short flags, char read_write, u8 command, int size, union i2c_smbus_data * data) { struct nforce2_smbus *smbus = adap->algo_data; unsigned char protocol, pec, temp; - unsigned char len = 0; /* to keep the compiler quiet */ - int i; protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ : NVIDIA_SMB_PRTCL_WRITE; @@ -163,35 +137,6 @@ static s32 nforce2_access(struct i2c_adapter * adap, u16 addr, protocol |= NVIDIA_SMB_PRTCL_WORD_DATA | pec; break; - case I2C_SMBUS_BLOCK_DATA: - outb_p(command, NVIDIA_SMB_CMD); - if (read_write == I2C_SMBUS_WRITE) { - len = min_t(u8, data->block[0], 32); - outb_p(len, NVIDIA_SMB_BCNT); - for (i = 0; i < len; i++) - outb_p(data->block[i + 1], NVIDIA_SMB_DATA+i); - } - protocol |= NVIDIA_SMB_PRTCL_BLOCK_DATA | pec; - break; - - case I2C_SMBUS_I2C_BLOCK_DATA: - len = min_t(u8, data->block[0], 32); - outb_p(command, NVIDIA_SMB_CMD); - outb_p(len, NVIDIA_SMB_BCNT); - if (read_write == I2C_SMBUS_WRITE) - for (i = 0; i < len; i++) - outb_p(data->block[i + 1], NVIDIA_SMB_DATA+i); - protocol |= NVIDIA_SMB_PRTCL_I2C_BLOCK_DATA; - break; - - case I2C_SMBUS_PROC_CALL: - dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n"); - return -1; - - case I2C_SMBUS_BLOCK_PROC_CALL: - dev_err(&adap->dev, "I2C_SMBUS_BLOCK_PROC_CALL not supported!\n"); - return -1; - default: dev_err(&adap->dev, "Unsupported transaction %d\n", size); return -1; @@ -227,19 +172,8 @@ static s32 nforce2_access(struct i2c_adapter * adap, u16 addr, break; case I2C_SMBUS_WORD_DATA: - /* case I2C_SMBUS_PROC_CALL: not supported */ data->word = inb_p(NVIDIA_SMB_DATA) | (inb_p(NVIDIA_SMB_DATA+1) << 8); break; - - case I2C_SMBUS_BLOCK_DATA: - /* case I2C_SMBUS_BLOCK_PROC_CALL: not supported */ - len = inb_p(NVIDIA_SMB_BCNT); - len = min_t(u8, len, 32); - case I2C_SMBUS_I2C_BLOCK_DATA: - for (i = 0; i < len; i++) - data->block[i+1] = inb_p(NVIDIA_SMB_DATA + i); - data->block[0] = len; - break; } return 0; @@ -250,10 +184,14 @@ static u32 nforce2_func(struct i2c_adapter *adapter) { /* other functionality might be possible, but is not tested */ return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | - I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA /* | - I2C_FUNC_SMBUS_BLOCK_DATA */; + I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA; } +static struct i2c_algorithm smbus_algorithm = { + .smbus_xfer = nforce2_access, + .functionality = nforce2_func, +}; + static struct pci_device_id nforce2_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) }, @@ -267,7 +205,6 @@ static struct pci_device_id nforce2_ids[] = { { 0 } }; - MODULE_DEVICE_TABLE (pci, nforce2_ids); @@ -291,7 +228,7 @@ static int __devinit nforce2_probe_smb (struct pci_dev *dev, int bar, } smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK; - smbus->size = 8; + smbus->size = 64; } smbus->dev = dev; @@ -300,7 +237,9 @@ static int __devinit nforce2_probe_smb (struct pci_dev *dev, int bar, smbus->base, smbus->base+smbus->size-1, name); return -1; } - smbus->adapter = nforce2_adapter; + smbus->adapter.owner = THIS_MODULE; + smbus->adapter.class = I2C_CLASS_HWMON; + smbus->adapter.algo = &smbus_algorithm; smbus->adapter.algo_data = smbus; smbus->adapter.dev.parent = &dev->dev; snprintf(smbus->adapter.name, I2C_NAME_SIZE, -- cgit v1.2.3 From a980a99ae5ada5260ddae15da45582dad32dbb93 Mon Sep 17 00:00:00 2001 From: Jason Gaston Date: Sun, 10 Dec 2006 21:21:31 +0100 Subject: i2c: i2c-i801 documentation update Add the Intel ICH9/ICH8/ESB2 SMBus Controller text to i2c-i801 documentation. Signed-off-by: Jason Gaston Signed-off-by: Jean Delvare --- Documentation/i2c/busses/i2c-i801 | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801 index e46c23458242..3db69a086c41 100644 --- a/Documentation/i2c/busses/i2c-i801 +++ b/Documentation/i2c/busses/i2c-i801 @@ -9,7 +9,10 @@ Supported adapters: * Intel 82801EB/ER (ICH5) (HW PEC supported, 32 byte buffer not supported) * Intel 6300ESB * Intel 82801FB/FR/FW/FRW (ICH6) - * Intel ICH7 + * Intel 82801G (ICH7) + * Intel 631xESB/632xESB (ESB2) + * Intel 82801H (ICH8) + * Intel ICH9 Datasheets: Publicly available at the Intel website Authors: -- cgit v1.2.3