From 700496fa11441b733c9e10a247e3a287d9b5a6e6 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 23 Oct 2019 16:49:53 +0200 Subject: drm/todo: Add entry to remove load/unload hooks They're midlayer, broken, and because of the old gunk, we can't fix them. For examples see the various checks in drm_mode_object.c against dev->registered, which cannot be enforced if the driver still uses the load hook. Unfortunately our biggest driver still uses load/unload, so this would be really great to get fixed. Cc: Alex Deucher Cc: Harry Wentland Reviewed-by: Thierry Reding Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20191023144953.28190-2-daniel.vetter@ffwll.ch --- Documentation/gpu/todo.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'Documentation') diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 6792fa9b6b6b..b3c0d517db93 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -351,6 +351,23 @@ connector register/unregister fixes Level: Intermediate +Remove load/unload callbacks from all non-DRIVER_LEGACY drivers +--------------------------------------------------------------- + +The load/unload callbacks in struct &drm_driver are very much midlayers, plus +for historical reasons they get the ordering wrong (and we can't fix that) +between setting up the &drm_driver structure and calling drm_dev_register(). + +- Rework drivers to no longer use the load/unload callbacks, directly coding the + load/unload sequence into the driver's probe function. + +- Once all non-DRIVER_LEGACY drivers are converted, disallow the load/unload + callbacks for all modern drivers. + +Contact: Daniel Vetter + +Level: Intermediate + Core refactorings ================= -- cgit v1.2.3 From 8a537de0f3d8b655cb901c948ed863bf0b23277b Mon Sep 17 00:00:00 2001 From: Leandro Ribeiro Date: Tue, 29 Oct 2019 22:12:11 -0300 Subject: drm/doc: Update IGT documentation The IGT documentation in this page is telling us to build it using make. According to commit 67993c1 ("automake: Point builders at meson") from the IGT project, this is deprecated and IGT should be built with meson. Instead of having a documentation for IGT in this page, point to their GitLab README, which should always be up to date. Signed-off-by: Leandro Ribeiro Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20191030011211.47942-1-leandrohr@riseup.net --- Documentation/gpu/drm-uapi.rst | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst index 94f90521f58c..996f7354e05c 100644 --- a/Documentation/gpu/drm-uapi.rst +++ b/Documentation/gpu/drm-uapi.rst @@ -254,36 +254,8 @@ Validating changes with IGT There's a collection of tests that aims to cover the whole functionality of DRM drivers and that can be used to check that changes to DRM drivers or the core don't regress existing functionality. This test suite is called IGT and -its code can be found in https://cgit.freedesktop.org/drm/igt-gpu-tools/. - -To build IGT, start by installing its build dependencies. In Debian-based -systems:: - - # apt-get build-dep intel-gpu-tools - -And in Fedora-based systems:: - - # dnf builddep intel-gpu-tools - -Then clone the repository:: - - $ git clone git://anongit.freedesktop.org/drm/igt-gpu-tools - -Configure the build system and start the build:: - - $ cd igt-gpu-tools && ./autogen.sh && make -j6 - -Download the piglit dependency:: - - $ ./scripts/run-tests.sh -d - -And run the tests:: - - $ ./scripts/run-tests.sh -t kms -t core -s - -run-tests.sh is a wrapper around piglit that will execute the tests matching -the -t options. A report in HTML format will be available in -./results/html/index.html. Results can be compared with piglit. +its code and instructions to build and run can be found in +https://gitlab.freedesktop.org/drm/igt-gpu-tools/. Display CRC Support ------------------- -- cgit v1.2.3 From 80ae0369d3e4b8559c04e2b4de2b86640908f2fd Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Wed, 6 Nov 2019 13:47:26 +0100 Subject: drm/todo: Convert drivers to generic fbdev emulation This replaces the original TODO item for drm_fb_helper_fbdev_setup() and _teardown(), which are deprecated. v2: * remove driver-specific comments * list some basic requirements * keep a TODO item on drm_fb_helper_init() Signed-off-by: Thomas Zimmermann Reviewed-by: Noralf Trønnes Link: https://patchwork.freedesktop.org/patch/msgid/20191106124727.11641-2-tzimmermann@suse.de --- Documentation/gpu/todo.rst | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index b3c0d517db93..3ec509381fc5 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -171,21 +171,12 @@ Contact: Maintainer of the driver you plan to convert Level: Intermediate -Convert drivers to use drm_fb_helper_fbdev_setup/teardown() ------------------------------------------------------------ +Convert drivers to use drm_fbdev_generic_setup() +------------------------------------------------ -Most drivers can use drm_fb_helper_fbdev_setup() except maybe: - -- amdgpu which has special logic to decide whether to call - drm_helper_disable_unused_functions() - -- armada which isn't atomic and doesn't call - drm_helper_disable_unused_functions() - -- i915 which calls drm_fb_helper_initial_config() in a worker - -Drivers that use drm_framebuffer_remove() to clean up the fbdev framebuffer can -probably use drm_fb_helper_fbdev_teardown(). +Most drivers can use drm_fbdev_generic_setup(). Driver have to implement +atomic modesetting and GEM vmap support. Current generic fbdev emulation +expects the framebuffer in system memory (or system-like memory). Contact: Maintainer of the driver you plan to convert @@ -328,8 +319,8 @@ drm_fb_helper tasks these igt tests need to be fixed: kms_fbcon_fbt@psr and kms_fbcon_fbt@psr-suspend. -- The max connector argument for drm_fb_helper_init() and - drm_fb_helper_fbdev_setup() isn't used anymore and can be removed. +- The max connector argument for drm_fb_helper_init() isn't used anymore and + can be removed. - The helper doesn't keep an array of connectors anymore so these can be removed: drm_fb_helper_single_add_all_connectors(), -- cgit v1.2.3 From 8d938df2056253218555800ea39a6ec391669f18 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 14 Nov 2019 14:15:24 +0100 Subject: drm/panel: Add DT bindings for Sony ACX424AKP This adds device tree bindings for the Sony ACX424AKP panel. Let's use YAML. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20191114131525.3988-1-linus.walleij@linaro.org --- .../bindings/display/panel/sony,acx424akp.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml b/Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml new file mode 100644 index 000000000000..185dcc8fd1f9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sony,acx424akp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony ACX424AKP 4" 480x864 AMOLED panel + +maintainers: + - Linus Walleij + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sony,acx424akp + reg: true + reset-gpios: true + vddi-supply: + description: regulator that supplies the vddi voltage + enforce-video-mode: true + +required: + - compatible + - reg + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi-controller@a0351000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0351000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sony,acx424akp"; + reg = <0>; + vddi-supply = <&foo>; + reset-gpios = <&foo_gpio 0 GPIO_ACTIVE_LOW>; + }; + }; + +... -- cgit v1.2.3 From 2c81bdc8024ef6f81dfecab86bcb97a8694dcd1e Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 27 Nov 2019 19:00:35 +0100 Subject: drm/todo: Add entry for fb funcs related cleanups We're doing a great job for really simple drivers right now, but still a lot of boilerplate for the bigger ones. Acked-by: Thomas Zimmermann Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20191127180035.416209-3-daniel.vetter@ffwll.ch --- Documentation/gpu/todo.rst | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'Documentation') diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 3ec509381fc5..2d85f37284a1 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -182,6 +182,32 @@ Contact: Maintainer of the driver you plan to convert Level: Intermediate +drm_framebuffer_funcs and drm_mode_config_funcs.fb_create cleanup +----------------------------------------------------------------- + +A lot more drivers could be switched over to the drm_gem_framebuffer helpers. +Various hold-ups: + +- Need to switch over to the generic dirty tracking code using + drm_atomic_helper_dirtyfb first (e.g. qxl). + +- Need to switch to drm_fbdev_generic_setup(), otherwise a lot of the custom fb + setup code can't be deleted. + +- Many drivers wrap drm_gem_fb_create() only to check for valid formats. For + atomic drivers we could check for valid formats by calling + drm_plane_check_pixel_format() against all planes, and pass if any plane + supports the format. For non-atomic that's not possible since like the format + list for the primary plane is fake and we'd therefor reject valid formats. + +- Many drivers subclass drm_framebuffer, we'd need a embedding compatible + version of the varios drm_gem_fb_create functions. Maybe called + drm_gem_fb_create/_with_dirty/_with_funcs as needed. + +Contact: Daniel Vetter + +Level: Intermediate + Clean up mmap forwarding ------------------------ -- cgit v1.2.3 From 65b2f7c43c6f087784db309e8a75bae3d2266520 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 8 Nov 2019 15:56:54 +0200 Subject: drm: Inline drm_color_lut_extract() This thing can get called several thousand times per LUT so seems like we want to inline it to: - avoid the function call overhead - allow constant folding A quick synthetic test (w/o any hardware interaction) with a ridiculously large LUT size shows about 50% reduction in runtime on my HSW and BSW boxes. Slightly less with more reasonable LUT size but still easily measurable in tens of microseconds. v2: Include drm_color_mgmt.h in the .rst (Daniel) Cc: Daniel Vetter Signed-off-by: Ville Syrjälä Reviewed-by: Nicholas Kazlauskas Link: https://patchwork.freedesktop.org/patch/msgid/20191108135654.12907-1-ville.syrjala@linux.intel.com --- Documentation/gpu/drm-kms.rst | 3 +++ drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------ include/drm/drm_color_mgmt.h | 24 +++++++++++++++++++++++- 3 files changed, 26 insertions(+), 25 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 23a3c986ef6d..c68588ce4090 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -479,6 +479,9 @@ Color Management Properties .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c :export: +.. kernel-doc:: include/drm/drm_color_mgmt.h + :internal: + Tile Group Property ------------------- diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index ba71e3b827f1..c93123ff7c21 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -108,30 +108,6 @@ * standard enum values supported by the DRM plane. */ -/** - * drm_color_lut_extract - clamp and round LUT entries - * @user_input: input value - * @bit_precision: number of bits the hw LUT supports - * - * Extract a degamma/gamma LUT value provided by user (in the form of - * &drm_color_lut entries) and round it to the precision supported by the - * hardware. - */ -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision) -{ - uint32_t val = user_input; - uint32_t max = 0xffff >> (16 - bit_precision); - - /* Round only if we're not using full precision. */ - if (bit_precision < 16) { - val += 1UL << (16 - bit_precision - 1); - val >>= 16 - bit_precision; - } - - return clamp_val(val, 0, max); -} -EXPORT_SYMBOL(drm_color_lut_extract); - /** * drm_color_ctm_s31_32_to_qm_n * diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 997a42ab29f5..81c298488b0c 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -29,7 +29,29 @@ struct drm_crtc; struct drm_plane; -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision); +/** + * drm_color_lut_extract - clamp and round LUT entries + * @user_input: input value + * @bit_precision: number of bits the hw LUT supports + * + * Extract a degamma/gamma LUT value provided by user (in the form of + * &drm_color_lut entries) and round it to the precision supported by the + * hardware. + */ +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision) +{ + u32 val = user_input; + u32 max = 0xffff >> (16 - bit_precision); + + /* Round only if we're not using full precision. */ + if (bit_precision < 16) { + val += 1UL << (16 - bit_precision - 1); + val >>= 16 - bit_precision; + } + + return clamp_val(val, 0, max); +} + u64 drm_color_ctm_s31_32_to_qm_n(u64 user_input, u32 m, u32 n); void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, -- cgit v1.2.3 From 621dab99847821d671e46509c4775d905c72a763 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 16 Oct 2019 08:51:46 -0500 Subject: dt-bindings: Add Logic PD Type 28 display panel This patch adds documentation of device tree bindings for the WVGA panel Logic PD Type 28 display. Signed-off-by: Adam Ford Reviewed-by: Rob Herring Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20191016135147.7743-2-aford173@gmail.com --- .../bindings/display/panel/logicpd,type28.yaml | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/logicpd,type28.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/logicpd,type28.yaml b/Documentation/devicetree/bindings/display/panel/logicpd,type28.yaml new file mode 100644 index 000000000000..2834287b8d88 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/logicpd,type28.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/logicpd,type28.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Logic PD Type 28 4.3" WQVGA TFT LCD panel + +maintainers: + - Adam Ford + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: logicpd,type28 + + power-supply: true + enable-gpios: true + backlight: true + port: true + +required: + - compatible + +additionalProperties: false + +examples: + - | + lcd0: display { + compatible = "logicpd,type28"; + enable-gpios = <&gpio5 27 0>; + backlight = <&backlight>; + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + +... -- cgit v1.2.3 From dc190678534ee0f9042a65db1613ab1e59582bff Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 28 Nov 2019 10:07:26 +0100 Subject: drm/panel: Add generic DSI display controller YAML bindings This adds a starting point for processing and defining generic bindings used by DSI display controllers and panels attached to the virtual DSI ports. Cc: Stephan Gerhold Cc: devicetree@vger.kernel.org Suggested-by: Rob Herring Link: https://patchwork.freedesktop.org/patch/msgid/20191128090726.51107-1-linus.walleij@linaro.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/display/dsi-controller.yaml | 91 ++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/dsi-controller.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/dsi-controller.yaml b/Documentation/devicetree/bindings/display/dsi-controller.yaml new file mode 100644 index 000000000000..fd986c36c737 --- /dev/null +++ b/Documentation/devicetree/bindings/display/dsi-controller.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/dsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for DSI Display Panels + +maintainers: + - Linus Walleij + +description: | + This document defines device tree properties common to DSI, Display + Serial Interface controllers and attached panels. It doesn't constitute + a device tree binding specification by itself but is meant to be referenced + by device tree bindings. + + When referenced from panel device tree bindings the properties defined in + this document are defined as follows. The panel device tree bindings are + responsible for defining whether each property is required or optional. + + Notice: this binding concerns DSI panels connected directly to a master + without any intermediate port graph to the panel. Each DSI master + can control one to four virtual channels to one panel. Each virtual + channel should have a node "panel" for their virtual channel with their + reg-property set to the virtual channel number, usually there is just + one virtual channel, number 0. + +properties: + $nodename: + pattern: "^dsi-controller(@.*)?$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^panel@[0-3]$": + description: Panels connected to the DSI link + type: object + + properties: + reg: + minimum: 0 + maximum: 3 + description: + The virtual channel number of a DSI peripheral. Must be in the range + from 0 to 3, as DSI uses a 2-bit addressing scheme. Some DSI + peripherals respond to more than a single virtual channel. In that + case the reg property can take multiple entries, one for each virtual + channel that the peripheral responds to. + + clock-master: + type: boolean + description: + Should be enabled if the host is being used in conjunction with + another DSI host to drive the same peripheral. Hardware supporting + such a configuration generally requires the data on both the busses + to be driven by the same clock. Only the DSI host instance + controlling this clock should contain this property. + + enforce-video-mode: + type: boolean + description: + The best option is usually to run a panel in command mode, as this + gives better control over the panel hardware. However for different + reasons like broken hardware, missing features or testing, it may be + useful to be able to force a command mode-capable panel into video + mode. + + required: + - reg + +examples: + - | + #include + dsi-controller@a0351000 { + reg = <0xa0351000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "sony,acx424akp"; + reg = <0>; + vddi-supply = <&ab8500_ldo_aux1_reg>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + }; + +... -- cgit v1.2.3 From 6f91f44dea701c7504dfe8af920f493ea0eed9cf Mon Sep 17 00:00:00 2001 From: Gabriela Bittencourt Date: Mon, 4 Nov 2019 13:27:05 -0300 Subject: drm/doc: Add VKMS module description and use to "Testing and Validation" Add a description on VKMS module and the cases in which it should be used. There's a brief explanation on how to set it and use it in a VM, along with an example of running an igt-test. Changes since V3: Rodrigo: - Change the log message to imperative - Fix some bad spelling/writing - Add a blank line before enumeration Changes since V2: Andre: - Avoid repetition of words in the same sentence; - Make the explanation on 'setting the kernel' shorter, eliminate the 'make menuconfig' command; - Add tab on enumeration to have one line per item; - Clarify from each machine igt-tests commands should be ran on. Reviewed-by: Rodrigo Siqueira Signed-off-by: Gabriela Bittencourt Signed-off-by: Rodrigo Siqueira Link: https://patchwork.freedesktop.org/patch/msgid/20191104162705.19735-1-gabrielabittencourt00@gmail.com --- Documentation/gpu/drm-uapi.rst | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'Documentation') diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst index 996f7354e05c..56fec6ed1ad8 100644 --- a/Documentation/gpu/drm-uapi.rst +++ b/Documentation/gpu/drm-uapi.rst @@ -257,6 +257,43 @@ core don't regress existing functionality. This test suite is called IGT and its code and instructions to build and run can be found in https://gitlab.freedesktop.org/drm/igt-gpu-tools/. +Using VKMS to test DRM API +-------------------------- + +VKMS is a software-only model of a KMS driver that is useful for testing +and for running compositors. VKMS aims to enable a virtual display without +the need for a hardware display capability. These characteristics made VKMS +a perfect tool for validating the DRM core behavior and also support the +compositor developer. VKMS makes it possible to test DRM functions in a +virtual machine without display, simplifying the validation of some of the +core changes. + +To Validate changes in DRM API with VKMS, start setting the kernel: make +sure to enable VKMS module; compile the kernel with the VKMS enabled and +install it in the target machine. VKMS can be run in a Virtual Machine +(QEMU, virtme or similar). It's recommended the use of KVM with the minimum +of 1GB of RAM and four cores. + +It's possible to run the IGT-tests in a VM in two ways: + + 1. Use IGT inside a VM + 2. Use IGT from the host machine and write the results in a shared directory. + +As follow, there is an example of using a VM with a shared directory with +the host machine to run igt-tests. As an example it's used virtme:: + + $ virtme-run --rwdir /path/for/shared_dir --kdir=path/for/kernel/directory --mods=auto + +Run the igt-tests in the guest machine, as example it's ran the 'kms_flip' +tests:: + + $ /path/for/igt-gpu-tools/scripts/run-tests.sh -p -s -t "kms_flip.*" -v + +In this example, instead of build the igt_runner, Piglit is used +(-p option); it's created html summary of the tests results and it's saved +in the folder "igt-gpu-tools/results"; it's executed only the igt-tests +matching the -t option. + Display CRC Support ------------------- -- cgit v1.2.3 From 3c9abe886a95d91b3d1e1cc16af4322a1abe31d5 Mon Sep 17 00:00:00 2001 From: Daniele Ceraolo Spurio Date: Thu, 5 Dec 2019 14:02:42 -0800 Subject: drm/i915/guc: kill the GuC client We now only use 1 client without any plan to add more. The client is also only holding information about the WQ and the process desc, so we can just move those in the intel_guc structure and always use stage_id 0. v2: fix comment (John) v3: fix the comment for real, fix kerneldoc Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost Reviewed-by: John Harrison Link: https://patchwork.freedesktop.org/patch/msgid/20191205220243.27403-4-daniele.ceraolospurio@intel.com --- Documentation/gpu/i915.rst | 3 - drivers/gpu/drm/i915/gt/intel_reset.c | 6 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 8 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 - drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 276 ++++++---------------- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h | 45 +--- drivers/gpu/drm/i915/i915_debugfs.c | 11 - 7 files changed, 89 insertions(+), 261 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index d0947c5c4ab8..e539c42a3e78 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -466,9 +466,6 @@ GuC-based command submission .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c :doc: GuC-based command submission -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c - :internal: - HuC --- .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 0e94b720c993..8408cb84e52c 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -21,6 +21,7 @@ #include "intel_reset.h" #include "uc/intel_guc.h" +#include "uc/intel_guc_submission.h" #define RESET_MAX_RETRIES 3 @@ -1085,6 +1086,7 @@ static inline int intel_gt_reset_engine(struct intel_engine_cs *engine) int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) { struct intel_gt *gt = engine->gt; + bool uses_guc = intel_engine_in_guc_submission_mode(engine); int ret; GEM_TRACE("%s flags=%lx\n", engine->name, gt->reset.flags); @@ -1100,14 +1102,14 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) "Resetting %s for %s\n", engine->name, msg); atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]); - if (!engine->gt->uc.guc.execbuf_client) + if (!uses_guc) ret = intel_gt_reset_engine(engine); else ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine); if (ret) { /* If we fail here, we expect to fallback to a global reset */ DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n", - engine->gt->uc.guc.execbuf_client ? "GuC " : "", + uses_guc ? "GuC " : "", engine->name, ret); goto out; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index b2d1766e689a..cd09c912e361 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -46,9 +46,13 @@ struct intel_guc { struct i915_vma *stage_desc_pool; void *stage_desc_pool_vaddr; - struct ida stage_ids; - struct intel_guc_client *execbuf_client; + struct i915_vma *workqueue; + void *workqueue_vaddr; + spinlock_t wq_lock; + + struct i915_vma *proc_desc; + void *proc_desc_vaddr; /* Control params for fw initialization */ u32 params[GUC_CTL_MAX_DWORDS]; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h index 1e8e4af7d9ca..a6b733c146c9 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h @@ -31,7 +31,6 @@ #define GUC_DOORBELL_INVALID 256 -#define GUC_PD_SIZE (PAGE_SIZE) #define GUC_WQ_SIZE (PAGE_SIZE * 2) /* Work queue item header definitions */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 334bd4ded642..172220e83079 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -27,24 +27,13 @@ * code) matches the old submission model and will be updated as part of the * upgrade to the new flow. * - * GuC client: - * A intel_guc_client refers to a submission path through GuC. Currently, there - * is only one client, which is charged with all submissions to the GuC. This - * struct is the owner of a process descriptor and a workqueue (both of them - * inside a single gem object that contains all required pages for these - * elements). - * * GuC stage descriptor: * During initialization, the driver allocates a static pool of 1024 such - * descriptors, and shares them with the GuC. - * Currently, there exists a 1:1 mapping between a intel_guc_client and a - * guc_stage_desc (via the client's stage_id), so effectively only one - * gets used. This stage descriptor lets the GuC know about the workqueue and + * descriptors, and shares them with the GuC. Currently, we only use one + * descriptor. This stage descriptor lets the GuC know about the workqueue and * process descriptor. Theoretically, it also lets the GuC know about our HW * contexts (context ID, etc...), but we actually employ a kind of submission - * where the GuC uses the LRCA sent via the work item instead (the single - * guc_stage_desc associated to execbuf client contains information about the - * default kernel context only, but this is essentially unused). This is called + * where the GuC uses the LRCA sent via the work item instead. This is called * a "proxy" submission. * * The Scratch registers: @@ -71,33 +60,45 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb) return rb_entry(rb, struct i915_priolist, node); } -static inline bool is_high_priority(struct intel_guc_client *client) +static struct guc_stage_desc *__get_stage_desc(struct intel_guc *guc, u32 id) { - return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH || - client->priority == GUC_CLIENT_PRIORITY_HIGH); + struct guc_stage_desc *base = guc->stage_desc_pool_vaddr; + + return &base[id]; } -static struct guc_stage_desc *__get_stage_desc(struct intel_guc_client *client) +static int guc_workqueue_create(struct intel_guc *guc) { - struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr; - - return &base[client->stage_id]; + return intel_guc_allocate_and_map_vma(guc, GUC_WQ_SIZE, &guc->workqueue, + &guc->workqueue_vaddr); } -static inline struct guc_process_desc * -__get_process_desc(struct intel_guc_client *client) +static void guc_workqueue_destroy(struct intel_guc *guc) { - return client->vaddr; + i915_vma_unpin_and_release(&guc->workqueue, I915_VMA_RELEASE_MAP); } /* * Initialise the process descriptor shared with the GuC firmware. */ -static void guc_proc_desc_init(struct intel_guc_client *client) +static int guc_proc_desc_create(struct intel_guc *guc) +{ + const u32 size = PAGE_ALIGN(sizeof(struct guc_process_desc)); + + return intel_guc_allocate_and_map_vma(guc, size, &guc->proc_desc, + &guc->proc_desc_vaddr); +} + +static void guc_proc_desc_destroy(struct intel_guc *guc) +{ + i915_vma_unpin_and_release(&guc->proc_desc, I915_VMA_RELEASE_MAP); +} + +static void guc_proc_desc_init(struct intel_guc *guc) { struct guc_process_desc *desc; - desc = memset(__get_process_desc(client), 0, sizeof(*desc)); + desc = memset(guc->proc_desc_vaddr, 0, sizeof(*desc)); /* * XXX: pDoorbell and WQVBaseAddress are pointers in process address @@ -108,39 +109,27 @@ static void guc_proc_desc_init(struct intel_guc_client *client) desc->wq_base_addr = 0; desc->db_base_addr = 0; - desc->stage_id = client->stage_id; desc->wq_size_bytes = GUC_WQ_SIZE; desc->wq_status = WQ_STATUS_ACTIVE; - desc->priority = client->priority; + desc->priority = GUC_CLIENT_PRIORITY_KMD_NORMAL; } -static void guc_proc_desc_fini(struct intel_guc_client *client) +static void guc_proc_desc_fini(struct intel_guc *guc) { - struct guc_process_desc *desc; - - desc = __get_process_desc(client); - memset(desc, 0, sizeof(*desc)); + memset(guc->proc_desc_vaddr, 0, sizeof(struct guc_process_desc)); } static int guc_stage_desc_pool_create(struct intel_guc *guc) { u32 size = PAGE_ALIGN(sizeof(struct guc_stage_desc) * GUC_MAX_STAGE_DESCRIPTORS); - int ret; - - ret = intel_guc_allocate_and_map_vma(guc, size, &guc->stage_desc_pool, - &guc->stage_desc_pool_vaddr); - if (ret) - return ret; - - ida_init(&guc->stage_ids); - return 0; + return intel_guc_allocate_and_map_vma(guc, size, &guc->stage_desc_pool, + &guc->stage_desc_pool_vaddr); } static void guc_stage_desc_pool_destroy(struct intel_guc *guc) { - ida_destroy(&guc->stage_ids); i915_vma_unpin_and_release(&guc->stage_desc_pool, I915_VMA_RELEASE_MAP); } @@ -148,58 +137,49 @@ static void guc_stage_desc_pool_destroy(struct intel_guc *guc) * Initialise/clear the stage descriptor shared with the GuC firmware. * * This descriptor tells the GuC where (in GGTT space) to find the important - * data structures relating to this client (process descriptor, write queue, + * data structures related to work submission (process descriptor, write queue, * etc). */ -static void guc_stage_desc_init(struct intel_guc_client *client) +static void guc_stage_desc_init(struct intel_guc *guc) { - struct intel_guc *guc = client->guc; struct guc_stage_desc *desc; - u32 gfx_addr; - desc = __get_stage_desc(client); + /* we only use 1 stage desc, so hardcode it to 0 */ + desc = __get_stage_desc(guc, 0); memset(desc, 0, sizeof(*desc)); desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE | GUC_STAGE_DESC_ATTR_KERNEL; - if (is_high_priority(client)) - desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT; - desc->stage_id = client->stage_id; - desc->priority = client->priority; - /* - * The process descriptor and workqueue are all parts of the client - * object, which the GuC will reference via the GGTT - */ - gfx_addr = intel_guc_ggtt_offset(guc, client->vma); - desc->process_desc = gfx_addr; - desc->wq_addr = gfx_addr + GUC_PD_SIZE; - desc->wq_size = GUC_WQ_SIZE; + desc->stage_id = 0; + desc->priority = GUC_CLIENT_PRIORITY_KMD_NORMAL; - desc->desc_private = ptr_to_u64(client); + desc->process_desc = intel_guc_ggtt_offset(guc, guc->proc_desc); + desc->wq_addr = intel_guc_ggtt_offset(guc, guc->workqueue); + desc->wq_size = GUC_WQ_SIZE; } -static void guc_stage_desc_fini(struct intel_guc_client *client) +static void guc_stage_desc_fini(struct intel_guc *guc) { struct guc_stage_desc *desc; - desc = __get_stage_desc(client); + desc = __get_stage_desc(guc, 0); memset(desc, 0, sizeof(*desc)); } /* Construct a Work Item and append it to the GuC's Work Queue */ -static void guc_wq_item_append(struct intel_guc_client *client, +static void guc_wq_item_append(struct intel_guc *guc, u32 target_engine, u32 context_desc, u32 ring_tail, u32 fence_id) { /* wqi_len is in DWords, and does not include the one-word header */ const size_t wqi_size = sizeof(struct guc_wq_item); const u32 wqi_len = wqi_size / sizeof(u32) - 1; - struct guc_process_desc *desc = __get_process_desc(client); + struct guc_process_desc *desc = guc->proc_desc_vaddr; struct guc_wq_item *wqi; u32 wq_off; - lockdep_assert_held(&client->wq_lock); + lockdep_assert_held(&guc->wq_lock); /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we * should not have the case where structure wqi is across page, neither @@ -219,8 +199,7 @@ static void guc_wq_item_append(struct intel_guc_client *client, GUC_WQ_SIZE) < wqi_size); GEM_BUG_ON(wq_off & (wqi_size - 1)); - /* WQ starts from the page after process_desc */ - wqi = client->vaddr + wq_off + GUC_PD_SIZE; + wqi = guc->workqueue_vaddr + wq_off; /* Now fill in the 4-word work queue item */ wqi->header = WQ_TYPE_INORDER | @@ -238,12 +217,11 @@ static void guc_wq_item_append(struct intel_guc_client *client, static void guc_add_request(struct intel_guc *guc, struct i915_request *rq) { - struct intel_guc_client *client = guc->execbuf_client; struct intel_engine_cs *engine = rq->engine; u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc); u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64); - guc_wq_item_append(client, engine->guc_id, ctx_desc, + guc_wq_item_append(guc, engine->guc_id, ctx_desc, ring_tail, rq->fence.seqno); } @@ -266,9 +244,8 @@ static void guc_submit(struct intel_engine_cs *engine, struct i915_request **end) { struct intel_guc *guc = &engine->gt->uc.guc; - struct intel_guc_client *client = guc->execbuf_client; - spin_lock(&client->wq_lock); + spin_lock(&guc->wq_lock); do { struct i915_request *rq = *out++; @@ -277,7 +254,7 @@ static void guc_submit(struct intel_engine_cs *engine, guc_add_request(guc, rq); } while (out != end); - spin_unlock(&client->wq_lock); + spin_unlock(&guc->wq_lock); } static inline int rq_prio(const struct i915_request *rq) @@ -528,126 +505,6 @@ static void guc_reset_finish(struct intel_engine_cs *engine) * path of guc_submit() above. */ -/** - * guc_client_alloc() - Allocate an intel_guc_client - * @guc: the intel_guc structure - * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW - * The kernel client to replace ExecList submission is created with - * NORMAL priority. Priority of a client for scheduler can be HIGH, - * while a preemption context can use CRITICAL. - * - * Return: An intel_guc_client object if success, else NULL. - */ -static struct intel_guc_client * -guc_client_alloc(struct intel_guc *guc, u32 priority) -{ - struct intel_guc_client *client; - struct i915_vma *vma; - void *vaddr; - int ret; - - client = kzalloc(sizeof(*client), GFP_KERNEL); - if (!client) - return ERR_PTR(-ENOMEM); - - client->guc = guc; - client->priority = priority; - spin_lock_init(&client->wq_lock); - - ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS, - GFP_KERNEL); - if (ret < 0) - goto err_client; - - client->stage_id = ret; - - /* The first page is proc_desc. Two following pages are wq. */ - vma = intel_guc_allocate_vma(guc, GUC_PD_SIZE + GUC_WQ_SIZE); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto err_id; - } - - /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ - client->vma = vma; - - vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); - if (IS_ERR(vaddr)) { - ret = PTR_ERR(vaddr); - goto err_vma; - } - client->vaddr = vaddr; - - DRM_DEBUG_DRIVER("new priority %u client %p: stage_id %u\n", - priority, client, client->stage_id); - - return client; - -err_vma: - i915_vma_unpin_and_release(&client->vma, 0); -err_id: - ida_simple_remove(&guc->stage_ids, client->stage_id); -err_client: - kfree(client); - return ERR_PTR(ret); -} - -static void guc_client_free(struct intel_guc_client *client) -{ - i915_vma_unpin_and_release(&client->vma, I915_VMA_RELEASE_MAP); - ida_simple_remove(&client->guc->stage_ids, client->stage_id); - kfree(client); -} - -static int guc_clients_create(struct intel_guc *guc) -{ - struct intel_guc_client *client; - - GEM_BUG_ON(guc->execbuf_client); - - client = guc_client_alloc(guc, GUC_CLIENT_PRIORITY_KMD_NORMAL); - if (IS_ERR(client)) { - DRM_ERROR("Failed to create GuC client for submission!\n"); - return PTR_ERR(client); - } - guc->execbuf_client = client; - - return 0; -} - -static void guc_clients_destroy(struct intel_guc *guc) -{ - struct intel_guc_client *client; - - client = fetch_and_zero(&guc->execbuf_client); - if (client) - guc_client_free(client); -} - -static void __guc_client_enable(struct intel_guc_client *client) -{ - guc_proc_desc_init(client); - guc_stage_desc_init(client); -} - -static void __guc_client_disable(struct intel_guc_client *client) -{ - /* Note: By the time we're here, GuC may have already been reset */ - guc_stage_desc_fini(client); - guc_proc_desc_fini(client); -} - -static void guc_clients_enable(struct intel_guc *guc) -{ - __guc_client_enable(guc->execbuf_client); -} - -static void guc_clients_disable(struct intel_guc *guc) -{ - if (guc->execbuf_client) - __guc_client_disable(guc->execbuf_client); -} - /* * Set up the memory resources to be shared with the GuC (via the GGTT) * at firmware loading time. @@ -668,12 +525,20 @@ int intel_guc_submission_init(struct intel_guc *guc) */ GEM_BUG_ON(!guc->stage_desc_pool); - ret = guc_clients_create(guc); + ret = guc_workqueue_create(guc); if (ret) goto err_pool; + ret = guc_proc_desc_create(guc); + if (ret) + goto err_workqueue; + + spin_lock_init(&guc->wq_lock); + return 0; +err_workqueue: + guc_workqueue_destroy(guc); err_pool: guc_stage_desc_pool_destroy(guc); return ret; @@ -681,10 +546,11 @@ err_pool: void intel_guc_submission_fini(struct intel_guc *guc) { - guc_clients_destroy(guc); - - if (guc->stage_desc_pool) + if (guc->stage_desc_pool) { + guc_proc_desc_destroy(guc); + guc_workqueue_destroy(guc); guc_stage_desc_pool_destroy(guc); + } } static void guc_interrupts_capture(struct intel_gt *gt) @@ -770,9 +636,8 @@ void intel_guc_submission_enable(struct intel_guc *guc) sizeof(struct guc_wq_item) * I915_NUM_ENGINES > GUC_WQ_SIZE); - GEM_BUG_ON(!guc->execbuf_client); - - guc_clients_enable(guc); + guc_proc_desc_init(guc); + guc_stage_desc_init(guc); /* Take over from manual control of ELSP (execlists) */ guc_interrupts_capture(gt); @@ -789,8 +654,12 @@ void intel_guc_submission_disable(struct intel_guc *guc) GEM_BUG_ON(gt->awake); /* GT should be parked first */ + /* Note: By the time we're here, GuC may have already been reset */ + guc_interrupts_release(gt); - guc_clients_disable(guc); + + guc_stage_desc_fini(guc); + guc_proc_desc_fini(guc); } static bool __guc_submission_support(struct intel_guc *guc) @@ -808,3 +677,8 @@ void intel_guc_submission_init_early(struct intel_guc *guc) { guc->submission_supported = __guc_submission_support(guc); } + +bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine) +{ + return engine->set_default_submission == guc_set_default_submission; +} diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h index e2deb4e6f42a..e402a2932592 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h @@ -6,48 +6,10 @@ #ifndef _INTEL_GUC_SUBMISSION_H_ #define _INTEL_GUC_SUBMISSION_H_ -#include +#include -#include "gt/intel_engine_types.h" - -#include "i915_gem.h" -#include "i915_selftest.h" - -struct drm_i915_private; - -/* - * This structure primarily describes the GEM object shared with the GuC. - * The specs sometimes refer to this object as a "GuC context", but we use - * the term "client" to avoid confusion with hardware contexts. This - * GEM object is held for the entire lifetime of our interaction with - * the GuC, being allocated before the GuC is loaded with its firmware. - * Because there's no way to update the address used by the GuC after - * initialisation, the shared object must stay pinned into the GGTT as - * long as the GuC is in use. We also keep the first page (only) mapped - * into kernel address space, as it includes shared data that must be - * updated on every request submission. - * - * The single GEM object described here is actually made up of several - * separate areas, as far as the GuC is concerned. The first page (kept - * kmap'd) includes the "process descriptor" which holds sequence data for - * the doorbell, and one cacheline which actually *is* the doorbell; a - * write to this will "ring the doorbell" (i.e. send an interrupt to the - * GuC). The subsequent pages of the client object constitute the work - * queue (a circular array of work items), again described in the process - * descriptor. Work queue pages are mapped momentarily as required. - */ -struct intel_guc_client { - struct i915_vma *vma; - void *vaddr; - struct intel_guc *guc; - - /* bitmap of (host) engine ids */ - u32 priority; - u32 stage_id; - - /* Protects GuC client's WQ access */ - spinlock_t wq_lock; -}; +struct intel_guc; +struct intel_engine_cs; void intel_guc_submission_init_early(struct intel_guc *guc); int intel_guc_submission_init(struct intel_guc *guc); @@ -56,5 +18,6 @@ void intel_guc_submission_disable(struct intel_guc *guc); void intel_guc_submission_fini(struct intel_guc *guc); int intel_guc_preempt_work_create(struct intel_guc *guc); void intel_guc_preempt_work_destroy(struct intel_guc *guc); +bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine); #endif diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 3e563384e84d..6cb149ba1905 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1792,23 +1792,12 @@ static void i915_guc_log_info(struct seq_file *m, static int i915_guc_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - const struct intel_guc *guc = &dev_priv->gt.uc.guc; - struct intel_guc_client *client = guc->execbuf_client; if (!USES_GUC(dev_priv)) return -ENODEV; i915_guc_log_info(m, dev_priv); - if (!USES_GUC_SUBMISSION(dev_priv)) - return 0; - - GEM_BUG_ON(!guc->execbuf_client); - - seq_printf(m, "\nGuC execbuf client @ %p:\n", client); - seq_printf(m, "\tPriority %d, GuC stage index: %u\n", - client->priority, - client->stage_id); /* Add more as required ... */ return 0; -- cgit v1.2.3 From 0380c6846a4be705b2d5c964b01ba1e5aaa3f5df Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 4 Dec 2019 11:00:11 +0100 Subject: drm/atomic: Update docs around locking and commit sequencing Both locking and especially sequencing of nonblocking commits have evolved a lot. The details are all there, but I noticed that the big picture and connections have fallen behind a bit. Apply polish. Motivated by some review discussions with Thierry. v2: Review from Thierry Reviewed-by: Thierry Reding Cc: Thierry Reding Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20191204100011.859468-1-daniel.vetter@ffwll.ch --- Documentation/gpu/drm-kms.rst | 11 ++++++++- drivers/gpu/drm/drm_atomic.c | 10 ++++---- drivers/gpu/drm/drm_atomic_helper.c | 46 +++++++++++++++++++++++-------------- include/drm/drm_atomic.h | 13 +++++++++-- 4 files changed, 56 insertions(+), 24 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index c68588ce4090..b9330343d1bc 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -260,7 +260,8 @@ Taken all together there's two consequences for the atomic design: drm_connector_state ` for connectors. These are the only objects with userspace-visible and settable state. For internal state drivers can subclass these structures through embeddeding, or add entirely new state - structures for their globally shared hardware functions. + structures for their globally shared hardware functions, see :c:type:`struct + drm_private_state`. - An atomic update is assembled and validated as an entirely free-standing pile of structures within the :c:type:`drm_atomic_state ` @@ -269,6 +270,14 @@ Taken all together there's two consequences for the atomic design: to the driver and modeset objects. This way rolling back an update boils down to releasing memory and unreferencing objects like framebuffers. +Locking of atomic state structures is internally using :c:type:`struct +drm_modeset_lock `. As a general rule the locking shouldn't be +exposed to drivers, instead the right locks should be automatically acquired by +any function that duplicates or peeks into a state, like e.g. +:c:func:`drm_atomic_get_crtc_state()`. Locking only protects the software data +structure, ordering of committing state changes to hardware is sequenced using +:c:type:`struct drm_crtc_commit `. + Read on in this chapter, and also in :ref:`drm_atomic_helper` for more detailed coverage of specific topics. diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 14aeaf736321..ab4508f25986 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -688,10 +688,12 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, * associated state struct &drm_private_state. * * Similar to userspace-exposed objects, private state structures can be - * acquired by calling drm_atomic_get_private_obj_state(). Since this function - * does not take care of locking, drivers should wrap it for each type of - * private state object they have with the required call to drm_modeset_lock() - * for the corresponding &drm_modeset_lock. + * acquired by calling drm_atomic_get_private_obj_state(). This also takes care + * of locking, hence drivers should not have a need to call drm_modeset_lock() + * directly. Sequence of the actual hardware state commit is not handled, + * drivers might need to keep track of struct drm_crtc_commit within subclassed + * structure of &drm_private_state as necessary, e.g. similar to + * &drm_plane_state.commit. See also &drm_atomic_state.fake_commit. * * All private state structures contained in a &drm_atomic_state update can be * iterated using for_each_oldnew_private_obj_in_state(), diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 29c3115bf9e2..57a84555a6bd 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1832,17 +1832,21 @@ EXPORT_SYMBOL(drm_atomic_helper_commit); /** * DOC: implementing nonblocking commit * - * Nonblocking atomic commits have to be implemented in the following sequence: + * Nonblocking atomic commits should use struct &drm_crtc_commit to sequence + * different operations against each another. Locks, especially struct + * &drm_modeset_lock, should not be held in worker threads or any other + * asynchronous context used to commit the hardware state. * - * 1. Run drm_atomic_helper_prepare_planes() first. This is the only function - * which commit needs to call which can fail, so we want to run it first and + * drm_atomic_helper_commit() implements the recommended sequence for + * nonblocking commits, using drm_atomic_helper_setup_commit() internally: + * + * 1. Run drm_atomic_helper_prepare_planes(). Since this can fail and we + * need to propagate out of memory/VRAM errors to userspace, it must be called * synchronously. * * 2. Synchronize with any outstanding nonblocking commit worker threads which - * might be affected the new state update. This can be done by either cancelling - * or flushing the work items, depending upon whether the driver can deal with - * cancelled updates. Note that it is important to ensure that the framebuffer - * cleanup is still done when cancelling. + * might be affected by the new state update. This is handled by + * drm_atomic_helper_setup_commit(). * * Asynchronous workers need to have sufficient parallelism to be able to run * different atomic commits on different CRTCs in parallel. The simplest way to @@ -1853,21 +1857,29 @@ EXPORT_SYMBOL(drm_atomic_helper_commit); * must be done as one global operation, and enabling or disabling a CRTC can * take a long time. But even that is not required. * + * IMPORTANT: A &drm_atomic_state update for multiple CRTCs is sequenced + * against all CRTCs therein. Therefore for atomic state updates which only flip + * planes the driver must not get the struct &drm_crtc_state of unrelated CRTCs + * in its atomic check code: This would prevent committing of atomic updates to + * multiple CRTCs in parallel. In general, adding additional state structures + * should be avoided as much as possible, because this reduces parallelism in + * (nonblocking) commits, both due to locking and due to commit sequencing + * requirements. + * * 3. The software state is updated synchronously with * drm_atomic_helper_swap_state(). Doing this under the protection of all modeset - * locks means concurrent callers never see inconsistent state. And doing this - * while it's guaranteed that no relevant nonblocking worker runs means that - * nonblocking workers do not need grab any locks. Actually they must not grab - * locks, for otherwise the work flushing will deadlock. + * locks means concurrent callers never see inconsistent state. Note that commit + * workers do not hold any locks; their access is only coordinated through + * ordering. If workers would access state only through the pointers in the + * free-standing state objects (currently not the case for any driver) then even + * multiple pending commits could be in-flight at the same time. * * 4. Schedule a work item to do all subsequent steps, using the split-out * commit helpers: a) pre-plane commit b) plane commit c) post-plane commit and * then cleaning up the framebuffers after the old framebuffer is no longer - * being displayed. - * - * The above scheme is implemented in the atomic helper libraries in - * drm_atomic_helper_commit() using a bunch of helper functions. See - * drm_atomic_helper_setup_commit() for a starting point. + * being displayed. The scheduled work should synchronize against other workers + * using the &drm_crtc_commit infrastructure as needed. See + * drm_atomic_helper_setup_commit() for more details. */ static int stall_checks(struct drm_crtc *crtc, bool nonblock) @@ -2096,7 +2108,7 @@ EXPORT_SYMBOL(drm_atomic_helper_setup_commit); * * This function waits for all preceeding commits that touch the same CRTC as * @old_state to both be committed to the hardware (as signalled by - * drm_atomic_helper_commit_hw_done) and executed by the hardware (as signalled + * drm_atomic_helper_commit_hw_done()) and executed by the hardware (as signalled * by calling drm_crtc_send_vblank_event() on the &drm_crtc_state.event). * * This is part of the atomic helper support for nonblocking commits, see diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index b6c73fd9f55a..5923819dcd68 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -60,8 +60,8 @@ * wait for flip_done <---- * clean up atomic state * - * The important bit to know is that cleanup_done is the terminal event, but the - * ordering between flip_done and hw_done is entirely up to the specific driver + * The important bit to know is that &cleanup_done is the terminal event, but the + * ordering between &flip_done and &hw_done is entirely up to the specific driver * and modeset state change. * * For an implementation of how to use this look at @@ -92,6 +92,9 @@ struct drm_crtc_commit { * commit is sent to userspace, or when an out-fence is singalled. Note * that for most hardware, in most cases this happens after @hw_done is * signalled. + * + * Completion of this stage is signalled implicitly by calling + * drm_crtc_send_vblank_event() on &drm_crtc_state.event. */ struct completion flip_done; @@ -107,6 +110,9 @@ struct drm_crtc_commit { * Note that this does not need to include separately reference-counted * resources like backing storage buffer pinning, or runtime pm * management. + * + * Drivers should call drm_atomic_helper_commit_hw_done() to signal + * completion of this stage. */ struct completion hw_done; @@ -118,6 +124,9 @@ struct drm_crtc_commit { * a vblank wait completed it might be a bit later. This completion is * useful to throttle updates and avoid hardware updates getting ahead * of the buffer cleanup too much. + * + * Drivers should call drm_atomic_helper_commit_cleanup_done() to signal + * completion of this stage. */ struct completion cleanup_done; -- cgit v1.2.3 From 6acc942c5eecad34a7623e01317f3d03d1e05462 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 4 Dec 2019 11:19:33 +0100 Subject: drm/doc: Drop :c:func: markup Kernel sphinx has learned how to do that in commit d74b0d31dddeac2b44c715588d53d9a1e5b1158e Author: Jonathan Corbet Date: Thu Apr 25 07:55:07 2019 -0600 Docs: An initial automarkup extension for sphinx Unfortunately it hasn't learned that yet for structures, so we're stuck with the :c:type: noise for now still. Reviewed-by: Thierry Reding Cc: Jonathan Corbet Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20191204101933.861169-1-daniel.vetter@ffwll.ch --- Documentation/gpu/drm-internals.rst | 4 +-- Documentation/gpu/drm-kms.rst | 7 ++-- Documentation/gpu/drm-mm.rst | 68 +++++++++++++++++-------------------- 3 files changed, 36 insertions(+), 43 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpu/drm-internals.rst b/Documentation/gpu/drm-internals.rst index 966bd2d9f0cc..a73320576ca9 100644 --- a/Documentation/gpu/drm-internals.rst +++ b/Documentation/gpu/drm-internals.rst @@ -24,9 +24,9 @@ Driver Initialization At the core of every DRM driver is a :c:type:`struct drm_driver ` structure. Drivers typically statically initialize a drm_driver structure, and then pass it to -:c:func:`drm_dev_alloc()` to allocate a device instance. After the +drm_dev_alloc() to allocate a device instance. After the device instance is fully initialized it can be registered (which makes -it accessible from userspace) using :c:func:`drm_dev_register()`. +it accessible from userspace) using drm_dev_register(). The :c:type:`struct drm_driver ` structure contains static information that describes the driver and features it diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index b9330343d1bc..906771e03103 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -3,7 +3,7 @@ Kernel Mode Setting (KMS) ========================= Drivers must initialize the mode setting core by calling -:c:func:`drm_mode_config_init()` on the DRM device. The function +drm_mode_config_init() on the DRM device. The function initializes the :c:type:`struct drm_device ` mode_config field and never fails. Once done, mode configuration must be setup by initializing the following fields. @@ -181,8 +181,7 @@ Setting`_). The somewhat surprising part here is that properties are not directly instantiated on each object, but free-standing mode objects themselves, represented by :c:type:`struct drm_property `, which only specify the type and value range of a property. Any given property can be attached -multiple times to different objects using :c:func:`drm_object_attach_property() -`. +multiple times to different objects using drm_object_attach_property(). .. kernel-doc:: include/drm/drm_mode_object.h :internal: @@ -274,7 +273,7 @@ Locking of atomic state structures is internally using :c:type:`struct drm_modeset_lock `. As a general rule the locking shouldn't be exposed to drivers, instead the right locks should be automatically acquired by any function that duplicates or peeks into a state, like e.g. -:c:func:`drm_atomic_get_crtc_state()`. Locking only protects the software data +drm_atomic_get_crtc_state(). Locking only protects the software data structure, ordering of committing state changes to hardware is sequenced using :c:type:`struct drm_crtc_commit `. diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index 59619296c84b..c77b32601260 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -149,19 +149,19 @@ struct :c:type:`struct drm_gem_object `. To create a GEM object, a driver allocates memory for an instance of its specific GEM object type and initializes the embedded struct :c:type:`struct drm_gem_object ` with a call -to :c:func:`drm_gem_object_init()`. The function takes a pointer +to drm_gem_object_init(). The function takes a pointer to the DRM device, a pointer to the GEM object and the buffer object size in bytes. GEM uses shmem to allocate anonymous pageable memory. -:c:func:`drm_gem_object_init()` will create an shmfs file of the +drm_gem_object_init() will create an shmfs file of the requested size and store it into the struct :c:type:`struct drm_gem_object ` filp field. The memory is used as either main storage for the object when the graphics hardware uses system memory directly or as a backing store otherwise. Drivers are responsible for the actual physical pages allocation by -calling :c:func:`shmem_read_mapping_page_gfp()` for each page. +calling shmem_read_mapping_page_gfp() for each page. Note that they can decide to allocate pages when initializing the GEM object, or to delay allocation until the memory is needed (for instance when a page fault occurs as a result of a userspace memory access or @@ -170,20 +170,18 @@ when the driver needs to start a DMA transfer involving the memory). Anonymous pageable memory allocation is not always desired, for instance when the hardware requires physically contiguous system memory as is often the case in embedded devices. Drivers can create GEM objects with -no shmfs backing (called private GEM objects) by initializing them with -a call to :c:func:`drm_gem_private_object_init()` instead of -:c:func:`drm_gem_object_init()`. Storage for private GEM objects -must be managed by drivers. +no shmfs backing (called private GEM objects) by initializing them with a call +to drm_gem_private_object_init() instead of drm_gem_object_init(). Storage for +private GEM objects must be managed by drivers. GEM Objects Lifetime -------------------- All GEM objects are reference-counted by the GEM core. References can be -acquired and release by :c:func:`calling drm_gem_object_get()` and -:c:func:`drm_gem_object_put()` respectively. The caller must hold the -:c:type:`struct drm_device ` struct_mutex lock when calling -:c:func:`drm_gem_object_get()`. As a convenience, GEM provides -:c:func:`drm_gem_object_put_unlocked()` functions that can be called without +acquired and release by calling drm_gem_object_get() and drm_gem_object_put() +respectively. The caller must hold the :c:type:`struct drm_device ` +struct_mutex lock when calling drm_gem_object_get(). As a convenience, GEM +provides drm_gem_object_put_unlocked() functions that can be called without holding the lock. When the last reference to a GEM object is released the GEM core calls @@ -194,7 +192,7 @@ free the GEM object and all associated resources. void (\*gem_free_object) (struct drm_gem_object \*obj); Drivers are responsible for freeing all GEM object resources. This includes the resources created by the GEM core, which need to be released with -:c:func:`drm_gem_object_release()`. +drm_gem_object_release(). GEM Objects Naming ------------------ @@ -210,13 +208,11 @@ to the GEM object in other standard or driver-specific ioctls. Closing a DRM file handle frees all its GEM handles and dereferences the associated GEM objects. -To create a handle for a GEM object drivers call -:c:func:`drm_gem_handle_create()`. The function takes a pointer -to the DRM file and the GEM object and returns a locally unique handle. -When the handle is no longer needed drivers delete it with a call to -:c:func:`drm_gem_handle_delete()`. Finally the GEM object -associated with a handle can be retrieved by a call to -:c:func:`drm_gem_object_lookup()`. +To create a handle for a GEM object drivers call drm_gem_handle_create(). The +function takes a pointer to the DRM file and the GEM object and returns a +locally unique handle. When the handle is no longer needed drivers delete it +with a call to drm_gem_handle_delete(). Finally the GEM object associated with a +handle can be retrieved by a call to drm_gem_object_lookup(). Handles don't take ownership of GEM objects, they only take a reference to the object that will be dropped when the handle is destroyed. To @@ -258,7 +254,7 @@ The mmap system call can't be used directly to map GEM objects, as they don't have their own file handle. Two alternative methods currently co-exist to map GEM objects to userspace. The first method uses a driver-specific ioctl to perform the mapping operation, calling -:c:func:`do_mmap()` under the hood. This is often considered +do_mmap() under the hood. This is often considered dubious, seems to be discouraged for new GEM-enabled drivers, and will thus not be described here. @@ -267,23 +263,22 @@ The second method uses the mmap system call on the DRM file handle. void offset); DRM identifies the GEM object to be mapped by a fake offset passed through the mmap offset argument. Prior to being mapped, a GEM object must thus be associated with a fake offset. To do so, drivers -must call :c:func:`drm_gem_create_mmap_offset()` on the object. +must call drm_gem_create_mmap_offset() on the object. Once allocated, the fake offset value must be passed to the application in a driver-specific way and can then be used as the mmap offset argument. -The GEM core provides a helper method :c:func:`drm_gem_mmap()` to +The GEM core provides a helper method drm_gem_mmap() to handle object mapping. The method can be set directly as the mmap file operation handler. It will look up the GEM object based on the offset value and set the VMA operations to the :c:type:`struct drm_driver -` gem_vm_ops field. Note that -:c:func:`drm_gem_mmap()` doesn't map memory to userspace, but -relies on the driver-provided fault handler to map pages individually. +` gem_vm_ops field. Note that drm_gem_mmap() doesn't map memory to +userspace, but relies on the driver-provided fault handler to map pages +individually. -To use :c:func:`drm_gem_mmap()`, drivers must fill the struct -:c:type:`struct drm_driver ` gem_vm_ops field -with a pointer to VM operations. +To use drm_gem_mmap(), drivers must fill the struct :c:type:`struct drm_driver +` gem_vm_ops field with a pointer to VM operations. The VM operations is a :c:type:`struct vm_operations_struct ` made up of several fields, the more interesting ones being: @@ -298,9 +293,8 @@ made up of several fields, the more interesting ones being: The open and close operations must update the GEM object reference -count. Drivers can use the :c:func:`drm_gem_vm_open()` and -:c:func:`drm_gem_vm_close()` helper functions directly as open -and close handlers. +count. Drivers can use the drm_gem_vm_open() and drm_gem_vm_close() helper +functions directly as open and close handlers. The fault operation handler is responsible for mapping individual pages to userspace when a page fault occurs. Depending on the memory @@ -312,12 +306,12 @@ Drivers that want to map the GEM object upfront instead of handling page faults can implement their own mmap file operation handler. For platforms without MMU the GEM core provides a helper method -:c:func:`drm_gem_cma_get_unmapped_area`. The mmap() routines will call -this to get a proposed address for the mapping. +drm_gem_cma_get_unmapped_area(). The mmap() routines will call this to get a +proposed address for the mapping. -To use :c:func:`drm_gem_cma_get_unmapped_area`, drivers must fill the -struct :c:type:`struct file_operations ` get_unmapped_area -field with a pointer on :c:func:`drm_gem_cma_get_unmapped_area`. +To use drm_gem_cma_get_unmapped_area(), drivers must fill the struct +:c:type:`struct file_operations ` get_unmapped_area field with +a pointer on drm_gem_cma_get_unmapped_area(). More detailed information about get_unmapped_area can be found in Documentation/nommu-mmap.txt -- cgit v1.2.3 From 9482ae6ea7879f29221eb9cd10807d087517b38b Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 10 Dec 2019 15:41:37 +0100 Subject: dt-bindings: display/ingenic: Add compatible string for JZ4770 Add a compatible string for the LCD controller found in the JZ4770 SoC. v2: No change Signed-off-by: Paul Cercueil Acked-by: Rob Herring Link: https://patchwork.freedesktop.org/patch/msgid/20191210144142.33143-1-paul@crapouillou.net # *** extracted tags *** Acked-by: Sam Ravnborg --- Documentation/devicetree/bindings/display/ingenic,lcd.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/ingenic,lcd.txt b/Documentation/devicetree/bindings/display/ingenic,lcd.txt index 7b536c8c6dde..01e3261defb6 100644 --- a/Documentation/devicetree/bindings/display/ingenic,lcd.txt +++ b/Documentation/devicetree/bindings/display/ingenic,lcd.txt @@ -4,6 +4,7 @@ Required properties: - compatible: one of: * ingenic,jz4740-lcd * ingenic,jz4725b-lcd + * ingenic,jz4770-lcd - reg: LCD registers location and length - clocks: LCD pixclock and device clock specifiers. The device clock is only required on the JZ4740. -- cgit v1.2.3 From 2156873f08c7893811f34177aa923ab1ea486591 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Mon, 9 Dec 2019 16:42:14 +0200 Subject: drm/tilcdc: Remove obsolete bundled tilcdc tfp410 driver Remove obsolete bundled tfp410 driver with its "ti,tilcdc,tfp410" devicetree binding. No platform has ever used this driver in the mainline kernel and if anybody connects tfp410 to tilcdc he or she should use the generic drm tfp410 bridge driver. Signed-off-by: Jyri Sarha Reviewed-by: Laurent Pinchart Link: https://patchwork.freedesktop.org/patch/msgid/6e2db6c328467cc51e8d633ecb0ffa7c5736f2e8.1575901747.git.jsarha@ti.com --- .../devicetree/bindings/display/tilcdc/tfp410.txt | 21 -- drivers/gpu/drm/tilcdc/Makefile | 1 - drivers/gpu/drm/tilcdc/tilcdc_drv.c | 3 - drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 381 --------------------- drivers/gpu/drm/tilcdc/tilcdc_tfp410.h | 15 - 5 files changed, 421 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/tilcdc/tfp410.txt delete mode 100644 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c delete mode 100644 drivers/gpu/drm/tilcdc/tilcdc_tfp410.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt b/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt deleted file mode 100644 index a58ae7756fc6..000000000000 --- a/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device-Tree bindings for tilcdc DRM TFP410 output driver - -Required properties: - - compatible: value should be "ti,tilcdc,tfp410". - - i2c: the phandle for the i2c device to use for DDC - -Recommended properties: - - pinctrl-names, pinctrl-0: the pincontrol settings to configure - muxing properly for pins that connect to TFP410 device - - powerdn-gpio: the powerdown GPIO, pulled low to power down the - TFP410 device (for DPMS_OFF) - -Example: - - dvicape { - compatible = "ti,tilcdc,tfp410"; - i2c = <&i2c2>; - pinctrl-names = "default"; - pinctrl-0 = <&bone_dvi_cape_dvi_00A1_pins>; - powerdn-gpio = <&gpio2 31 0>; - }; diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile index 87f9480e43b0..662bf3a348c9 100644 --- a/drivers/gpu/drm/tilcdc/Makefile +++ b/drivers/gpu/drm/tilcdc/Makefile @@ -6,7 +6,6 @@ endif tilcdc-y := \ tilcdc_plane.o \ tilcdc_crtc.o \ - tilcdc_tfp410.o \ tilcdc_panel.o \ tilcdc_external.o \ tilcdc_drv.o diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index a160880bea0a..c18a28df6e2c 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -30,7 +30,6 @@ #include "tilcdc_external.h" #include "tilcdc_panel.h" #include "tilcdc_regs.h" -#include "tilcdc_tfp410.h" static LIST_HEAD(module_list); @@ -643,7 +642,6 @@ static struct platform_driver tilcdc_platform_driver = { static int __init tilcdc_drm_init(void) { DBG("init"); - tilcdc_tfp410_init(); tilcdc_panel_init(); return platform_driver_register(&tilcdc_platform_driver); } @@ -653,7 +651,6 @@ static void __exit tilcdc_drm_fini(void) DBG("fini"); platform_driver_unregister(&tilcdc_platform_driver); tilcdc_panel_fini(); - tilcdc_tfp410_fini(); } module_init(tilcdc_drm_init); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c deleted file mode 100644 index 562e98ab43cd..000000000000 --- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c +++ /dev/null @@ -1,381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments - * Author: Rob Clark - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "tilcdc_drv.h" -#include "tilcdc_tfp410.h" - -struct tfp410_module { - struct tilcdc_module base; - struct i2c_adapter *i2c; - int gpio; -}; -#define to_tfp410_module(x) container_of(x, struct tfp410_module, base) - - -static const struct tilcdc_panel_info dvi_info = { - .ac_bias = 255, - .ac_bias_intrpt = 0, - .dma_burst_sz = 16, - .bpp = 16, - .fdd = 0x80, - .tft_alt_mode = 0, - .sync_edge = 0, - .sync_ctrl = 1, - .raster_order = 0, -}; - -/* - * Encoder: - */ - -struct tfp410_encoder { - struct drm_encoder base; - struct tfp410_module *mod; - int dpms; -}; -#define to_tfp410_encoder(x) container_of(x, struct tfp410_encoder, base) - -static void tfp410_encoder_dpms(struct drm_encoder *encoder, int mode) -{ - struct tfp410_encoder *tfp410_encoder = to_tfp410_encoder(encoder); - - if (tfp410_encoder->dpms == mode) - return; - - if (mode == DRM_MODE_DPMS_ON) { - DBG("Power on"); - gpio_direction_output(tfp410_encoder->mod->gpio, 1); - } else { - DBG("Power off"); - gpio_direction_output(tfp410_encoder->mod->gpio, 0); - } - - tfp410_encoder->dpms = mode; -} - -static void tfp410_encoder_prepare(struct drm_encoder *encoder) -{ - tfp410_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); -} - -static void tfp410_encoder_commit(struct drm_encoder *encoder) -{ - tfp410_encoder_dpms(encoder, DRM_MODE_DPMS_ON); -} - -static void tfp410_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - /* nothing needed */ -} - -static const struct drm_encoder_funcs tfp410_encoder_funcs = { - .destroy = drm_encoder_cleanup, -}; - -static const struct drm_encoder_helper_funcs tfp410_encoder_helper_funcs = { - .dpms = tfp410_encoder_dpms, - .prepare = tfp410_encoder_prepare, - .commit = tfp410_encoder_commit, - .mode_set = tfp410_encoder_mode_set, -}; - -static struct drm_encoder *tfp410_encoder_create(struct drm_device *dev, - struct tfp410_module *mod) -{ - struct tfp410_encoder *tfp410_encoder; - struct drm_encoder *encoder; - int ret; - - tfp410_encoder = devm_kzalloc(dev->dev, sizeof(*tfp410_encoder), - GFP_KERNEL); - if (!tfp410_encoder) - return NULL; - - tfp410_encoder->dpms = DRM_MODE_DPMS_OFF; - tfp410_encoder->mod = mod; - - encoder = &tfp410_encoder->base; - encoder->possible_crtcs = 1; - - ret = drm_encoder_init(dev, encoder, &tfp410_encoder_funcs, - DRM_MODE_ENCODER_TMDS, NULL); - if (ret < 0) - goto fail; - - drm_encoder_helper_add(encoder, &tfp410_encoder_helper_funcs); - - return encoder; - -fail: - drm_encoder_cleanup(encoder); - return NULL; -} - -/* - * Connector: - */ - -struct tfp410_connector { - struct drm_connector base; - - struct drm_encoder *encoder; /* our connected encoder */ - struct tfp410_module *mod; -}; -#define to_tfp410_connector(x) container_of(x, struct tfp410_connector, base) - - -static void tfp410_connector_destroy(struct drm_connector *connector) -{ - drm_connector_unregister(connector); - drm_connector_cleanup(connector); -} - -static enum drm_connector_status tfp410_connector_detect( - struct drm_connector *connector, - bool force) -{ - struct tfp410_connector *tfp410_connector = to_tfp410_connector(connector); - - if (drm_probe_ddc(tfp410_connector->mod->i2c)) - return connector_status_connected; - - return connector_status_unknown; -} - -static int tfp410_connector_get_modes(struct drm_connector *connector) -{ - struct tfp410_connector *tfp410_connector = to_tfp410_connector(connector); - struct edid *edid; - int ret = 0; - - edid = drm_get_edid(connector, tfp410_connector->mod->i2c); - - drm_connector_update_edid_property(connector, edid); - - if (edid) { - ret = drm_add_edid_modes(connector, edid); - kfree(edid); - } - - return ret; -} - -static struct drm_encoder *tfp410_connector_best_encoder( - struct drm_connector *connector) -{ - struct tfp410_connector *tfp410_connector = to_tfp410_connector(connector); - return tfp410_connector->encoder; -} - -static const struct drm_connector_funcs tfp410_connector_funcs = { - .destroy = tfp410_connector_destroy, - .detect = tfp410_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static const struct drm_connector_helper_funcs tfp410_connector_helper_funcs = { - .get_modes = tfp410_connector_get_modes, - .best_encoder = tfp410_connector_best_encoder, -}; - -static struct drm_connector *tfp410_connector_create(struct drm_device *dev, - struct tfp410_module *mod, struct drm_encoder *encoder) -{ - struct tfp410_connector *tfp410_connector; - struct drm_connector *connector; - int ret; - - tfp410_connector = devm_kzalloc(dev->dev, sizeof(*tfp410_connector), - GFP_KERNEL); - if (!tfp410_connector) - return NULL; - - tfp410_connector->encoder = encoder; - tfp410_connector->mod = mod; - - connector = &tfp410_connector->base; - - drm_connector_init_with_ddc(dev, connector, - &tfp410_connector_funcs, - DRM_MODE_CONNECTOR_DVID, - mod->i2c); - drm_connector_helper_add(connector, &tfp410_connector_helper_funcs); - - connector->polled = DRM_CONNECTOR_POLL_CONNECT | - DRM_CONNECTOR_POLL_DISCONNECT; - - connector->interlace_allowed = 0; - connector->doublescan_allowed = 0; - - ret = drm_connector_attach_encoder(connector, encoder); - if (ret) - goto fail; - - return connector; - -fail: - tfp410_connector_destroy(connector); - return NULL; -} - -/* - * Module: - */ - -static int tfp410_modeset_init(struct tilcdc_module *mod, struct drm_device *dev) -{ - struct tfp410_module *tfp410_mod = to_tfp410_module(mod); - struct tilcdc_drm_private *priv = dev->dev_private; - struct drm_encoder *encoder; - struct drm_connector *connector; - - encoder = tfp410_encoder_create(dev, tfp410_mod); - if (!encoder) - return -ENOMEM; - - connector = tfp410_connector_create(dev, tfp410_mod, encoder); - if (!connector) - return -ENOMEM; - - priv->encoders[priv->num_encoders++] = encoder; - priv->connectors[priv->num_connectors++] = connector; - - tilcdc_crtc_set_panel_info(priv->crtc, &dvi_info); - return 0; -} - -static const struct tilcdc_module_ops tfp410_module_ops = { - .modeset_init = tfp410_modeset_init, -}; - -/* - * Device: - */ - -static int tfp410_probe(struct platform_device *pdev) -{ - struct device_node *node = pdev->dev.of_node; - struct device_node *i2c_node; - struct tfp410_module *tfp410_mod; - struct tilcdc_module *mod; - struct pinctrl *pinctrl; - uint32_t i2c_phandle; - int ret = -EINVAL; - - /* bail out early if no DT data: */ - if (!node) { - dev_err(&pdev->dev, "device-tree data is missing\n"); - return -ENXIO; - } - - tfp410_mod = devm_kzalloc(&pdev->dev, sizeof(*tfp410_mod), GFP_KERNEL); - if (!tfp410_mod) - return -ENOMEM; - - mod = &tfp410_mod->base; - pdev->dev.platform_data = mod; - - tilcdc_module_init(mod, "tfp410", &tfp410_module_ops); - - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(pinctrl)) - dev_warn(&pdev->dev, "pins are not configured\n"); - - if (of_property_read_u32(node, "i2c", &i2c_phandle)) { - dev_err(&pdev->dev, "could not get i2c bus phandle\n"); - goto fail; - } - - i2c_node = of_find_node_by_phandle(i2c_phandle); - if (!i2c_node) { - dev_err(&pdev->dev, "could not get i2c bus node\n"); - goto fail; - } - - tfp410_mod->i2c = of_find_i2c_adapter_by_node(i2c_node); - if (!tfp410_mod->i2c) { - dev_err(&pdev->dev, "could not get i2c\n"); - of_node_put(i2c_node); - goto fail; - } - - of_node_put(i2c_node); - - tfp410_mod->gpio = of_get_named_gpio_flags(node, "powerdn-gpio", - 0, NULL); - if (tfp410_mod->gpio < 0) { - dev_warn(&pdev->dev, "No power down GPIO\n"); - } else { - ret = gpio_request(tfp410_mod->gpio, "DVI_PDn"); - if (ret) { - dev_err(&pdev->dev, "could not get DVI_PDn gpio\n"); - goto fail_adapter; - } - } - - return 0; - -fail_adapter: - i2c_put_adapter(tfp410_mod->i2c); - -fail: - tilcdc_module_cleanup(mod); - return ret; -} - -static int tfp410_remove(struct platform_device *pdev) -{ - struct tilcdc_module *mod = dev_get_platdata(&pdev->dev); - struct tfp410_module *tfp410_mod = to_tfp410_module(mod); - - i2c_put_adapter(tfp410_mod->i2c); - gpio_free(tfp410_mod->gpio); - - tilcdc_module_cleanup(mod); - - return 0; -} - -static const struct of_device_id tfp410_of_match[] = { - { .compatible = "ti,tilcdc,tfp410", }, - { }, -}; - -struct platform_driver tfp410_driver = { - .probe = tfp410_probe, - .remove = tfp410_remove, - .driver = { - .owner = THIS_MODULE, - .name = "tfp410", - .of_match_table = tfp410_of_match, - }, -}; - -int __init tilcdc_tfp410_init(void) -{ - return platform_driver_register(&tfp410_driver); -} - -void __exit tilcdc_tfp410_fini(void) -{ - platform_driver_unregister(&tfp410_driver); -} diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.h b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.h deleted file mode 100644 index f9aaf6911ffc..000000000000 --- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2012 Texas Instruments - * Author: Rob Clark - */ - -#ifndef __TILCDC_TFP410_H__ -#define __TILCDC_TFP410_H__ - -/* sub-module for tfp410 dvi adaptor */ - -int tilcdc_tfp410_init(void); -void tilcdc_tfp410_fini(void); - -#endif /* __TILCDC_TFP410_H__ */ -- cgit v1.2.3 From 0606f9b67e8c8727c1369096b3b142dd74dc0a39 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 9 Dec 2019 15:31:27 +0100 Subject: dt-bindings: display: rockchip-dsi: document external phys Some dw-mipi-dsi instances in Rockchip SoCs use external dphys. In these cases the needs clock will also be generated externally so these don't need the ref-clock as well. changes in v5: - rebased on top of 5.5-rc1 - merged with dsi timing change to prevent ordering conflicts Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring Link: https://patchwork.freedesktop.org/patch/msgid/20191209143130.4553-4-heiko@sntech.de --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index ce4c1fc9116c..1ba9237d0ac0 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -9,8 +9,9 @@ Required properties: - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference - clock(ref) and APB clock(pclk). For RK3399, a phy config clock - (phy_cfg) and a grf clock(grf) are required. As described in [1]. + clock(ref) when using an internal dphy and APB clock(pclk). + For RK3399, a phy config clock (phy_cfg) and a grf clock(grf) + are required. As described in [1]. - rockchip,grf: this soc should set GRF regs to mux vopl/vopb. - ports: contain a port node with endpoint definitions as defined in [2]. For vopb,set the reg = <0> and set the reg = <1> for vopl. @@ -18,6 +19,8 @@ Required properties: - video port 1 for either a panel or subsequent encoder Optional properties: +- phys: from general PHY binding: the phandle for the PHY device. +- phy-names: Should be "dphy" if phys references an external phy. - power-domains: a phandle to mipi dsi power domain node. - resets: list of phandle + reset specifier pairs, as described in [3]. - reset-names: string reset name, must be "apb". -- cgit v1.2.3 From 95da672f386c937cc22f892fadb019de3b2c2f0d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 9 Dec 2019 15:31:29 +0100 Subject: dt-bindings: display: rockchip-dsi: add px30 compatible The px30 SoC also uses a dw-mipi-dsi controller, so add the compatible value for it. changes in v5: - rebased on top of 5.5-rc1 - merged with dsi timing change to prevent ordering conflicts Signed-off-by: Heiko Stuebner Acked-by: Rob Herring Link: https://patchwork.freedesktop.org/patch/msgid/20191209143130.4553-6-heiko@sntech.de --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 1ba9237d0ac0..151be3bba06f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -4,8 +4,10 @@ Rockchip specific extensions to the Synopsys Designware MIPI DSI Required properties: - #address-cells: Should be <1>. - #size-cells: Should be <0>. -- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi". - "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi". +- compatible: one of + "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi" + "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi" + "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi" - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference -- cgit v1.2.3 From 4e7a4a6fbdc669c44e6079f9d5eb25673749455f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 18 Nov 2019 16:51:30 +0100 Subject: drm/modes: parse_cmdline: Add support for specifying panel_orientation (v2) Sometimes we want to override a connector's panel_orientation from the kernel commandline. Either for testing and for special cases, e.g. a kiosk like setup which uses a TV mounted in portrait mode. Users can already specify a "rotate" option through a video= kernel cmdline option. But that only supports 0/180 degrees (see drm_client_modeset TODO) and only works for in kernel modeset clients, not for userspace kms users. The "panel-orientation" connector property OTOH does support 90/270 degrees as it leaves dealing with the rotation up to userspace and this does work for userspace kms clients (at least those which support this property). Changes in v2: -Add missing ':' after @panel_orientation (reported by kbuild test robot) BugLink: https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/83 Acked-by: Maxime Ripard Signed-off-by: Hans de Goede Link: https://patchwork.freedesktop.org/patch/msgid/20191118155134.30468-9-hdegoede@redhat.com --- Documentation/fb/modedb.rst | 3 ++ drivers/gpu/drm/drm_modes.c | 32 ++++++++++++++++++++++ drivers/gpu/drm/selftests/drm_cmdline_selftests.h | 1 + .../gpu/drm/selftests/test-drm_cmdline_parser.c | 22 +++++++++++++++ include/drm/drm_connector.h | 8 ++++++ 5 files changed, 66 insertions(+) (limited to 'Documentation') diff --git a/Documentation/fb/modedb.rst b/Documentation/fb/modedb.rst index 9c4e3fd39e6d..624d08fd2856 100644 --- a/Documentation/fb/modedb.rst +++ b/Documentation/fb/modedb.rst @@ -65,6 +65,9 @@ Valid options are:: - reflect_y (boolean): Perform an axial symmetry on the Y axis - rotate (integer): Rotate the initial framebuffer by x degrees. Valid values are 0, 90, 180 and 270. + - panel_orientation, one of "normal", "upside_down", "left_side_up", or + "right_side_up". For KMS drivers only, this sets the "panel orientation" + property on the kms connector as hint for kms users. ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 2e82603f5d0a..119fed7ab815 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -1591,6 +1591,33 @@ static int drm_mode_parse_cmdline_int(const char *delim, unsigned int *int_ret) return 0; } +static int drm_mode_parse_panel_orientation(const char *delim, + struct drm_cmdline_mode *mode) +{ + const char *value; + + if (*delim != '=') + return -EINVAL; + + value = delim + 1; + delim = strchr(value, ','); + if (!delim) + delim = value + strlen(value); + + if (!strncmp(value, "normal", delim - value)) + mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; + else if (!strncmp(value, "upside_down", delim - value)) + mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; + else if (!strncmp(value, "left_side_up", delim - value)) + mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP; + else if (!strncmp(value, "right_side_up", delim - value)) + mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; + else + return -EINVAL; + + return 0; +} + static int drm_mode_parse_cmdline_options(const char *str, bool freestanding, const struct drm_connector *connector, @@ -1657,6 +1684,9 @@ static int drm_mode_parse_cmdline_options(const char *str, return -EINVAL; mode->tv_margins.bottom = margin; + } else if (!strncmp(option, "panel_orientation", delim - option)) { + if (drm_mode_parse_panel_orientation(delim, mode)) + return -EINVAL; } else { return -EINVAL; } @@ -1715,6 +1745,8 @@ bool drm_mode_parse_command_line_for_connector(const char *mode_option, char *bpp_end_ptr = NULL, *refresh_end_ptr = NULL; int i, len, ret; + mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; + #ifdef CONFIG_FB if (!mode_option) mode_option = fb_mode_option; diff --git a/drivers/gpu/drm/selftests/drm_cmdline_selftests.h b/drivers/gpu/drm/selftests/drm_cmdline_selftests.h index aee92ac2cc21..ceac7af9a172 100644 --- a/drivers/gpu/drm/selftests/drm_cmdline_selftests.h +++ b/drivers/gpu/drm/selftests/drm_cmdline_selftests.h @@ -64,3 +64,4 @@ cmdline_test(drm_cmdline_test_bpp_extra_and_option) cmdline_test(drm_cmdline_test_extra_and_option) cmdline_test(drm_cmdline_test_freestanding_options) cmdline_test(drm_cmdline_test_freestanding_force_e_and_options) +cmdline_test(drm_cmdline_test_panel_orientation) diff --git a/drivers/gpu/drm/selftests/test-drm_cmdline_parser.c b/drivers/gpu/drm/selftests/test-drm_cmdline_parser.c index 8248d4aa5aaa..520f3e66a384 100644 --- a/drivers/gpu/drm/selftests/test-drm_cmdline_parser.c +++ b/drivers/gpu/drm/selftests/test-drm_cmdline_parser.c @@ -1092,6 +1092,28 @@ static int drm_cmdline_test_freestanding_force_e_and_options(void *ignored) return 0; } +static int drm_cmdline_test_panel_orientation(void *ignored) +{ + struct drm_cmdline_mode mode = { }; + + FAIL_ON(!drm_mode_parse_command_line_for_connector("panel_orientation=upside_down", + &no_connector, + &mode)); + FAIL_ON(mode.specified); + FAIL_ON(mode.refresh_specified); + FAIL_ON(mode.bpp_specified); + + FAIL_ON(mode.panel_orientation != DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP); + + FAIL_ON(mode.rb); + FAIL_ON(mode.cvt); + FAIL_ON(mode.interlace); + FAIL_ON(mode.margins); + FAIL_ON(mode.force != DRM_FORCE_UNSPECIFIED); + + return 0; +} + #include "drm_selftest.c" static int __init test_drm_cmdline_init(void) diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 17b728d9c73d..221910948b37 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -1069,6 +1069,14 @@ struct drm_cmdline_mode { */ unsigned int rotation_reflection; + /** + * @panel_orientation: + * + * drm-connector "panel orientation" property override value, + * DRM_MODE_PANEL_ORIENTATION_UNKNOWN if not set. + */ + enum drm_panel_orientation panel_orientation; + /** * @tv_margins: TV margins to apply to the mode. */ -- cgit v1.2.3 From 7f7b9455b35290a1032c73222261bfd784cc3702 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Wed, 16 Oct 2019 10:55:41 +0200 Subject: dt-bindings: display: renesas,cmm: Add R-Car CMM documentation Add device tree bindings documentation for the Renesas R-Car Display Unit Color Management Module. CMM is the image enhancement module available on each R-Car DU video channel on R-Car Gen2 and Gen3 SoCs (V3H and V3M excluded). Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Jacopo Mondi Reviewed-by: Rob Herring Signed-off-by: Laurent Pinchart --- .../devicetree/bindings/display/renesas,cmm.yaml | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/renesas,cmm.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/renesas,cmm.yaml b/Documentation/devicetree/bindings/display/renesas,cmm.yaml new file mode 100644 index 000000000000..a57037b9e9ba --- /dev/null +++ b/Documentation/devicetree/bindings/display/renesas,cmm.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,cmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Color Management Module (CMM) + +maintainers: + - Laurent Pinchart + - Kieran Bingham + - Jacopo Mondi + +description: |+ + Renesas R-Car color management module connected to R-Car DU video channels. + It provides image enhancement functions such as 1-D look-up tables (LUT), + 3-D look-up tables (CLU), 1D-histogram generation (HGO), and color + space conversion (CSC). + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r8a7795-cmm + - renesas,r8a7796-cmm + - renesas,r8a77965-cmm + - renesas,r8a77990-cmm + - renesas,r8a77995-cmm + - const: renesas,rcar-gen3-cmm + - items: + - const: renesas,rcar-gen2-cmm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + + cmm0: cmm@fea40000 { + compatible = "renesas,r8a7796-cmm", + "renesas,rcar-gen3-cmm"; + reg = <0 0xfea40000 0 0x1000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 711>; + resets = <&cpg 711>; + }; -- cgit v1.2.3 From 6e2258b58f819e73aad229fd0af7d8274ef22669 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Wed, 16 Oct 2019 10:55:42 +0200 Subject: dt-bindings: display: renesas,du: Document cmms property Document the newly added 'renesas,cmms' property which accepts a list of phandle and channel index pairs that point to the CMM units available for each Display Unit output video channel. Reviewed-by: Rob Herring Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Jacopo Mondi Signed-off-by: Laurent Pinchart --- Documentation/devicetree/bindings/display/renesas,du.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt index 17cb2771364b..f6fdaa67c257 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ b/Documentation/devicetree/bindings/display/renesas,du.txt @@ -46,6 +46,10 @@ Required Properties: instance that serves the DU channel, and the channel index identifies the LIF instance in that VSP. + - renesas,cmms: A list of phandles to the CMM instances present in the SoC, + one for each available DU channel. The property shall not be specified for + SoCs that do not provide any CMM (such as V3M and V3H). + Required nodes: The connections to the DU output video ports are modeled using the OF graph @@ -93,6 +97,7 @@ Example: R8A7795 (R-Car H3) ES2.0 DU <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.2", "du.3"; vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; + renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; ports { #address-cells = <1>; -- cgit v1.2.3 From c81456d2452da72891688edb81d2f0749c2db568 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 Nov 2019 19:35:02 +0100 Subject: dt-bindings: display: renesas: du: Add vendor prefix to vsps property The Renesas-specific "vsps" property lacks a vendor prefix. Add a "renesas," prefix to comply with DT best practises. Move "renesas,vsps" below "renesas,cmms" to preserve alphabetical sort order. Fixes: 06711e6385a4ab4c ("drm: rcar-du: Document the vsps property in the DT bindings") Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart --- Documentation/devicetree/bindings/display/renesas,du.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt index f6fdaa67c257..eb4ae41fe41f 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ b/Documentation/devicetree/bindings/display/renesas,du.txt @@ -41,15 +41,15 @@ Required Properties: supplied they must be named "dclkin.x" with "x" being the input clock numerical index. - - vsps: A list of phandle and channel index tuples to the VSPs that handle - the memory interfaces for the DU channels. The phandle identifies the VSP - instance that serves the DU channel, and the channel index identifies the - LIF instance in that VSP. - - renesas,cmms: A list of phandles to the CMM instances present in the SoC, one for each available DU channel. The property shall not be specified for SoCs that do not provide any CMM (such as V3M and V3H). + - renesas,vsps: A list of phandle and channel index tuples to the VSPs that + handle the memory interfaces for the DU channels. The phandle identifies the + VSP instance that serves the DU channel, and the channel index identifies + the LIF instance in that VSP. + Required nodes: The connections to the DU output video ports are modeled using the OF graph @@ -96,8 +96,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.2", "du.3"; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; ports { #address-cells = <1>; -- cgit v1.2.3 From a7738c08cf269461da69f81db42279b57c68b2bb Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Nov 2019 15:51:20 +0000 Subject: dt-bindings: display: bridge: Convert lvds-transmitter binding to json-schema Convert the lvds-transmitter binding to DT schema format using json-schema. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/1573660292-10629-2-git-send-email-fabrizio.castro@bp.renesas.com --- .../bindings/display/bridge/lvds-transmitter.txt | 66 ---------------- .../bindings/display/bridge/lvds-transmitter.yaml | 91 ++++++++++++++++++++++ 2 files changed, 91 insertions(+), 66 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt create mode 100644 Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt deleted file mode 100644 index 60091db5dfa5..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt +++ /dev/null @@ -1,66 +0,0 @@ -Parallel to LVDS Encoder ------------------------- - -This binding supports the parallel to LVDS encoders that don't require any -configuration. - -LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple -incompatible data link layers have been used over time to transmit image data -to LVDS panels. This binding targets devices compatible with the following -specifications only. - -[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February -1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) -[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National -Semiconductor -[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video -Electronics Standards Association (VESA) - -Those devices have been marketed under the FPD-Link and FlatLink brand names -among others. - - -Required properties: - -- compatible: Must be "lvds-encoder" - - Any encoder compatible with this generic binding, but with additional - properties not listed here, must list a device specific compatible first - followed by this generic compatible. - -Required nodes: - -This device has two video ports. Their connections are modeled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for parallel input -- Video port 1 for LVDS output - - -Example -------- - -lvds-encoder { - compatible = "lvds-encoder"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint { - remote-endpoint = <&display_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint { - remote-endpoint = <&lvds_panel_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml new file mode 100644 index 000000000000..b5dd0da71394 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/lvds-transmitter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parallel to LVDS Encoder + +maintainers: + - Laurent Pinchart + +description: | + This binding supports the parallel to LVDS encoders that don't require any + configuration. + + LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple + incompatible data link layers have been used over time to transmit image data + to LVDS panels. This binding targets devices compatible with the following + specifications only. + + [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February + 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) + [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National + Semiconductor + [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video + Electronics Standards Association (VESA) + + Those devices have been marketed under the FPD-Link and FlatLink brand names + among others. + +properties: + compatible: + description: | + Any encoder compatible with this generic binding, but with additional + properties not listed here, must define its own binding and list a device + specific compatible first followed by the generic compatible. + enum: + - lvds-encoder + + ports: + type: object + description: | + This device has two video ports. Their connections are modeled using the + OF graph bindings specified in Documentation/devicetree/bindings/graph.txt + properties: + port@0: + type: object + description: | + Port 0 is for parallel input + + port@1: + type: object + description: | + Port 1 is for LVDS output + + required: + - port@0 + - port@1 + +required: + - compatible + - ports + +examples: + - | + lvds-encoder { + compatible = "lvds-encoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_enc_in: endpoint { + remote-endpoint = <&display_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + + lvds_enc_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; + }; + +... -- cgit v1.2.3 From 9acfa9d30ad71a64049b1f1b61c7f937e12531df Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Nov 2019 15:51:21 +0000 Subject: dt-bindings: display: bridge: lvds-transmitter: Document powerdown-gpios Add documentation for property powerdown-gpios. The property is optional. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/1573660292-10629-3-git-send-email-fabrizio.castro@bp.renesas.com --- .../devicetree/bindings/display/bridge/lvds-transmitter.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml index b5dd0da71394..2484737233f6 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml @@ -57,6 +57,11 @@ properties: - port@0 - port@1 + powerdown-gpios: + description: + The GPIO used to control the power down line of this device. + maxItems: 1 + required: - compatible - ports -- cgit v1.2.3 From 5240272d4323c20265329a6b85b799bddf9827df Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Nov 2019 15:51:22 +0000 Subject: dt-bindings: display: bridge: lvds-transmitter: Absorb ti, ds90c185.txt ti,ds90c185.txt documents LVDS encoders using the same driver as the one documented by lvds-transmitter.yaml. Since the properties listed in ti,ds90c185.txt are the same as the ones listed in lvds-transmitter.yaml, absorb the dt-binding into lvds-transmitter.yaml. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/1573660292-10629-4-git-send-email-fabrizio.castro@bp.renesas.com --- .../bindings/display/bridge/lvds-transmitter.yaml | 14 +++--- .../bindings/display/bridge/ti,ds90c185.txt | 55 ---------------------- 2 files changed, 8 insertions(+), 61 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml index 2484737233f6..a8326ceec9fd 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml @@ -31,11 +31,13 @@ description: | properties: compatible: description: | - Any encoder compatible with this generic binding, but with additional - properties not listed here, must define its own binding and list a device - specific compatible first followed by the generic compatible. - enum: - - lvds-encoder + Must list the device specific compatible string first, followed by the + generic compatible string. + items: + - enum: + - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer + - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer + - const: lvds-encoder # Generic LVDS encoder compatible fallback ports: type: object @@ -69,7 +71,7 @@ required: examples: - | lvds-encoder { - compatible = "lvds-encoder"; + compatible = "ti,ds90c185", "lvds-encoder"; ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt b/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt deleted file mode 100644 index e575f996959a..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt +++ /dev/null @@ -1,55 +0,0 @@ -Texas Instruments FPD-Link (LVDS) Serializer --------------------------------------------- - -The DS90C185 and DS90C187 are low-power serializers for portable -battery-powered applications that reduces the size of the RGB -interface between the host GPU and the display. - -Required properties: - -- compatible: Should be - "ti,ds90c185", "lvds-encoder" for the TI DS90C185 FPD-Link Serializer - "ti,ds90c187", "lvds-encoder" for the TI DS90C187 FPD-Link Serializer - -Optional properties: - -- powerdown-gpios: Power down control GPIO (the PDB pin, active-low) - -Required nodes: - -The devices have two video ports. Their connections are modeled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for parallel input -- Video port 1 for LVDS output - - -Example -------- - -lvds-encoder { - compatible = "ti,ds90c185", "lvds-encoder"; - - powerdown-gpios = <&gpio 17 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint { - remote-endpoint = <&lcdc_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint { - remote-endpoint = <&lvds_panel_in>; - }; - }; - }; -}; -- cgit v1.2.3 From 4788f4e11d1d3dc304b119b993d3ce39a5fd22c3 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Nov 2019 15:51:23 +0000 Subject: dt-bindings: display: bridge: lvds-transmitter: Document "ti, sn75lvds83" Compatible string "ti,sn75lvds83" is being used by device tree rk3188-bqedison2qc.dts, but it's not documented anywhere, therefore document it within lvds-transmitter.yaml. Signed-off-by: Fabrizio Castro Acked-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/1573660292-10629-5-git-send-email-fabrizio.castro@bp.renesas.com --- Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml index a8326ceec9fd..27de616a1973 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml @@ -37,6 +37,7 @@ properties: - enum: - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer + - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter - const: lvds-encoder # Generic LVDS encoder compatible fallback ports: -- cgit v1.2.3 From 575af8ecd1943d432ede9891e1419d001fa67c5d Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Nov 2019 15:51:27 +0000 Subject: dt-bindings: display: bridge: Repurpose lvds-encoder In an effort to repurpose lvds-encoder.c to also serve the function of LVDS decoders, we ended up defining a new "generic" compatible string ("lvds-decoder"), therefore adapt the dt schema to allow for the new compatible string. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart [narmstrong: fixed port descriptions as acked with lpinchart] Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/1573660292-10629-9-git-send-email-fabrizio.castro@bp.renesas.com --- .../bindings/display/bridge/lvds-codec.yaml | 129 +++++++++++++++++++++ .../bindings/display/bridge/lvds-transmitter.yaml | 99 ---------------- 2 files changed, 129 insertions(+), 99 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml delete mode 100644 Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml new file mode 100644 index 000000000000..f714fbd2814d --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/lvds-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Transparent LVDS encoders and decoders + +maintainers: + - Laurent Pinchart + +description: | + This binding supports transparent LVDS encoders and decoders that don't + require any configuration. + + LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple + incompatible data link layers have been used over time to transmit image data + to LVDS panels. This binding targets devices compatible with the following + specifications only. + + [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February + 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) + [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National + Semiconductor + [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video + Electronics Standards Association (VESA) + + Those devices have been marketed under the FPD-Link and FlatLink brand names + among others. + +properties: + compatible: + description: | + Must list the device specific compatible string first, followed by the + generic compatible string. + oneOf: + - items: + - enum: + - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer + - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer + - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter + - const: lvds-encoder # Generic LVDS encoder compatible fallback + - const: lvds-decoder # Generic LVDS decoders compatible fallback + + ports: + type: object + description: | + This device has two video ports. Their connections are modeled using the + OF graph bindings specified in Documentation/devicetree/bindings/graph.txt + properties: + port@0: + type: object + description: | + For LVDS encoders, port 0 is the parallel input + For LVDS decoders, port 0 is the LVDS input + + port@1: + type: object + description: | + For LVDS encoders, port 1 is the LVDS output + For LVDS decoders, port 1 is the parallel output + + required: + - port@0 + - port@1 + + powerdown-gpios: + description: + The GPIO used to control the power down line of this device. + maxItems: 1 + +required: + - compatible + - ports + +examples: + - | + lvds-encoder { + compatible = "ti,ds90c185", "lvds-encoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_enc_in: endpoint { + remote-endpoint = <&display_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + + lvds_enc_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; + }; + + - | + lvds-decoder { + compatible = "lvds-decoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_dec_in: endpoint { + remote-endpoint = <&display_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + + lvds_dec_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml deleted file mode 100644 index 27de616a1973..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.yaml +++ /dev/null @@ -1,99 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/bridge/lvds-transmitter.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Parallel to LVDS Encoder - -maintainers: - - Laurent Pinchart - -description: | - This binding supports the parallel to LVDS encoders that don't require any - configuration. - - LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple - incompatible data link layers have been used over time to transmit image data - to LVDS panels. This binding targets devices compatible with the following - specifications only. - - [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February - 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) - [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National - Semiconductor - [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video - Electronics Standards Association (VESA) - - Those devices have been marketed under the FPD-Link and FlatLink brand names - among others. - -properties: - compatible: - description: | - Must list the device specific compatible string first, followed by the - generic compatible string. - items: - - enum: - - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer - - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer - - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter - - const: lvds-encoder # Generic LVDS encoder compatible fallback - - ports: - type: object - description: | - This device has two video ports. Their connections are modeled using the - OF graph bindings specified in Documentation/devicetree/bindings/graph.txt - properties: - port@0: - type: object - description: | - Port 0 is for parallel input - - port@1: - type: object - description: | - Port 1 is for LVDS output - - required: - - port@0 - - port@1 - - powerdown-gpios: - description: - The GPIO used to control the power down line of this device. - maxItems: 1 - -required: - - compatible - - ports - -examples: - - | - lvds-encoder { - compatible = "ti,ds90c185", "lvds-encoder"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint { - remote-endpoint = <&display_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint { - remote-endpoint = <&lvds_panel_in>; - }; - }; - }; - }; - -... -- cgit v1.2.3 From b7de4ba7dbe962d38768e0396f7acd11eff7628b Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Nov 2019 15:51:28 +0000 Subject: dt-bindings: display: bridge: lvds-codec: Document ti, ds90cf384a The DS90CF384A from TI is a transparent LVDS receiver (decoder), and therefore it is compatible with the lvds-codec driver and bindings. Document the ti,ds90cf384a compatible string with the dt-bindings. No driver change required. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/1573660292-10629-10-git-send-email-fabrizio.castro@bp.renesas.com --- Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index f714fbd2814d..9f27d4d91a10 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -40,7 +40,10 @@ properties: - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter - const: lvds-encoder # Generic LVDS encoder compatible fallback - - const: lvds-decoder # Generic LVDS decoders compatible fallback + - items: + - enum: + - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver + - const: lvds-decoder # Generic LVDS decoders compatible fallback ports: type: object @@ -102,7 +105,7 @@ examples: - | lvds-decoder { - compatible = "lvds-decoder"; + compatible = "ti,ds90cf384a", "lvds-decoder"; ports { #address-cells = <1>; -- cgit v1.2.3 From cad8c44a9ff0da507f1e225e0ad342d69dbbc4cd Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Nov 2019 15:51:32 +0000 Subject: dt-bindings: display: bridge: lvds-codec: Absorb thine, thc63lvdm83d.txt At this point in time, compatible string "thine,thc63lvdm83d" is backed by the lvds-codec driver, and the documentation contained in thine,thc63lvdm83d.txt is basically the same as the one contained in lvds-codec.yaml (generic fallback compatible string aside), therefore absorb thine,thc63lvdm83d.txt. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/ <1573660292-10629-14-git-send-email-fabrizio.castro@bp.renesas.com --- .../bindings/display/bridge/lvds-codec.yaml | 5 +-- .../bindings/display/bridge/thine,thc63lvdm83d.txt | 50 ---------------------- 2 files changed, 2 insertions(+), 53 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index 9f27d4d91a10..8f373029f5d2 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -30,9 +30,6 @@ description: | properties: compatible: - description: | - Must list the device specific compatible string first, followed by the - generic compatible string. oneOf: - items: - enum: @@ -44,6 +41,8 @@ properties: - enum: - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver - const: lvds-decoder # Generic LVDS decoders compatible fallback + - enum: + - thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer ports: type: object diff --git a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt deleted file mode 100644 index fee3c88e1a17..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt +++ /dev/null @@ -1,50 +0,0 @@ -THine Electronics THC63LVDM83D LVDS serializer ----------------------------------------------- - -The THC63LVDM83D is an LVDS serializer designed to support pixel data -transmission between a host and a flat panel. - -Required properties: - -- compatible: Should be "thine,thc63lvdm83d" - -Optional properties: - -- powerdown-gpios: Power down control GPIO (the /PWDN pin, active low). - -Required nodes: - -The THC63LVDM83D has two video ports. Their connections are modeled using the -OFgraph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for CMOS/TTL input -- Video port 1 for LVDS output - - -Example -------- - - lvds_enc: encoder@0 { - compatible = "thine,thc63lvdm83d"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint@0 { - remote-endpoint = <&rgb_out>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint@0 { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; -- cgit v1.2.3 From 93ccfa9a4eca482216c5caf88be77e5ffa0d744a Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 19 Dec 2019 17:17:22 +0100 Subject: drm/todo: Updating logging todo Jani has merged a new set of logging functions, which we hope to be the One True solution now, pinky promises: commit fb6c7ab8718eb2543695d77ad8302ff81e8e1e32 Author: Jani Nikula Date: Tue Dec 10 14:30:43 2019 +0200 drm/print: introduce new struct drm_device based logging macros Update the todo entry to match the new preference. v2: Fix spelling issue Sam noticed. Cc: Jani Nikula Cc: Sean Paul Cc: Wambui Karuga Acked-by: Jani Nikula Acked-by: Sam Ravnborg Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20191219161722.2779994-1-daniel.vetter@ffwll.ch --- Documentation/gpu/todo.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 2d85f37284a1..bc869b23fc39 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -142,14 +142,14 @@ Contact: Daniel Vetter, respective driver maintainers Level: Advanced -Convert instances of dev_info/dev_err/dev_warn to their DRM_DEV_* equivalent ----------------------------------------------------------------------------- +Convert logging to drm_* functions with drm_device paramater +------------------------------------------------------------ For drivers which could have multiple instances, it is necessary to differentiate between which is which in the logs. Since DRM_INFO/WARN/ERROR don't do this, drivers used dev_info/warn/err to make this differentiation. We -now have DRM_DEV_* variants of the drm print macros, so we can start to convert -those drivers back to using drm-formwatted specific log messages. +now have drm_* variants of the drm print functions, so we can start to convert +those drivers back to using drm-formatted specific log messages. Before you start this conversion please contact the relevant maintainers to make sure your work will be merged - not everyone agrees that the DRM dmesg macros -- cgit v1.2.3 From fe5040f2843a638d847282520e5eeaa61a4769e2 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 22 Dec 2019 18:52:23 +0530 Subject: dt-bindings: sun6i-dsi: Document A64 MIPI-DSI controller The MIPI DSI controller in Allwinner A64 is similar to A33. But unlike A33, A64 doesn't have DSI_SCLK gating so it is valid to have separate compatible for A64 on the same driver. DSI_SCLK uses mod clock-names on dt-bindings, so the same is not required for A64. On that note - A64 require minimum of 1 clock like the bus clock - A33 require minimum of 2 clocks like both bus, mod clocks So, update dt-bindings so-that it can document both A33, A64 bindings requirements. Reviewed-by: Rob Herring Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20191222132229.30276-2-jagan@amarulasolutions.com --- .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 33 ++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index dafc0980c4fa..d41ecb5e7f7c 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -15,7 +15,9 @@ properties: "#size-cells": true compatible: - const: allwinner,sun6i-a31-mipi-dsi + enum: + - allwinner,sun6i-a31-mipi-dsi + - allwinner,sun50i-a64-mipi-dsi reg: maxItems: 1 @@ -24,6 +26,8 @@ properties: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 items: - description: Bus Clock - description: Module Clock @@ -63,13 +67,38 @@ required: - reg - interrupts - clocks - - clock-names - phys - phy-names - resets - vcc-dsi-supply - port +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-mipi-dsi + + then: + properties: + clocks: + minItems: 2 + + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-a64-mipi-dsi + + then: + properties: + clocks: + minItems: 1 + additionalProperties: false examples: -- cgit v1.2.3 From db08ca5a64d208645301600e79f34e441e5da986 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 22 Dec 2019 18:52:24 +0530 Subject: dt-bindings: sun6i-dsi: Add A64 DPHY compatible (w/ A31 fallback) The MIPI DSI PHY controller on Allwinner A64 is similar on the one on A31. Add A64 compatible and append A31 compatible as fallback. Reviewed-by: Rob Herring Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20191222132229.30276-3-jagan@amarulasolutions.com --- .../devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml index fa46670de299..8841938050b2 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml @@ -15,7 +15,11 @@ properties: const: 0 compatible: - const: allwinner,sun6i-a31-mipi-dphy + oneOf: + - const: allwinner,sun6i-a31-mipi-dphy + - items: + - const: allwinner,sun50i-a64-mipi-dphy + - const: allwinner,sun6i-a31-mipi-dphy reg: maxItems: 1 -- cgit v1.2.3 From b435f8b4f6a08f5bbf001cfd4bed22070e3774fd Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Thu, 21 Nov 2019 20:26:42 -0500 Subject: dt-bindings: drm/msm/gpu: document second interconnect Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. There's a separate interconnect path that needs to be setup to OCMEM. Let's document this second interconnect path that's available. Since there's now two available interconnects, let's add the interconnect-names property. Signed-off-by: Brian Masney Acked-by: Rob Herring Reviewed-by: Bjorn Andersson Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/gpu.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 2b8fd26c43b0..3e6cd3f64a78 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -23,7 +23,10 @@ Required properties: - iommus: optional phandle to an adreno iommu instance - operating-points-v2: optional phandle to the OPP operating points - interconnects: optional phandle to an interconnect provider. See - ../interconnect/interconnect.txt for details. + ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms + will have two paths; all others will have one path. +- interconnect-names: The names of the interconnect paths that correspond to the + interconnects property. Values must be gfx-mem and ocmem. - qcom,gmu: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. Applicable targets: - qcom,adreno-630.2 @@ -76,6 +79,7 @@ Example a6xx (with GMU): operating-points-v2 = <&gpu_opp_table>; interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + interconnect-names = "gfx-mem"; qcom,gmu = <&gmu>; -- cgit v1.2.3 From 854f94226a91010e81e09d79ba7ea253e64e6091 Mon Sep 17 00:00:00 2001 From: Kalyan Thota Date: Mon, 25 Nov 2019 17:29:26 +0530 Subject: dt-bindings: msm:disp: add sc7180 DPU variant Add a compatible string to support sc7180 dpu version. Signed-off-by: Kalyan Thota Acked-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/dpu.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index a61dd40f3792..551ae26f60da 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC. MDSS: Required properties: -- compatible: "qcom,sdm845-mdss" +- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" - reg: physical base address and length of contoller's registers. - reg-names: register region names. The following region is required: * "mdss" @@ -41,7 +41,7 @@ Optional properties: MDP: Required properties: -- compatible: "qcom,sdm845-dpu" +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" - reg: physical base address and length of controller's registers. - reg-names : register region names. The following region is required: * "mdp" -- cgit v1.2.3 From fd933c00ebe220060e66fb136a7050a242456566 Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Tue, 27 Aug 2019 11:09:16 +0000 Subject: fbdev: fix numbering of fbcon options Three shall be the number thou shalt count, and the number of the counting shall be three. Four shalt thou not count... One! Two! Five! Fixes: efb985f6b265 ("[PATCH] fbcon: Console Rotation - Add framebuffer console documentation") Signed-off-by: Peter Rosin Reviewed-by: Geert Uytterhoeven Cc: Jonathan Corbet Cc: Matthew Wilcox Signed-off-by: Bartlomiej Zolnierkiewicz Link: https://patchwork.freedesktop.org/patch/msgid/20190827110854.12574-2-peda@axentia.se --- Documentation/fb/fbcon.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/fb/fbcon.rst b/Documentation/fb/fbcon.rst index ebca41785abe..65ba40255137 100644 --- a/Documentation/fb/fbcon.rst +++ b/Documentation/fb/fbcon.rst @@ -127,7 +127,7 @@ C. Boot options is typically located on the same video card. Thus, the consoles that are controlled by the VGA console will be garbled. -4. fbcon=rotate: +5. fbcon=rotate: This option changes the orientation angle of the console display. The value 'n' accepts the following: @@ -152,21 +152,21 @@ C. Boot options Actually, the underlying fb driver is totally ignorant of console rotation. -5. fbcon=margin: +6. fbcon=margin: This option specifies the color of the margins. The margins are the leftover area at the right and the bottom of the screen that are not used by text. By default, this area will be black. The 'color' value is an integer number that depends on the framebuffer driver being used. -6. fbcon=nodefer +7. fbcon=nodefer If the kernel is compiled with deferred fbcon takeover support, normally the framebuffer contents, left in place by the firmware/bootloader, will be preserved until there actually is some text is output to the console. This option causes fbcon to bind immediately to the fbdev device. -7. fbcon=logo-pos: +8. fbcon=logo-pos: The only possible 'location' is 'center' (without quotes), and when given, the bootup logo is moved from the default top-left corner -- cgit v1.2.3 From 691f50ab2742556aea467a946e10393da2e8d9ef Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Tue, 27 Aug 2019 11:09:21 +0000 Subject: fbdev: fbmem: allow overriding the number of bootup logos Probably most useful if you want no logo at all, or if you only want one logo regardless of how many CPU cores you have. Signed-off-by: Peter Rosin Reviewed-by: Geert Uytterhoeven Cc: Jonathan Corbet Cc: Matthew Wilcox Signed-off-by: Bartlomiej Zolnierkiewicz Link: https://patchwork.freedesktop.org/patch/msgid/20190827110854.12574-3-peda@axentia.se --- Documentation/fb/fbcon.rst | 5 +++++ drivers/video/fbdev/core/fbcon.c | 7 +++++++ drivers/video/fbdev/core/fbmem.c | 12 +++++++++--- include/linux/fb.h | 1 + 4 files changed, 22 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/fb/fbcon.rst b/Documentation/fb/fbcon.rst index 65ba40255137..e57a3d1d085a 100644 --- a/Documentation/fb/fbcon.rst +++ b/Documentation/fb/fbcon.rst @@ -174,6 +174,11 @@ C. Boot options displayed due to multiple CPUs, the collected line of logos is moved as a whole. +9. fbcon=logo-count: + + The value 'n' overrides the number of bootup logos. 0 disables the + logo, and -1 gives the default which is the number of online CPUs. + C. Attaching, Detaching and Unloading Before going on to how to attach, detach and unload the framebuffer console, an diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c index c9235a2f42f8..bb6ae995c2e5 100644 --- a/drivers/video/fbdev/core/fbcon.c +++ b/drivers/video/fbdev/core/fbcon.c @@ -536,6 +536,13 @@ static int __init fb_console_setup(char *this_opt) fb_center_logo = true; continue; } + + if (!strncmp(options, "logo-count:", 11)) { + options += 11; + if (*options) + fb_logo_count = simple_strtol(options, &options, 0); + continue; + } } return 1; } diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c index 7ddeb90337bc..7ce21009f85d 100644 --- a/drivers/video/fbdev/core/fbmem.c +++ b/drivers/video/fbdev/core/fbmem.c @@ -56,6 +56,8 @@ EXPORT_SYMBOL(num_registered_fb); bool fb_center_logo __read_mostly; EXPORT_SYMBOL(fb_center_logo); +int fb_logo_count __read_mostly = -1; + static struct fb_info *get_fb_info(unsigned int idx) { struct fb_info *fb_info; @@ -620,7 +622,7 @@ int fb_prepare_logo(struct fb_info *info, int rotate) memset(&fb_logo, 0, sizeof(struct logo_data)); if (info->flags & FBINFO_MISC_TILEBLITTING || - info->fbops->owner) + info->fbops->owner || !fb_logo_count) return 0; if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { @@ -686,10 +688,14 @@ int fb_prepare_logo(struct fb_info *info, int rotate) int fb_show_logo(struct fb_info *info, int rotate) { + unsigned int count; int y; - y = fb_show_logo_line(info, rotate, fb_logo.logo, 0, - num_online_cpus()); + if (!fb_logo_count) + return 0; + + count = fb_logo_count < 0 ? num_online_cpus() : fb_logo_count; + y = fb_show_logo_line(info, rotate, fb_logo.logo, 0, count); y = fb_show_extra_logos(info, y, rotate); return y; diff --git a/include/linux/fb.h b/include/linux/fb.h index 6557fabdea62..3b4b2f0c6994 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -625,6 +625,7 @@ extern int fb_new_modelist(struct fb_info *info); extern struct fb_info *registered_fb[FB_MAX]; extern int num_registered_fb; extern bool fb_center_logo; +extern int fb_logo_count; extern struct class *fb_class; #define for_each_registered_fb(i) \ -- cgit v1.2.3 From 3862c824de3aa73be5a5ba716f6df8085cc67473 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 24 Dec 2019 12:29:05 +0100 Subject: dt-bindings: Add vendor prefix for Xinpeng Technology Shenzhen Xinpeng Technology Co., Ltd produces for example display panels. Signed-off-by: Heiko Stuebner Acked-by: Sam Ravnborg Acked-by: Rob Herring Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20191224112907.30758-1-heiko@sntech.de --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 967e78c5ec0a..d7c5c47dc47c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1050,6 +1050,8 @@ patternProperties: description: Extreme Engineering Solutions (X-ES) "^xillybus,.*": description: Xillybus Ltd. + "^xinpeng,.*": + description: Shenzhen Xinpeng Technology Co., Ltd "^xlnx,.*": description: Xilinx "^xunlong,.*": -- cgit v1.2.3 From 01d53e327dabff04859f76e2917fd95ef1844d3e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 24 Dec 2019 12:29:06 +0100 Subject: dt-bindings: display: panel: Add binding document for Xinpeng XPP055C272 The XPP055C272 is a 5.5" 720x1280 DSI display. changes in v4: - fix id (Maxime) - drop port (Maxime) changes in v2: - add size info into binding title (Sam) - add more required properties (Sam) Signed-off-by: Heiko Stuebner Reviewed-by: Sam Ravnborg Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20191224112907.30758-2-heiko@sntech.de --- .../bindings/display/panel/xinpeng,xpp055c272.yaml | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml b/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml new file mode 100644 index 000000000000..378cf9e2549d --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/xinpeng,xpp055c272.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xinpeng XPP055C272 5.5in 720x1280 DSI panel + +maintainers: + - Heiko Stuebner + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: xinpeng,xpp055c272 + reg: true + backlight: true + reset-gpios: true + iovcc-supply: + description: regulator that supplies the iovcc voltage + vci-supply: + description: regulator that supplies the vci voltage + +required: + - compatible + - reg + - backlight + - iovcc-supply + - vci-supply + +additionalProperties: false + +examples: + - | + dsi@ff450000 { + panel@0 { + compatible = "xinpeng,xpp055c272"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + vci-supply = <&vcc3v3_lcd>; + }; + }; + +... -- cgit v1.2.3 From e8d47c471b990db1459f386276089c4893ad28d4 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 24 Dec 2019 12:26:39 +0100 Subject: dt-bindings: Add vendor prefix for Leadtek Technology Shenzhen Leadtek Technology Co., Ltd. produces for example display and touch panels. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20191224112641.30647-1-heiko@sntech.de --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index d7c5c47dc47c..2dd835af0994 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -511,6 +511,8 @@ patternProperties: description: Lantiq Semiconductor "^lattice,.*": description: Lattice Semiconductor + "^leadtek,.*": + description: Shenzhen Leadtek Technology Co., Ltd. "^leez,.*": description: Leez "^lego,.*": -- cgit v1.2.3 From eeb15a55d22bacc49814bfccf43e2397e6e5f476 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 24 Dec 2019 12:26:40 +0100 Subject: dt-bindings: display: panel: Add binding document for Leadtek LTK500HD1829 The LTK500HD1829 is a 5.0" 720x1280 DSI display. v3: - fixed example by adding address,size-cells (sam) changes in v2: - fix id (Maxime) - drop port (Maxime) Signed-off-by: Heiko Stuebner Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20191224112641.30647-2-heiko@sntech.de --- .../display/panel/leadtek,ltk500hd1829.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml b/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml new file mode 100644 index 000000000000..4ebcea7d0c63 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/leadtek,ltk500hd1829.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Leadtek LTK500HD1829 5.0in 720x1280 DSI panel + +maintainers: + - Heiko Stuebner + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: leadtek,ltk500hd1829 + reg: true + backlight: true + reset-gpios: true + iovcc-supply: + description: regulator that supplies the iovcc voltage + vcc-supply: + description: regulator that supplies the vcc voltage + +required: + - compatible + - reg + - backlight + - iovcc-supply + - vcc-supply + +additionalProperties: false + +examples: + - | + dsi@ff450000 { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "leadtek,ltk500hd1829"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + vcc-supply = <&vcc_2v8>; + }; + }; + +... -- cgit v1.2.3 From d1dc01860a2a2e9a542485b732ece729402c2bd5 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 24 Dec 2019 15:38:50 +0100 Subject: dt-bindings: display: rockchip-lvds: Declare PX30 compatible Document the PX30 LVDS compatible. Signed-off-by: Miquel Raynal Acked-by: Rob Herring Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/20191224143900.23567-2-miquel.raynal@bootlin.com --- Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt index 7849ff039229..aa5663a6fd42 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt @@ -4,6 +4,7 @@ Rockchip RK3288 LVDS interface Required properties: - compatible: matching the soc type, one of - "rockchip,rk3288-lvds"; + - "rockchip,px30-lvds"; - reg: physical base address of the controller and length of memory mapped region. -- cgit v1.2.3 From 1e0b0a0cf31a1c2d7770bed904c66c4e71e01311 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 24 Dec 2019 15:38:51 +0100 Subject: dt-bindings: display: rockchip-lvds: Document PX30 PHY PX30 SoCs use a single PHY shared by two display pipelines: MIPI DSI and LVDS. In the case of the LVDS IP, document the possibility to fill a PHY handle. Signed-off-by: Miquel Raynal Acked-by: Rob Herring Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/20191224143900.23567-3-miquel.raynal@bootlin.com --- Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt index aa5663a6fd42..aaf8c44cf90f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt @@ -19,6 +19,9 @@ Required properties: - rockchip,grf: phandle to the general register files syscon - rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface +- phys: LVDS/DSI DPHY (px30 only) +- phy-names: name of the PHY, must be "dphy" (px30 only) + Optional properties: - pinctrl-names: must contain a "lcdc" entry. - pinctrl-0: pin control group to be used for this controller. -- cgit v1.2.3 From bf046007641a7ef76d4ed976ac67bf24d05ac51a Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Mon, 6 Jan 2020 19:17:31 +0100 Subject: dt-bindings: fix warnings in xinpeng,xpp055c272.yaml The reg property in the example caused following warnings: xinpeng,xpp055c272.example.dts:20.17-27: Warning (reg_format): /example-0/dsi@ff450000/panel@0:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) xinpeng,xpp055c272.example.dt.yaml: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' xinpeng,xpp055c272.example.dt.yaml: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' xinpeng,xpp055c272.example.dt.yaml: Warning (spi_bus_reg): Failed prerequisite 'reg_format' xinpeng,xpp055c272.example.dts:18.21-24.15: Warning (avoid_default_addr_size): /example-0/dsi@ff450000/panel@0: Relying on default #address-cells value xinpeng,xpp055c272.example.dts:18.21-24.15: Warning (avoid_default_addr_size): /example-0/dsi@ff450000/panel@0: Relying on default #size-cells value Added #address-cells and #size-cells to silence the warning. Signed-off-by: Sam Ravnborg Reviewed-by: Heiko Stuebner Cc: Maxime Ripard Cc: Rob Herring Cc: devicetree@vger.kernel.org Link: https://patchwork.freedesktop.org/patch/msgid/20200106181731.GA24294@ravnborg.org --- Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml b/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml index 378cf9e2549d..186e5e1c8fa3 100644 --- a/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml +++ b/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml @@ -35,6 +35,8 @@ additionalProperties: false examples: - | dsi@ff450000 { + #address-cells = <1>; + #size-cells = <0>; panel@0 { compatible = "xinpeng,xpp055c272"; reg = <0>; -- cgit v1.2.3 From 6ab2b3d9dc602230624afa8170f746c59d7fabde Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Thu, 2 Jan 2020 11:17:11 +0100 Subject: dt-bindings: one binding file for all simple panels There is an increasing number of new simple panels. Common for many of these simple panels are that they have one mandatory power-supply and some of them have backlight and / or an enable gpio. The binding file to describe these panels adds overhead that really do not add value. The binding are known and there is nothing gained from a dedicated binding file nor for any dedicated example. The following patch introduces a single panel-simple.yaml and converts two ampire bindings over to the new file. The conversion - if applied will have following effects: - The maintainer for the individual file will change There is no need for many different maintainers for a simple binding. We have the same situation with the panel-simple driver in the kernel. - The license will change to (GPL-2.0-only OR BSD-2-Clause) There is usually only a single line copied from the original file, a line that is often copied from a datasheet. This license change should be acceptable considered what little is copied. If the license change is not OK we can use a dedicated binding file in these cases. This is a follow-up on Rob's big patch converting a lot of panel bindings to individual files: "dt-bindings: display: Convert a bunch of panels to DT schema" https://patchwork.ozlabs.org/patch/1197683/ The objectives with one file for the relevant simple panels are: - Make it simpler to add bindings for simple panels - Keep the number of bindings file lower and thus easier to find a relevant file to copy from when adding new panels. - Keep the binding documentation for simple panels more consistent - Make it simpler to add support for new panels v3: - Whitespace fix (checkpatch) - Indent compatible (Rob h) - Indent comments to give compatible more visibility (Rob h) v2: - spelling fixes (imirkin via irc, Rob) - updated description (Rob) - list properires in alphabetical order - added power-supply to example (Rob) - updated title - reworded changelog a little Signed-off-by: Sam Ravnborg Reviewed-by: Rob Herring Benjamin Gaignard Cc: Thierry Reding Cc: Maxime Ripard Cc: Yannick Fertre Cc: Mark Rutland Cc: Daniel Vetter Cc: dri-devel@lists.freedesktop.org Cc: devicetree@vger.kernel.org Link: https://patchwork.freedesktop.org/patch/msgid/20200102101712.5085-2-sam@ravnborg.org --- .../display/panel/ampire,am-480272h3tmqw-t01h.yaml | 42 --------------- .../display/panel/ampire,am800480r3tmqwa1h.txt | 7 --- .../bindings/display/panel/panel-simple.yaml | 59 ++++++++++++++++++++++ 3 files changed, 59 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml delete mode 100644 Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt create mode 100644 Documentation/devicetree/bindings/display/panel/panel-simple.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml b/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml deleted file mode 100644 index c6e33e7f36d0..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/panel/ampire,am-480272h3tmqw-t01h.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel - -maintainers: - - Yannick Fertre - - Thierry Reding - -allOf: - - $ref: panel-common.yaml# - -properties: - compatible: - const: ampire,am-480272h3tmqw-t01h - - power-supply: true - enable-gpios: true - backlight: true - port: true - -required: - - compatible - -additionalProperties: false - -examples: - - | - panel_rgb: panel { - compatible = "ampire,am-480272h3tmqw-t01h"; - enable-gpios = <&gpioa 8 1>; - port { - panel_in_rgb: endpoint { - remote-endpoint = <&controller_out_rgb>; - }; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt b/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt deleted file mode 100644 index 83e2cae1cc1b..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt +++ /dev/null @@ -1,7 +0,0 @@ -Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "ampire,am800480r3tmqwa1h" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml new file mode 100644 index 000000000000..090866260f4f --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/panel-simple.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple panels with one power supply + +maintainers: + - Thierry Reding + - Sam Ravnborg + +description: | + This binding file is a collection of the simple (dumb) panels that + requires only a single power-supply. + There are optionally a backlight and an enable GPIO. + The panel may use an OF graph binding for the association to the display, + or it may be a direct child node of the display. + + If the panel is more advanced a dedicated binding file is required. + +allOf: + - $ref: panel-common.yaml# + +properties: + + compatible: + enum: + # compatible must be listed in alphabetical order, ordered by compatible. + # The description in the comment is mandatory for each compatible. + + # Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel + - ampire,am-480272h3tmqw-t01h + # Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel + - ampire,am800480r3tmqwa1h + + backlight: true + enable-gpios: true + port: true + power-supply: true + +additionalProperties: false + +required: + - compatible + - power-supply + +examples: + - | + panel_rgb: panel-rgb { + compatible = "ampire,am-480272h3tmqw-t01h"; + power-supply = <&vcc_lcd_reg>; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; -- cgit v1.2.3 From c00481d072506b471102e485d8b8bf324b11efdc Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 6 Jan 2020 16:18:25 +0100 Subject: dt-bindings: Add vendor prefix for Satoz Satoz is a Chinese TFT manufacturer. Website: http://www.sat-sz.com/English/index.html Signed-off-by: Miquel Raynal Acked-by: Rob Herring Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20200106151827.31511-1-miquel.raynal@bootlin.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 4e6248ec5ed9..835579edc971 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -825,6 +825,8 @@ patternProperties: description: Sancloud Ltd "^sandisk,.*": description: Sandisk Corporation + "^satoz,.*": + description: Satoz International Co., Ltd "^sbs,.*": description: Smart Battery System "^schindler,.*": -- cgit v1.2.3 From eb0201e600311b07a7593f0794b3801e26dba589 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 8 Jan 2020 15:53:55 -0800 Subject: dt-bindings: display: panel: Add AUO B116XAK01 panel bindings Signed-off-by: Rob Clark Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20200108235356.918189-1-robdclark@gmail.com --- Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 090866260f4f..5f1d765447bc 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -33,6 +33,8 @@ properties: - ampire,am-480272h3tmqw-t01h # Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel - ampire,am800480r3tmqwa1h + # AUO B116XAK01 eDP TFT LCD panel + - auo,b116xa01 backlight: true enable-gpios: true -- cgit v1.2.3 From 2ae4829d222e9ad066b1bcbdabefc3e5d039d46c Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Wed, 8 Jan 2020 21:29:59 -0300 Subject: dt-bindings: panel-simple: Add compatible for GiantPlus GPM940B0 Add a compatible string for the GiantPlus GPM740B0 3" QVGA TFT LCD panel, and remove the old giantplus,gpm740b0.txt documentation which is now obsolete. Signed-off-by: Paul Cercueil Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20200109003000.119516-1-paul@crapouillou.net --- .../devicetree/bindings/display/panel/giantplus,gpm940b0.txt | 12 ------------ .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 2 files changed, 2 insertions(+), 12 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt b/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt deleted file mode 100644 index 3dab52f92c26..000000000000 --- a/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt +++ /dev/null @@ -1,12 +0,0 @@ -GiantPlus 3.0" (320x240 pixels) 24-bit TFT LCD panel - -Required properties: -- compatible: should be "giantplus,gpm940b0" -- power-supply: as specified in the base binding - -Optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 5f1d765447bc..cbcd3d7e4591 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -35,6 +35,8 @@ properties: - ampire,am800480r3tmqwa1h # AUO B116XAK01 eDP TFT LCD panel - auo,b116xa01 + # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel + - giantplus,gpm940b0 backlight: true enable-gpios: true -- cgit v1.2.3 From 240a25720925b5033a27863fb051a2c384a4dd64 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Wed, 8 Jan 2020 21:30:00 -0300 Subject: dt-bindings: panel-simple: Add compatible for Sharp LS020B1DD01D Add a compatible string for the Sharp LS020B1DD01D 2" HQVGA TFT LCD panel, and remove the old sharp,ls020b1dd01d.txt documentation which is now obsolete. Signed-off-by: Paul Cercueil Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20200109003000.119516-2-paul@crapouillou.net --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ .../devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt | 12 ------------ 2 files changed, 2 insertions(+), 12 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index cbcd3d7e4591..ddc00480b6fe 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -37,6 +37,8 @@ properties: - auo,b116xa01 # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel - giantplus,gpm940b0 + # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel + - sharp,ls020b1dd01d backlight: true enable-gpios: true diff --git a/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt b/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt deleted file mode 100644 index e45edbc565a3..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt +++ /dev/null @@ -1,12 +0,0 @@ -Sharp 2.0" (240x160 pixels) 16-bit TFT LCD panel - -Required properties: -- compatible: should be "sharp,ls020b1dd01d" -- power-supply: as specified in the base binding - -Optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. -- cgit v1.2.3 From 4cee2f8e03568a61c20a26d33158ae1309e10611 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Thu, 9 Jan 2020 14:48:41 +0100 Subject: dt-bindings: display: add BOE 14" panel Add bindings for the BOE NV140FHM-N49 14" 1920x1080 panel. The panel is used by the pine64 Pinebook Pro. Signed-off-by: Sam Ravnborg Reviewed-by: Tobias Schramm Cc: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20200109140742.GA12940@ravnborg.org --- Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index ddc00480b6fe..6c098a0b6e1e 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -35,6 +35,8 @@ properties: - ampire,am800480r3tmqwa1h # AUO B116XAK01 eDP TFT LCD panel - auo,b116xa01 + # BOE NV140FHM-N49 14.0" FHD a-Si FT panel + - boe,nv140fhmn49 # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel - giantplus,gpm940b0 # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel -- cgit v1.2.3 From f5a98bfe7b3726ba81b45b5597b880b62260ed98 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 3 Jan 2020 16:27:58 +0100 Subject: dt-bindings: display: Convert Allwinner display pipeline to schemas The Allwinner SoCs have a display engine composed of several controllers assembled differently depending on the SoC, the number and type of output they have, and the additional features they provide. A number of those are supported in Linux, with the matching bindings. Now that we have the DT validation in place, let's split into separate file and convert the device tree bindings for those controllers to schemas. Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20200103152801.47254-1-maxime@cerno.tech --- .../allwinner,sun4i-a10-display-backend.yaml | 291 +++++++++ .../allwinner,sun4i-a10-display-engine.yaml | 114 ++++ .../allwinner,sun4i-a10-display-frontend.yaml | 138 +++++ .../bindings/display/allwinner,sun4i-a10-hdmi.yaml | 183 ++++++ .../bindings/display/allwinner,sun4i-a10-tcon.yaml | 676 +++++++++++++++++++++ .../display/allwinner,sun4i-a10-tv-encoder.yaml | 62 ++ .../bindings/display/allwinner,sun6i-a31-drc.yaml | 138 +++++ .../display/allwinner,sun8i-a83t-de2-mixer.yaml | 118 ++++ .../display/allwinner,sun8i-a83t-dw-hdmi.yaml | 273 +++++++++ .../display/allwinner,sun8i-a83t-hdmi-phy.yaml | 117 ++++ .../display/allwinner,sun8i-r40-tcon-top.yaml | 382 ++++++++++++ .../bindings/display/allwinner,sun9i-a80-deu.yaml | 133 ++++ .../bindings/display/sunxi/sun4i-drm.txt | 637 ------------------- 13 files changed, 2625 insertions(+), 637 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml delete mode 100644 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml new file mode 100644 index 000000000000..86057d541065 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Engine Backend Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +description: | + The display engine backend exposes layers and sprites to the system. + +properties: + compatible: + enum: + - allwinner,sun4i-a10-display-backend + - allwinner,sun5i-a13-display-backend + - allwinner,sun6i-a31-display-backend + - allwinner,sun7i-a20-display-backend + - allwinner,sun8i-a23-display-backend + - allwinner,sun8i-a33-display-backend + - allwinner,sun9i-a80-display-backend + + reg: + minItems: 1 + maxItems: 2 + items: + - description: Display Backend registers + - description: SAT registers + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: be + - const: sat + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 4 + items: + - description: The backend interface clock + - description: The backend module clock + - description: The backend DRAM clock + - description: The SAT clock + + clock-names: + minItems: 3 + maxItems: 4 + items: + - const: ahb + - const: mod + - const: ram + - const: sat + + resets: + minItems: 1 + maxItems: 2 + items: + - description: The Backend reset line + - description: The SAT reset line + + reset-names: + minItems: 1 + maxItems: 2 + items: + - const: be + - const: sat + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnects: + maxItems: 1 + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnect-names: + const: dma-mem + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: allwinner,sun8i-a33-display-backend + +then: + properties: + reg: + minItems: 2 + + reg-names: + minItems: 2 + + clocks: + minItems: 4 + + clock-names: + minItems: 4 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + required: + - reg-names + - reset-names + +else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + +examples: + - | + /* + * This comes from the clock/sun4i-a10-ccu.h and + * reset/sun4i-a10-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_AHB_DE_BE0 42 + #define CLK_DRAM_DE_BE0 140 + #define CLK_DE_BE0 144 + #define RST_DE_BE0 5 + + display-backend@1e60000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; + }; + + - | + #include + + /* + * This comes from the clock/sun8i-a23-a33-ccu.h and + * reset/sun8i-a23-a33-ccu.h headers, but we can't include them + * since it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_BUS_DE_BE 40 + #define CLK_BUS_SAT 46 + #define CLK_DRAM_DE_BE 84 + #define CLK_DE_BE 85 + #define RST_BUS_DE_BE 21 + #define RST_BUS_SAT 27 + + display-backend@1e60000 { + compatible = "allwinner,sun8i-a33-display-backend"; + reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; + reg-names = "be", "sat"; + interrupts = ; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; + clock-names = "ahb", "mod", + "ram", "sat"; + resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; + reset-names = "be", "sat"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&fe0_out_be0>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml new file mode 100644 index 000000000000..944ff2f1cf93 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Engine Pipeline Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +description: | + The display engine pipeline (and its entry point, since it can be + either directly the backend or the frontend) is represented as an + extra node. + + The Allwinner A10 Display pipeline is composed of several components + that are going to be documented below: + + For all connections between components up to the TCONs in the + display pipeline, when there are multiple components of the same + type at the same depth, the local endpoint ID must be the same as + the remote component's index. For example, if the remote endpoint is + Frontend 1, then the local endpoint ID must be 1. + + Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0 + [1] -- -- [1] [1] -- -- [1] + \ / \ / + X X + / \ / \ + [0] -- -- [0] [0] -- -- [0] + Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1 + + For a two pipeline system such as the one depicted above, the lines + represent the connections between the components, while the numbers + within the square brackets corresponds to the ID of the local endpoint. + + The same rule also applies to DE 2.0 mixer-TCON connections: + + Mixer 0 [0] ----------- [0] TCON 0 + [1] ---- ---- [1] + \ / + X + / \ + [0] ---- ---- [0] + Mixer 1 [1] ----------- [1] TCON 1 + +properties: + compatible: + enum: + - allwinner,sun4i-a10-display-engine + - allwinner,sun5i-a10s-display-engine + - allwinner,sun5i-a13-display-engine + - allwinner,sun6i-a31-display-engine + - allwinner,sun6i-a31s-display-engine + - allwinner,sun7i-a20-display-engine + - allwinner,sun8i-a23-display-engine + - allwinner,sun8i-a33-display-engine + - allwinner,sun8i-a83t-display-engine + - allwinner,sun8i-h3-display-engine + - allwinner,sun8i-r40-display-engine + - allwinner,sun8i-v3s-display-engine + - allwinner,sun9i-a80-display-engine + - allwinner,sun50i-a64-display-engine + - allwinner,sun50i-h6-display-engine + + allwinner,pipelines: + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle-array + - minItems: 1 + maxItems: 2 + description: | + Available display engine frontends (DE 1.0) or mixers (DE + 2.0/3.0) available. + +required: + - compatible + - allwinner,pipelines + +additionalProperties: false + +if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-display-engine + - allwinner,sun6i-a31-display-engine + - allwinner,sun6i-a31s-display-engine + - allwinner,sun7i-a20-display-engine + - allwinner,sun8i-a83t-display-engine + - allwinner,sun8i-r40-display-engine + - allwinner,sun9i-a80-display-engine + - allwinner,sun50i-a64-display-engine + +then: + properties: + allwinner,pipelines: + minItems: 2 + +else: + properties: + allwinner,pipelines: + maxItems: 1 + +examples: + - | + de: display-engine { + compatible = "allwinner,sun4i-a10-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml new file mode 100644 index 000000000000..3eb1c2bbf4e7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Engine Frontend Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +description: | + The display engine frontend does formats conversion, scaling, + deinterlacing and color space conversion. + +properties: + compatible: + enum: + - allwinner,sun4i-a10-display-frontend + - allwinner,sun5i-a13-display-frontend + - allwinner,sun6i-a31-display-frontend + - allwinner,sun7i-a20-display-frontend + - allwinner,sun8i-a23-display-frontend + - allwinner,sun8i-a33-display-frontend + - allwinner,sun9i-a80-display-frontend + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The frontend interface clock + - description: The frontend module clock + - description: The frontend DRAM clock + + clock-names: + items: + - const: ahb + - const: mod + - const: ram + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnects: + maxItems: 1 + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnect-names: + const: dma-mem + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include + #include + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml new file mode 100644 index 000000000000..5d4915aed1e2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml @@ -0,0 +1,183 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 HDMI Controller Device Tree Bindings + +description: | + The HDMI Encoder supports the HDMI video and audio outputs, and does + CEC. It is one end of the pipeline. + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + compatible: + oneOf: + - const: allwinner,sun4i-a10-hdmi + - const: allwinner,sun5i-a10s-hdmi + - const: allwinner,sun6i-a31-hdmi + - items: + - const: allwinner,sun7i-a20-hdmi + - const: allwinner,sun5i-a10s-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + oneOf: + - items: + - description: The HDMI interface clock + - description: The HDMI module clock + - description: The first video PLL + - description: The second video PLL + + - items: + - description: The HDMI interface clock + - description: The HDMI module clock + - description: The HDMI DDC clock + - description: The first video PLL + - description: The second video PLL + + clock-names: + oneOf: + - items: + - const: ahb + - const: mod + - const: pll-0 + - const: pll-1 + + - items: + - const: ahb + - const: mod + - const: ddc + - const: pll-0 + - const: pll-1 + + resets: + maxItems: 1 + + dmas: + items: + - description: DDC Transmission DMA Channel + - description: DDC Reception DMA Channel + - description: Audio Transmission DMA Channel + + dma-names: + items: + - const: ddc-tx + - const: ddc-rx + - const: audio-tx + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. Usually an HDMI + connector. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-hdmi + +then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + + required: + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun4i-a10-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml new file mode 100644 index 000000000000..86ad617d2327 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -0,0 +1,676 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Timings Controller (TCON) Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +description: | + The TCON acts as a timing controller for RGB, LVDS and TV + interfaces. + +properties: + "#clock-cells": + const: 0 + + compatible: + oneOf: + - const: allwinner,sun4i-a10-tcon + - const: allwinner,sun5i-a13-tcon + - const: allwinner,sun6i-a31-tcon + - const: allwinner,sun6i-a31s-tcon + - const: allwinner,sun7i-a20-tcon + - const: allwinner,sun8i-a23-tcon + - const: allwinner,sun8i-a33-tcon + - const: allwinner,sun8i-a83t-tcon-lcd + - const: allwinner,sun8i-a83t-tcon-tv + - const: allwinner,sun8i-r40-tcon-tv + - const: allwinner,sun8i-v3s-tcon + - const: allwinner,sun9i-a80-tcon-lcd + - const: allwinner,sun9i-a80-tcon-tv + + - items: + - enum: + - allwinner,sun50i-a64-tcon-lcd + - const: allwinner,sun8i-a83t-tcon-lcd + + - items: + - enum: + - allwinner,sun8i-h3-tcon-tv + - allwinner,sun50i-a64-tcon-tv + - allwinner,sun50i-h6-tcon-tv + - const: allwinner,sun8i-a83t-tcon-tv + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + clock-output-names: + allOf: + - $ref: /schemas/types.yaml#/definitions/string-array + - maxItems: 1 + description: + Name of the LCD pixel clock created. + + dmas: + maxItems: 1 + + resets: + anyOf: + - items: + - description: TCON Reset Line + + - items: + - description: TCON Reset Line + - description: TCON LVDS Reset Line + + - items: + - description: TCON Reset Line + - description: TCON eDP Reset Line + + - items: + - description: TCON Reset Line + - description: TCON eDP Reset Line + - description: TCON LVDS Reset Line + + reset-names: + oneOf: + - const: lcd + + - items: + - const: lcd + - const: lvds + + - items: + - const: lcd + - const: edp + + - items: + - const: lcd + - const: edp + - const: lvds + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + patternProperties: + "^endpoint(@[0-9])$": + type: object + + properties: + allwinner,tcon-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + TCON can have 1 or 2 channels, usually with the + first channel being used for the panels interfaces + (RGB, LVDS, etc.), and the second being used for the + outputs that require another controller (TV Encoder, + HDMI, etc.). + + If that property is present, specifies the TCON + channel the endpoint is associated to. If that + property is not present, the endpoint number will be + used as the channel number. + + unevaluatedProperties: true + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-tcon + - allwinner,sun5i-a13-tcon + - allwinner,sun7i-a20-tcon + + then: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: ahb + - const: tcon-ch0 + - const: tcon-ch1 + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-tcon + - allwinner,sun6i-a31s-tcon + + then: + properties: + clocks: + minItems: 4 + + clock-names: + items: + - const: ahb + - const: tcon-ch0 + - const: tcon-ch1 + - const: lvds-alt + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a23-tcon + - allwinner,sun8i-a33-tcon + + then: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: ahb + - const: tcon-ch0 + - const: lvds-alt + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-tcon-lcd + - allwinner,sun8i-v3s-tcon + - allwinner,sun9i-a80-tcon-lcd + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: ahb + - const: tcon-ch0 + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-tcon-tv + - allwinner,sun8i-r40-tcon-tv + - allwinner,sun9i-a80-tcon-tv + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: ahb + - const: tcon-ch1 + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun5i-a13-tcon + - allwinner,sun6i-a31-tcon + - allwinner,sun6i-a31s-tcon + - allwinner,sun7i-a20-tcon + - allwinner,sun8i-a23-tcon + - allwinner,sun8i-a33-tcon + - allwinner,sun8i-v3s-tcon + - allwinner,sun9i-a80-tcon-lcd + - allwinner,sun4i-a10-tcon + - allwinner,sun8i-a83t-tcon-lcd + + then: + required: + - "#clock-cells" + - clock-output-names + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-tcon + - allwinner,sun6i-a31s-tcon + - allwinner,sun8i-a23-tcon + - allwinner,sun8i-a33-tcon + - allwinner,sun8i-a83t-tcon-lcd + + then: + properties: + resets: + minItems: 2 + + reset-names: + items: + - const: lcd + - const: lvds + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun9i-a80-tcon-lcd + + then: + properties: + resets: + minItems: 3 + + reset-names: + items: + - const: lcd + - const: edp + - const: lvds + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun9i-a80-tcon-tv + + then: + properties: + resets: + minItems: 2 + + reset-names: + items: + - const: lcd + - const: edp + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-tcon + - allwinner,sun5i-a13-tcon + - allwinner,sun6i-a31-tcon + - allwinner,sun6i-a31s-tcon + - allwinner,sun7i-a20-tcon + - allwinner,sun8i-a23-tcon + - allwinner,sun8i-a33-tcon + + then: + required: + - dmas + +examples: + - | + #include + + /* + * This comes from the clock/sun4i-a10-ccu.h and + * reset/sun4i-a10-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_AHB_LCD0 56 + #define CLK_TCON0_CH0 149 + #define CLK_TCON0_CH1 155 + #define RST_TCON0 11 + + lcd-controller@1c0c000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + #undef CLK_AHB_LCD0 + #undef CLK_TCON0_CH0 + #undef CLK_TCON0_CH1 + #undef RST_TCON0 + + - | + #include + + /* + * This comes from the clock/sun6i-a31-ccu.h and + * reset/sun6i-a31-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_PLL_MIPI 15 + #define CLK_AHB1_LCD0 47 + #define CLK_LCD0_CH0 127 + #define CLK_LCD0_CH1 129 + #define RST_AHB1_LCD0 27 + #define RST_AHB1_LVDS 41 + + lcd-controller@1c0c000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + dmas = <&dma 11>; + resets = <&ccu RST_AHB1_LCD0>, <&ccu RST_AHB1_LVDS>; + reset-names = "lcd", "lvds"; + clocks = <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_LCD0_CH0>, + <&ccu CLK_LCD0_CH1>, + <&ccu CLK_PLL_MIPI>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1", + "lvds-alt"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_out_tcon0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + #undef CLK_PLL_MIPI + #undef CLK_AHB1_LCD0 + #undef CLK_LCD0_CH0 + #undef CLK_LCD0_CH1 + #undef RST_AHB1_LCD0 + #undef RST_AHB1_LVDS + + - | + #include + + /* + * This comes from the clock/sun9i-a80-ccu.h and + * reset/sun9i-a80-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_BUS_LCD0 102 + #define CLK_LCD0 58 + #define RST_BUS_LCD0 22 + #define RST_BUS_EDP 24 + #define RST_BUS_LVDS 25 + + lcd-controller@3c00000 { + compatible = "allwinner,sun9i-a80-tcon-lcd"; + reg = <0x03c00000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; + clock-names = "ahb", "tcon-ch0"; + resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "edp", "lvds"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + #undef CLK_BUS_TCON0 + #undef CLK_TCON0 + #undef RST_BUS_TCON0 + #undef RST_BUS_EDP + #undef RST_BUS_LVDS + + - | + #include + + /* + * This comes from the clock/sun8i-a83t-ccu.h and + * reset/sun8i-a83t-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_BUS_TCON0 36 + #define CLK_TCON0 85 + #define RST_BUS_TCON0 22 + #define RST_BUS_LVDS 31 + + lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-a83t-tcon-lcd"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + #undef CLK_BUS_TCON0 + #undef CLK_TCON0 + #undef RST_BUS_TCON0 + #undef RST_BUS_LVDS + + - | + #include + + /* + * This comes from the clock/sun8i-r40-ccu.h and + * reset/sun8i-r40-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_BUS_TCON_TV0 73 + #define RST_BUS_TCON_TV0 49 + + tcon_tv0: lcd-controller@1c73000 { + compatible = "allwinner,sun8i-r40-tcon-tv"; + reg = <0x01c73000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV0>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + #undef CLK_BUS_TCON_TV0 + #undef RST_BUS_TCON_TV0 + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml new file mode 100644 index 000000000000..5d5d39665119 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tv-encoder.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 TV Encoder Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + compatible: + const: allwinner,sun4i-a10-tv-encoder + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + port: + type: object + description: + A port node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoint, usually coming from the + associated TCON. + +required: + - compatible + - reg + - clocks + - resets + - port + +additionalProperties: false + +examples: + - | + tve0: tv-encoder@1c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ahb_gates 34>; + resets = <&tcon_ch0_clk 0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_tve0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml new file mode 100644 index 000000000000..0c1ce55940e1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 Dynamic Range Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +description: | + The DRC (Dynamic Range Controller) allows to dynamically adjust + pixel brightness/contrast based on histogram measurements for LCD + content adaptive backlight control. + +properties: + compatible: + enum: + - allwinner,sun6i-a31-drc + - allwinner,sun6i-a31s-drc + - allwinner,sun8i-a23-drc + - allwinner,sun8i-a33-drc + - allwinner,sun9i-a80-drc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The DRC interface clock + - description: The DRC module clock + - description: The DRC DRAM clock + + clock-names: + items: + - const: ahb + - const: mod + - const: ram + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include + + #include + #include + + drc0: drc@1e70000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e70000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_DRAM_DRC0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + reg = <0>; + + drc0_in_be0: endpoint { + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + + drc0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_drc0>; + }; + }; + }; + }; + + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml new file mode 100644 index 000000000000..1dee641e3ea1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-de2-mixer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner Display Engine 2.0 Mixer Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + compatible: + enum: + - allwinner,sun8i-a83t-de2-mixer-0 + - allwinner,sun8i-a83t-de2-mixer-1 + - allwinner,sun8i-h3-de2-mixer-0 + - allwinner,sun8i-r40-de2-mixer-0 + - allwinner,sun8i-r40-de2-mixer-1 + - allwinner,sun8i-v3s-de2-mixer + - allwinner,sun50i-a64-de2-mixer-0 + - allwinner,sun50i-a64-de2-mixer-1 + - allwinner,sun50i-h6-de3-mixer-0 + + reg: + maxItems: 1 + + clocks: + items: + - description: The mixer interface clock + - description: The mixer module clock + + clock-names: + items: + - const: bus + - const: mod + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include + #include + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + + mixer0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_mixer0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml new file mode 100644 index 000000000000..4d6795690ac3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -0,0 +1,273 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller + IP with Allwinner\'s own PHY IP. It supports audio and video outputs + and CEC. + + These DT bindings follow the Synopsys DWC HDMI TX bindings defined + in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with + the following device-specific properties. + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#phy-cells": + const: 0 + + compatible: + oneOf: + - const: allwinner,sun8i-a83t-dw-hdmi + - const: allwinner,sun50i-h6-dw-hdmi + + - items: + - enum: + - allwinner,sun8i-h3-dw-hdmi + - allwinner,sun8i-r40-dw-hdmi + - allwinner,sun50i-a64-dw-hdmi + - const: allwinner,sun8i-a83t-dw-hdmi + + reg: + maxItems: 1 + + reg-io-width: + const: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 6 + items: + - description: Bus Clock + - description: Register Clock + - description: TMDS Clock + - description: HDMI CEC Clock + - description: HDCP Clock + - description: HDCP Bus Clock + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: iahb + - const: isfr + - const: tmds + - const: cec + - const: hdcp + - const: hdcp-bus + + resets: + minItems: 1 + maxItems: 2 + items: + - description: HDMI Controller Reset + - description: HDCP Reset + + reset-names: + minItems: 1 + maxItems: 2 + items: + - const: ctrl + - const: hdcp + + phys: + maxItems: 1 + description: + Phandle to the DWC HDMI PHY. + + phy-names: + const: phy + + hvcc-supply: + description: + The VCC power supply of the controller + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. Usually the associated + TCON. + + port@1: + type: object + description: | + Output endpoints of the controller. Usually an HDMI + connector. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - reg-io-width + - interrupts + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-h6-dw-hdmi + +then: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + +additionalProperties: false + +examples: + - | + #include + + /* + * This comes from the clock/sun8i-a83t-ccu.h and + * reset/sun8i-a83t-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + #define CLK_BUS_HDMI 39 + #define CLK_HDMI 93 + #define CLK_HDMI_SLOW 94 + #define RST_BUS_HDMI1 26 + + hdmi@1ee0000 { + compatible = "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "phy"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + /* Cleanup after ourselves */ + #undef CLK_BUS_HDMI + #undef CLK_HDMI + #undef CLK_HDMI_SLOW + + - | + #include + + /* + * This comes from the clock/sun50i-h6-ccu.h and + * reset/sun50i-h6-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + #define CLK_BUS_HDMI 126 + #define CLK_BUS_HDCP 137 + #define CLK_HDMI 123 + #define CLK_HDMI_SLOW 124 + #define CLK_HDMI_CEC 125 + #define CLK_HDCP 136 + #define RST_BUS_HDMI_SUB 57 + #define RST_BUS_HDCP 62 + + hdmi@6000000 { + compatible = "allwinner,sun50i-h6-dw-hdmi"; + reg = <0x06000000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, + <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; + clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", + "hdcp-bus"; + resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; + reset-names = "ctrl", "hdcp"; + phys = <&hdmi_phy>; + phy-names = "phy"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml new file mode 100644 index 000000000000..501cec16168c --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A83t HDMI PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - allwinner,sun8i-a83t-hdmi-phy + - allwinner,sun8i-h3-hdmi-phy + - allwinner,sun8i-r40-hdmi-phy + - allwinner,sun50i-a64-hdmi-phy + - allwinner,sun50i-h6-hdmi-phy + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Bus Clock + - description: Module Clock + - description: Parent of the PHY clock + - description: Second possible parent of the PHY clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: bus + - const: mod + - const: pll-0 + - const: pll-1 + + resets: + maxItems: 1 + + reset-names: + const: phy + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-r40-hdmi-phy + +then: + properties: + clocks: + minItems: 4 + + clock-names: + minItems: 4 + +else: + if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-h3-hdmi-phy + - allwinner,sun50i-a64-hdmi-phy + + then: + properties: + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + else: + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + +additionalProperties: false + +examples: + - | + #include + #include + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-a83t-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml new file mode 100644 index 000000000000..b98ca609824b --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -0,0 +1,382 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner R40 TCON TOP Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +description: | + TCON TOPs main purpose is to configure whole display pipeline. It + determines relationships between mixers and TCONs, selects source + TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV + encoder clock source and contains additional TV TCON and DSI gates. + + It allows display pipeline to be configured in very different ways: + + / LCD0/LVDS0 + / [0] TCON-LCD0 + | \ MIPI DSI + mixer0 | + \ / [1] TCON-LCD1 - LCD1/LVDS1 + TCON-TOP + / \ [2] TCON-TV0 [0] - TVE0/RGB + mixer1 | \ + | TCON-TOP - HDMI + | / + \ [3] TCON-TV1 [1] - TVE1/RGB + + Note that both TCON TOP references same physical unit. Both mixers + can be connected to any TCON. Not all TCON TOP variants support all + features. + +properties: + "#clock-cells": + const: 1 + + compatible: + enum: + - allwinner,sun8i-r40-tcon-top + - allwinner,sun50i-h6-tcon-top + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 6 + items: + - description: The TCON TOP interface clock + - description: The TCON TOP TV0 clock + - description: The TCON TOP TVE0 clock + - description: The TCON TOP TV1 clock + - description: The TCON TOP TVE1 clock + - description: The TCON TOP MIPI DSI clock + + clock-names: + minItems: 2 + maxItems: 6 + items: + - const: bus + - const: tcon-tv0 + - const: tve0 + - const: tcon-tv1 + - const: tve1 + - const: dsi + + clock-output-names: + minItems: 1 + maxItems: 3 + description: > + The first item is the name of the clock created for the TV0 + channel, the second item is the name of the TCON TV1 channel + clock and the third one is the name of the DSI channel clock. + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + All ports should have only one endpoint connected to + remote endpoint. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoint for Mixer 0 mux. + + port@1: + type: object + description: | + Output endpoint for Mixer 0 mux + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: true + + patternProperties: + "^endpoint@[0-9]$": + type: object + + properties: + reg: + description: | + ID of the target TCON + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + + additionalProperties: false + + port@2: + type: object + description: | + Input endpoint for Mixer 1 mux. + + port@3: + type: object + description: | + Output endpoint for Mixer 1 mux + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: true + + patternProperties: + "^endpoint@[0-9]$": + type: object + + properties: + reg: + description: | + ID of the target TCON + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + + additionalProperties: false + + port@4: + type: object + description: | + Input endpoint for HDMI mux. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: true + + patternProperties: + "^endpoint@[0-9]$": + type: object + + properties: + reg: + description: | + ID of the target TCON + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + + additionalProperties: false + + port@5: + type: object + description: | + Output endpoint for HDMI mux + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + - port@4 + - port@5 + + additionalProperties: false + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - resets + - ports + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-tcon-top + +then: + properties: + clocks: + maxItems: 2 + + clock-output-names: + maxItems: 1 + +else: + properties: + clocks: + minItems: 6 + + clock-output-names: + minItems: 3 + + ports: + required: + - port@2 + - port@3 + +examples: + - | + #include + + #include + #include + + tcon_top: tcon-top@1c70000 { + compatible = "allwinner,sun8i-r40-tcon-top"; + reg = <0x01c70000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>, + <&ccu CLK_TVE0>, + <&ccu CLK_TCON_TV1>, + <&ccu CLK_TVE1>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", + "tcon-tv0", + "tve0", + "tcon-tv1", + "tve1", + "dsi"; + clock-output-names = "tcon-top-tv0", + "tcon-top-tv1", + "tcon-top-dsi"; + resets = <&ccu RST_BUS_TCON_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon_top>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon_top>; + }; + }; + + tcon_top_mixer1_out: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_tv0_out_tcon_top>; + }; + + tcon_top_hdmi_in_tcon_tv1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_tv1_out_tcon_top>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml b/Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml new file mode 100644 index 000000000000..96de41d32b3e --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 Detail Enhancement Unit Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +description: | + The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, + can sharpen the display content in both luma and chroma channels. + +properties: + compatible: + const: allwinner,sun9i-a80-deu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The DEU interface clock + - description: The DEU module clock + - description: The DEU DRAM clock + + clock-names: + items: + - const: ahb + - const: mod + - const: ram + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include + + #include + #include + + deu0: deu@3300000 { + compatible = "allwinner,sun9i-a80-deu"; + reg = <0x03300000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DEU0>, + <&de_clocks CLK_IEP_DEU0>, + <&de_clocks CLK_DRAM_DEU0>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DEU0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + deu0_in: port@0 { + reg = <0>; + + deu0_in_fe0: endpoint { + remote-endpoint = <&fe0_out_deu0>; + }; + }; + + deu0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deu0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_deu0>; + }; + + deu0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_deu0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt deleted file mode 100644 index 31ab72cba3d4..000000000000 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ /dev/null @@ -1,637 +0,0 @@ -Allwinner A10 Display Pipeline -============================== - -The Allwinner A10 Display pipeline is composed of several components -that are going to be documented below: - -For all connections between components up to the TCONs in the display -pipeline, when there are multiple components of the same type at the -same depth, the local endpoint ID must be the same as the remote -component's index. For example, if the remote endpoint is Frontend 1, -then the local endpoint ID must be 1. - - Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0 - [1] -- -- [1] [1] -- -- [1] - \ / \ / - X X - / \ / \ - [0] -- -- [0] [0] -- -- [0] - Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1 - -For a two pipeline system such as the one depicted above, the lines -represent the connections between the components, while the numbers -within the square brackets corresponds to the ID of the local endpoint. - -The same rule also applies to DE 2.0 mixer-TCON connections: - - Mixer 0 [0] ----------- [0] TCON 0 - [1] ---- ---- [1] - \ / - X - / \ - [0] ---- ---- [0] - Mixer 1 [1] ----------- [1] TCON 1 - -HDMI Encoder ------------- - -The HDMI Encoder supports the HDMI video and audio outputs, and does -CEC. It is one end of the pipeline. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-hdmi - * allwinner,sun5i-a10s-hdmi - * allwinner,sun6i-a31-hdmi - - reg: base address and size of memory-mapped region - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the HDMI encoder - * ahb: the HDMI interface clock - * mod: the HDMI module clock - * ddc: the HDMI ddc clock (A31 only) - * pll-0: the first video PLL - * pll-1: the second video PLL - - clock-names: the clock names mentioned above - - resets: phandle to the reset control for the HDMI encoder (A31 only) - - dmas: phandles to the DMA channels used by the HDMI encoder - * ddc-tx: The channel for DDC transmission - * ddc-rx: The channel for DDC reception - * audio-tx: The channel used for audio transmission - - dma-names: the channel names mentioned above - - - ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. The second should be the - output, usually to an HDMI connector. - -DWC HDMI TX Encoder -------------------- - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with Allwinner's own PHY IP. It supports audio and video outputs and CEC. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - -Required properties: - - - compatible: value must be one of: - * "allwinner,sun8i-a83t-dw-hdmi" - * "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi" - * "allwinner,sun50i-h6-dw-hdmi" - - reg: base address and size of memory-mapped region - - reg-io-width: See dw_hdmi.txt. Shall be 1. - - interrupts: HDMI interrupt number - - clocks: phandles to the clocks feeding the HDMI encoder - * iahb: the HDMI bus clock - * isfr: the HDMI register clock - * tmds: TMDS clock - * cec: HDMI CEC clock (H6 only) - * hdcp: HDCP clock (H6 only) - * hdcp-bus: HDCP bus clock (H6 only) - - clock-names: the clock names mentioned above - - resets: - * ctrl: HDMI controller reset - * hdcp: HDCP reset (H6 only) - - reset-names: reset names mentioned above - - phys: phandle to the DWC HDMI PHY - - phy-names: must be "phy" - - - ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. The second should be the - output, usually to an HDMI connector. - -Optional properties: - - hvcc-supply: the VCC power supply of the controller - -DWC HDMI PHY ------------- - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-a83t-hdmi-phy - * allwinner,sun8i-h3-hdmi-phy - * allwinner,sun8i-r40-hdmi-phy - * allwinner,sun50i-a64-hdmi-phy - * allwinner,sun50i-h6-hdmi-phy - - reg: base address and size of memory-mapped region - - clocks: phandles to the clocks feeding the HDMI PHY - * bus: the HDMI PHY interface clock - * mod: the HDMI PHY module clock - - clock-names: the clock names mentioned above - - resets: phandle to the reset controller driving the PHY - - reset-names: must be "phy" - -H3, A64 and R40 HDMI PHY require additional clocks: - - pll-0: parent of phy clock - - pll-1: second possible phy clock parent (A64/R40 only) - -TV Encoder ----------- - -The TV Encoder supports the composite and VGA output. It is one end of -the pipeline. - -Required properties: - - compatible: value should be "allwinner,sun4i-a10-tv-encoder". - - reg: base address and size of memory-mapped region - - clocks: the clocks driving the TV encoder - - resets: phandle to the reset controller driving the encoder - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. - -TCON ----- - -The TCON acts as a timing controller for RGB, LVDS and TV interfaces. - -Required properties: - - compatible: value must be either: - * allwinner,sun4i-a10-tcon - * allwinner,sun5i-a13-tcon - * allwinner,sun6i-a31-tcon - * allwinner,sun6i-a31s-tcon - * allwinner,sun7i-a20-tcon - * allwinner,sun8i-a23-tcon - * allwinner,sun8i-a33-tcon - * allwinner,sun8i-a83t-tcon-lcd - * allwinner,sun8i-a83t-tcon-tv - * allwinner,sun8i-r40-tcon-tv - * allwinner,sun8i-v3s-tcon - * allwinner,sun9i-a80-tcon-lcd - * allwinner,sun9i-a80-tcon-tv - * "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd" - * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv" - * allwinner,sun50i-h6-tcon-tv, allwinner,sun8i-r40-tcon-tv - - reg: base address and size of memory-mapped region - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the TCON. - - 'ahb': the interface clocks - - 'tcon-ch0': The clock driving the TCON channel 0, if supported - - resets: phandles to the reset controllers driving the encoder - - "lcd": the reset line for the TCON - - "edp": the reset line for the eDP block (A80 only) - - - clock-names: the clock names mentioned above - - reset-names: the reset names mentioned above - - clock-output-names: Name of the pixel clock created, if TCON supports - channel 0. - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint, the second one the output - - The output may have multiple endpoints. TCON can have 1 or 2 channels, - usually with the first channel being used for the panels interfaces - (RGB, LVDS, etc.), and the second being used for the outputs that - require another controller (TV Encoder, HDMI, etc.). The endpoints - will take an extra property, allwinner,tcon-channel, to specify the - channel the endpoint is associated to. If that property is not - present, the endpoint number will be used as the channel number. - -For TCONs with channel 0, there is one more clock required: - - 'tcon-ch0': The clock driving the TCON channel 0 -For TCONs with channel 1, there is one more clock required: - - 'tcon-ch1': The clock driving the TCON channel 1 - -When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found -in A13, H3, H5 and V3s SoCs), you need one more reset line: - - 'lvds': The reset line driving the LVDS logic - -And on the A23, A31, A31s and A33, you need one more clock line: - - 'lvds-alt': An alternative clock source, separate from the TCON channel 0 - clock, that can be used to drive the LVDS clock - -TCON TOP --------- - -TCON TOPs main purpose is to configure whole display pipeline. It determines -relationships between mixers and TCONs, selects source TCON for HDMI, muxes -LCD and TV encoder GPIO output, selects TV encoder clock source and contains -additional TV TCON and DSI gates. - -It allows display pipeline to be configured in very different ways: - - / LCD0/LVDS0 - / [0] TCON-LCD0 - | \ MIPI DSI - mixer0 | - \ / [1] TCON-LCD1 - LCD1/LVDS1 - TCON-TOP - / \ [2] TCON-TV0 [0] - TVE0/RGB - mixer1 | \ - | TCON-TOP - HDMI - | / - \ [3] TCON-TV1 [1] - TVE1/RGB - -Note that both TCON TOP references same physical unit. Both mixers can be -connected to any TCON. Not all TCON TOP variants support all features. - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-r40-tcon-top - * allwinner,sun50i-h6-tcon-top - - reg: base address and size of the memory-mapped region. - - clocks: phandle to the clocks feeding the TCON TOP - * bus: TCON TOP interface clock - * tcon-tv0: TCON TV0 clock - * tve0: TVE0 clock (R40 only) - * tcon-tv1: TCON TV1 clock (R40 only) - * tve1: TVE0 clock (R40 only) - * dsi: MIPI DSI clock (R40 only) - - clock-names: clock name mentioned above - - resets: phandle to the reset line driving the TCON TOP - - #clock-cells : must contain 1 - - clock-output-names: Names of clocks created for TCON TV0 channel clock, - TCON TV1 channel clock (R40 only) and DSI channel clock (R40 only), in - that order. - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should - be defined: - * port 0 is input for mixer0 mux - * port 1 is output for mixer0 mux - * port 2 is input for mixer1 mux - * port 3 is output for mixer1 mux - * port 4 is input for HDMI mux - * port 5 is output for HDMI mux - All output endpoints for mixer muxes and input endpoints for HDMI mux should - have reg property with the id of the target TCON, as shown in above graph - (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one - endpoint connected to remote endpoint. - -DRC ---- - -The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs -(A31, A23, A33, A80), allows to dynamically adjust pixel -brightness/contrast based on histogram measurements for LCD content -adaptive backlight control. - - -Required properties: - - compatible: value must be one of: - * allwinner,sun6i-a31-drc - * allwinner,sun6i-a31s-drc - * allwinner,sun8i-a23-drc - * allwinner,sun8i-a33-drc - * allwinner,sun9i-a80-drc - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the DRC - * ahb: the DRC interface clock - * mod: the DRC module clock - * ram: the DRC DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset line driving the DRC - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine Backend ----------------------- - -The display engine backend exposes layers and sprites to the -system. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-backend - * allwinner,sun5i-a13-display-backend - * allwinner,sun6i-a31-display-backend - * allwinner,sun7i-a20-display-backend - * allwinner,sun8i-a23-display-backend - * allwinner,sun8i-a33-display-backend - * allwinner,sun9i-a80-display-backend - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the frontend and backend - * ahb: the backend interface clock - * mod: the backend module clock - * ram: the backend DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the backend - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the output - -On the A33, some additional properties are required: - - reg needs to have an additional region corresponding to the SAT - - reg-names need to be set, with "be" and "sat" - - clocks and clock-names need to have a phandle to the SAT bus - clocks, whose name will be "sat" - - resets and reset-names need to have a phandle to the SAT bus - resets, whose name will be "sat" - -DEU ---- - -The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, -can sharpen the display content in both luma and chroma channels. - -Required properties: - - compatible: value must be one of: - * allwinner,sun9i-a80-deu - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the DEU - * ahb: the DEU interface clock - * mod: the DEU module clock - * ram: the DEU DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset line driving the DEU - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine Frontend ------------------------ - -The display engine frontend does formats conversion, scaling, -deinterlacing and color space conversion. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-frontend - * allwinner,sun5i-a13-display-frontend - * allwinner,sun6i-a31-display-frontend - * allwinner,sun7i-a20-display-frontend - * allwinner,sun8i-a23-display-frontend - * allwinner,sun8i-a33-display-frontend - * allwinner,sun9i-a80-display-frontend - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the frontend and backend - * ahb: the backend interface clock - * mod: the backend module clock - * ram: the backend DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the backend - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine 2.0 Mixer ------------------------- - -The DE2 mixer have many functionalities, currently only layer blending is -supported. - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-a83t-de2-mixer-0 - * allwinner,sun8i-a83t-de2-mixer-1 - * allwinner,sun8i-h3-de2-mixer-0 - * allwinner,sun8i-r40-de2-mixer-0 - * allwinner,sun8i-r40-de2-mixer-1 - * allwinner,sun8i-v3s-de2-mixer - * allwinner,sun50i-a64-de2-mixer-0 - * allwinner,sun50i-a64-de2-mixer-1 - * allwinner,sun50i-h6-de3-mixer-0 - - reg: base address and size of the memory-mapped region. - - clocks: phandles to the clocks feeding the mixer - * bus: the mixer interface clock - * mod: the mixer module clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the mixer - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the output - - -Display Engine Pipeline ------------------------ - -The display engine pipeline (and its entry point, since it can be -either directly the backend or the frontend) is represented as an -extra node. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-engine - * allwinner,sun5i-a10s-display-engine - * allwinner,sun5i-a13-display-engine - * allwinner,sun6i-a31-display-engine - * allwinner,sun6i-a31s-display-engine - * allwinner,sun7i-a20-display-engine - * allwinner,sun8i-a23-display-engine - * allwinner,sun8i-a33-display-engine - * allwinner,sun8i-a83t-display-engine - * allwinner,sun8i-h3-display-engine - * allwinner,sun8i-r40-display-engine - * allwinner,sun8i-v3s-display-engine - * allwinner,sun9i-a80-display-engine - * allwinner,sun50i-a64-display-engine - * allwinner,sun50i-h6-display-engine - - - allwinner,pipelines: list of phandle to the display engine - frontends (DE 1.0) or mixers (DE 2.0/3.0) available. - -Example: - -panel: panel { - compatible = "olimex,lcd-olinuxino-43-ts"; - #address-cells = <1>; - #size-cells = <0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; -}; - -connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; -}; - -hdmi: hdmi@1c16000 { - compatible = "allwinner,sun5i-a10s-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_hdmi>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - }; -}; - -tve0: tv-encoder@1c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ahb_gates 34>; - resets = <&tcon_ch0_clk 0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tve0_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_tve0>; - }; - }; -}; - -tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&tcon_ch0_clk 1>; - reset-names = "lcd"; - clocks = <&ahb_gates 36>, - <&tcon_ch0_clk>, - <&tcon_ch1_clk>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - }; - }; - }; -}; - -fe0: display-frontend@1e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ahb_gates 46>, <&de_fe_clk>, - <&dram_gates 25>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_fe_clk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint { - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; -}; - -be0: display-backend@1e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ahb_gates 44>, <&de_be_clk>, - <&dram_gates 26>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_be_clk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; -}; - -display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; -}; -- cgit v1.2.3 From 923eb18667ab3c8e875c7915716736005bb705ff Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 9 Jan 2020 19:40:36 +0100 Subject: dt-bindings: display: simple: Add Satoz panel Satoz is a Chinese TFT manufacturer. Website: http://www.sat-sz.com/English/index.html Add the compatible for its SAT050AT40H12R2 5.0 inch LCD panel. Signed-off-by: Miquel Raynal Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20200109184037.9091-1-miquel.raynal@bootlin.com --- Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 6c098a0b6e1e..8fe60ee2531c 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -39,6 +39,8 @@ properties: - boe,nv140fhmn49 # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel - giantplus,gpm940b0 + # Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel + - satoz,sat050at40h12r2 # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel - sharp,ls020b1dd01d -- cgit v1.2.3 From 57d6c2eb735a0e08d7e0bbd985ec3ebc5fcaf214 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 7 Jan 2020 16:28:41 -0800 Subject: dt-bindings: drm/msm/gpu: Document firmware-name The firmware-name property in the zap node can be used to specify a device specific zap firmware. Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/display/msm/gpu.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 3e6cd3f64a78..7edc298a15f2 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -33,6 +33,8 @@ Required properties: - zap-shader: For a5xx and a6xx devices this node contains a memory-region that points to reserved memory to store the zap shader that can be used to help bring the GPU out of secure mode. +- firmware-name: optional property of the 'zap-shader' node, listing the + relative path of the device specific zap firmware. Example 3xx/4xx/a5xx: @@ -85,6 +87,7 @@ Example a6xx (with GMU): zap-shader { memory-region = <&zap_shader_region>; + firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn" }; }; }; -- cgit v1.2.3