From fc32ca1ea6f74c1be7abf9d21b0bac8bce11bec3 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Tue, 21 Dec 2021 11:00:14 +0800 Subject: dt-bindings: arm: amlogic: add S4 based AQ222 bindings Add bindings for the new Amlogic S4 SoC family, and add binds the compatible for the Amlogic S4 Based AQ222 board. S4 is an application processor designed for hybrid OTT/IP Set To Box(STB) and high-end media box applications, with quad core Cortex-A35. Signed-off-by: Xianwei Zhao Acked-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211221030014.434-1-xianwei.zhao@amlogic.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 36081734f720..31df120d73b0 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -183,6 +183,12 @@ properties: - amlogic,ad401 - const: amlogic,a1 + - description: Boards with the Amlogic Meson S4 S805X2 SoC + items: + - enum: + - amlogic,aq222 + - const: amlogic,s4 + additionalProperties: true ... -- cgit v1.2.3 From d2ecf5ae59c8eef9fe2ad20d83977c2889646d4c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:06 +0000 Subject: dt-bindings: arm: amlogic: add X96-AIR bindings Add board bindings for the Amediatech X96-AIR STB which ships with model variants distiguished by Ethernet configuration: models using an external Gigabit PHY have a -gbit suffix, while models using an internal 10/100 PHY have no suffix. Signed-off-by: Christian Hewitt Acked-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-3-christianshewitt@gmail.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 31df120d73b0..b5b995941d3b 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -170,6 +170,8 @@ properties: - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC items: - enum: + - amediatech,x96-air + - amediatech,x96-air-gbit - bananapi,bpi-m5 - hardkernel,odroid-c4 - hardkernel,odroid-hc4 -- cgit v1.2.3 From 3dbabb9ac746ab01c71aa019c58a2e0cc6eafe1c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:08 +0000 Subject: dt-bindings: vendor-prefixes: add cyx prefix Shenzhen CYX Industrial Co., Ltd are a manufacturer of Android Set-Top Box devices. Signed-off-by: Christian Hewitt Acked-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-5-christianshewitt@gmail.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd781..f1b4afb2876a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -279,6 +279,8 @@ patternProperties: description: CUI Devices "^cypress,.*": description: Cypress Semiconductor Corporation + "^cyx,.*": + description: Shenzhen CYX Industrial Co., Ltd "^cznic,.*": description: CZ.NIC, z.s.p.o. "^dallas,.*": -- cgit v1.2.3 From bc7811bd4e884bbc21cc7b7031cb7c297662db9c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:09 +0000 Subject: dt-bindings: arm: amlogic: add A95XF3-AIR bindings Add board bindings for the CYX A95XF3-AIR set-top box which ships with model variants distinguished by Ethernet configuration: models using external Gigabit PHY have a -gbit suffix, while models using an internal 10/100 PHY have no suffix. Signed-off-by: Christian Hewitt Acked-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-6-christianshewitt@gmail.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index b5b995941d3b..2027ce81a834 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -173,6 +173,8 @@ properties: - amediatech,x96-air - amediatech,x96-air-gbit - bananapi,bpi-m5 + - cyx,a95xf3-air + - cyx,a95xf3-air-gbit - hardkernel,odroid-c4 - hardkernel,odroid-hc4 - khadas,vim3l -- cgit v1.2.3 From bf510ace20ac153946d6d0ab6305dd8aa52eec6c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:11 +0000 Subject: dt-bindings: vendor-prefixes: add haochuangyi prefix Shenzhen Haochuangyi Technology Co.,Ltd are a manufacturer of Android Set-Top Box devices. Signed-off-by: Christian Hewitt Acked-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-8-christianshewitt@gmail.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f1b4afb2876a..52ff63248892 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -483,6 +483,8 @@ patternProperties: deprecated: true "^hannstar,.*": description: HannStar Display Corporation + "^haochuangyi,.*": + description: Shenzhen Haochuangyi Technology Co.,Ltd "^haoyu,.*": description: Haoyu Microelectronic Co. Ltd. "^hardkernel,.*": -- cgit v1.2.3 From 2ca889b1201625d36efcd51d25371d937a6a0b8f Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:12 +0000 Subject: dt-bindings: arm: amlogic: add H96-Max bindings Add the board binding for the Haochuangyi H96-Max STB device. Signed-off-by: Christian Hewitt Acked-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-9-christianshewitt@gmail.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 2027ce81a834..a073a959232c 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -177,6 +177,7 @@ properties: - cyx,a95xf3-air-gbit - hardkernel,odroid-c4 - hardkernel,odroid-hc4 + - haochuangyi,h96-max - khadas,vim3l - seirobotics,sei610 - const: amlogic,sm1 -- cgit v1.2.3 From af030d83da1dc0d750d7bcc88d57dd1cae5f6b61 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:18 +0100 Subject: dt-bindings: pinctrl: samsung: convert to dtschema Convert the Samsung SoC (S3C24xx, S3C64xx, S5Pv210, Exynos) pin controller bindings to DT schema format. Parts of description and DTS example was copied from existing sources, so keep the license as GPL-2.0-only. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20220111201722.327219-18-krzysztof.kozlowski@canonical.com --- .../pinctrl/samsung,pinctrl-gpio-bank.yaml | 52 +++ .../bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml | 81 +++++ .../pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 85 +++++ .../bindings/pinctrl/samsung,pinctrl.yaml | 392 +++++++++++++++++++++ .../bindings/pinctrl/samsung-pinctrl.txt | 383 -------------------- MAINTAINERS | 2 +- 6 files changed, 611 insertions(+), 384 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml new file mode 100644 index 000000000000..f73348c54748 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank + +maintainers: + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller. + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + '#gpio-cells': + const: 2 + + gpio-controller: true + + '#interrupt-cells': + description: + For GPIO banks supporting external GPIO interrupts or external wake-up + interrupts. + const: 2 + + interrupt-controller: + description: + For GPIO banks supporting external GPIO interrupts or external wake-up + interrupts. + + interrupts: + description: + For GPIO banks supporting direct external wake-up interrupts (without + multiplexing). Number of interrupts must match number of wake-up capable + pins of this bank. + minItems: 1 + maxItems: 8 + +required: + - '#gpio-cells' + - gpio-controller + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml new file mode 100644 index 000000000000..c71939ac8b63 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration + +maintainers: + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller. + + The values used for config properties should be derived from the hardware + manual and these values are programmed as-is into the pin pull up/down and + driver strength register of the pin-controller. + See also include/dt-bindings/pinctrl/samsung.h with useful constants. + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + samsung,pins: + description: | + List of pins to configure. For initial and sleep states, the maximum + number is one pin. In other cases there is no upper limit. + + The pins should use lowercase names matching hardware manual, e.g. for + GPA0 bank: gpa0-0, gpa0-1, gpa0-2. + $ref: /schemas/types.yaml#/definitions/string-array + + samsung,pin-function: + description: | + The pin function selection that should be applied on the pins listed in the + child node is specified using the "samsung,pin-function" property. The value + of this property that should be applied to each of the pins listed in the + "samsung,pins" property should be picked from the hardware manual of the SoC + for the specified pin group. This property is optional in the child node if + no specific function selection is desired for the pins listed in the child + node. The value of this property is used as-is to program the pin-controller + function selector register of the pin-bank. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + samsung,pin-drv: + description: Drive strength configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + samsung,pin-pud: + description: Pull up/down configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + samsung,pin-val: + description: Initial value of pin output buffer. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + samsung,pin-con-pdn: + description: Function in power down mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + samsung,pin-pud-pdn: + description: Pull up/down configuration in power down mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + +required: + - samsung,pins + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml new file mode 100644 index 000000000000..6b684a53119b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller + +maintainers: + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller. + Only one pin-controller device node can include external wake-up interrupts + child node (in other words, only one External wake-up interrupts + pin-controller is supported). + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s3c2410-wakeup-eint + - samsung,s3c2412-wakeup-eint + - samsung,s3c64xx-wakeup-eint + - samsung,s5pv210-wakeup-eint + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + + interrupts: + description: + Interrupt used by multiplexed external wake-up interrupts. + minItems: 1 + maxItems: 6 + +required: + - compatible + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,s3c2410-wakeup-eint + - samsung,s3c2412-wakeup-eint + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + const: samsung,s3c64xx-wakeup-eint + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + + - if: + properties: + compatible: + contains: + enum: + - samsung,s5pv210-wakeup-eint + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + then: + properties: + interrupts: + minItems: 1 + maxItems: 1 + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml new file mode 100644 index 000000000000..28f0851d07bb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -0,0 +1,392 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller + +maintainers: + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + Pin group settings (like drive strength, pull up/down) are available as + macros in include/dt-bindings/pinctrl/samsung.h. + + All the pin controller nodes should be represented in the aliases node using + the following format 'pinctrl{n}' where n is a unique number for the alias. + + The controller supports three types of interrupts:: + - External GPIO interrupts (see interrupts property in pin controller node); + + - External wake-up interrupts - multiplexed (capable of waking up the system + see interrupts property in external wake-up interrupt controller node - + samsung,pinctrl-wakeup-interrupt.yaml); + + - External wake-up interrupts - direct (capable of waking up the system, see + interrupts property in every bank of pin controller with external wake-up + interrupt controller - samsung,pinctrl-gpio-bank.yaml). + +properties: + $nodename: + pattern: "^pinctrl(@.*)?" + + compatible: + enum: + - samsung,s3c2412-pinctrl + - samsung,s3c2416-pinctrl + - samsung,s3c2440-pinctrl + - samsung,s3c2450-pinctrl + - samsung,s3c64xx-pinctrl + - samsung,s5pv210-pinctrl + - samsung,exynos3250-pinctrl + - samsung,exynos4210-pinctrl + - samsung,exynos4x12-pinctrl + - samsung,exynos5250-pinctrl + - samsung,exynos5260-pinctrl + - samsung,exynos5410-pinctrl + - samsung,exynos5420-pinctrl + - samsung,exynos5433-pinctrl + - samsung,exynos7-pinctrl + - samsung,exynos7885-pinctrl + - samsung,exynos850-pinctrl + - samsung,exynosautov9-pinctrl + + interrupts: + description: + Required for GPIO banks supporting external GPIO interrupts. + maxItems: 1 + + power-domains: + maxItems: 1 + + reg: + description: + Second base address of the pin controller if the specific registers of + the pin controller are separated into the different base address. + Only certain banks of certain pin controller might need it. + minItems: 1 + maxItems: 2 + + wakeup-interrupt-controller: + $ref: samsung,pinctrl-wakeup-interrupt.yaml + +patternProperties: + "^[a-z]+[0-9]*-gpio-bank$": + description: + Pin banks of the controller are represented by child nodes of the + controller node. Bank name is taken from name of the node. + $ref: samsung,pinctrl-gpio-bank.yaml + + "^[a-z0-9-]+-pins$": + oneOf: + - $ref: samsung,pinctrl-pins-cfg.yaml + required: + - samsung,pins + - type: object + patternProperties: + "^[a-z0-9-]+-pins$": + $ref: samsung,pinctrl-pins-cfg.yaml + + additionalProperties: false + + "^(initial|sleep)-state$": + patternProperties: + "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$": + $ref: samsung,pinctrl-pins-cfg.yaml + + properties: + samsung,pins: + description: See samsung,pinctrl-pins-cfg.yaml + $ref: /schemas/types.yaml#/definitions/string-array + maxItems: 1 + + required: + - samsung,pins + + unevaluatedProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: "pinctrl.yaml#" + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-pinctrl + then: + properties: + reg: + minItems: 1 + maxItems: 2 + else: + properties: + reg: + minItems: 1 + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + + pinctrl@7f008000 { + compatible = "samsung,s3c64xx-pinctrl"; + reg = <0x7f008000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <21>; + + wakeup-interrupt-controller { + compatible = "samsung,s3c64xx-wakeup-eint"; + interrupts-extended = <&vic0 0>, + <&vic0 1>, + <&vic1 0>, + <&vic1 1>; + }; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpa-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + uart0-data-pins { + samsung,pins = "gpa-0", "gpa-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + // ... + }; + + - | + #include + #include + + pinctrl@11400000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + // ... + + sleep0: sleep-state { + gpa0-0-pin { + samsung,pins = "gpa0-0"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-1-pin { + samsung,pins = "gpa0-1"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + // ... + }; + }; + + - | + #include + #include + + pinctrl@11000000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpj0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* Pin bank without external interrupts */ + gpy0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + /* Pin bank with external direct wake-up interrupts */ + gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + // ... + + sd0-clk-pins { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4-bus-width8-pins { + part-1-pins { + samsung,pins = "gpk0-3", "gpk0-4", + "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + part-2-pins { + samsung,pins = "gpk1-3", "gpk1-4", + "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + }; + + // ... + + otg-gp-pins { + samsung,pins = "gpx3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + }; + + - | + #include + #include + + pinctrl@10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1a20>, <0x11090000 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&initial_alive>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = ; + }; + + /* Pin bank with external direct wake-up interrupts */ + gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + // ... + + te-irq-pins { + samsung,pins = "gpf1-3"; + samsung,pin-function = <0xf>; + }; + + // .. + + initial_alive: initial-state { + gpa0-0-pin { + samsung,pins = "gpa0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + // ... + }; + }; + + - | + #include + #include + + pinctrl@114b0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x114b0000 0x1000>; + interrupts = ; + power-domains = <&pd_aud>; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpz0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + i2s0-bus-pins { + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", + "gpz0-4", "gpz0-5", "gpz0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + // ... + }; diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt deleted file mode 100644 index 9e70edceb21b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ /dev/null @@ -1,383 +0,0 @@ -Samsung GPIO and Pin Mux/Config controller - -Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware -controller. It controls the input/output settings on the available pads/pins -and also provides ability to multiplex and configure the output of various -on-chip controllers onto these pads. - -Required Properties: -- compatible: should be one of the following. - - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, - - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, - - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, - - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, - - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, - - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, - - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. - - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. - - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. - - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. - - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. - - "samsung,exynos7885-pinctrl": for Exynos7885 compatible pin-controller. - - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller. - -- reg: Base address of the pin controller hardware module and length of - the address space it occupies. - - - reg: Second base address of the pin controller if the specific registers - of the pin controller are separated into the different base address. - - Eg: GPF[1-5] of Exynos5433 are separated into the two base address. - - First base address is for GPAx and GPF[1-5] external interrupt - registers. - - Second base address is for GPF[1-5] pinctrl registers. - - pinctrl_0: pinctrl@10580000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x10580000 0x1a20>, <0x11090000 0x100>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; - interrupts = <0 16 0>; - }; - }; - -- Pin banks as child nodes: Pin banks of the controller are represented by child - nodes of the controller node. Bank name is taken from name of the node. Each - bank node must contain following properties: - - - gpio-controller: identifies the node as a gpio controller and pin bank. - - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. - - Eg: <&gpx2 6 0> - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [flags]> - - Values for gpio specifier: - - Pin number: is a value between 0 to 7. - - Flags: 0 - Active High - 1 - Active Low - -- Pin mux/config groups as child nodes: The pin mux (selecting pin function - mode) and pin config (pull up/down, driver strength) settings are represented - as child nodes of the pin-controller node. There should be at least one - child node and there is no limit on the count of these child nodes. It is - also possible for a child node to consist of several further child nodes - to allow grouping multiple pinctrl groups into one. The format of second - level child nodes is exactly the same as for first level ones and is - described below. - - The child node should contain a list of pin(s) on which a particular pin - function selection or pin configuration (or both) have to applied. This - list of pins is specified using the property name "samsung,pins". There - should be at least one pin specified for this property and there is no upper - limit on the count of pins that can be specified. The pins are specified - using pin names which are derived from the hardware manual of the SoC. As - an example, the pins in GPA0 bank of the pin controller can be represented - as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. - The format of the pin names should be (as per the hardware manual) - "[pin bank name]-[pin number within the bank]". - - The pin function selection that should be applied on the pins listed in the - child node is specified using the "samsung,pin-function" property. The value - of this property that should be applied to each of the pins listed in the - "samsung,pins" property should be picked from the hardware manual of the SoC - for the specified pin group. This property is optional in the child node if - no specific function selection is desired for the pins listed in the child - node. The value of this property is used as-is to program the pin-controller - function selector register of the pin-bank. - - The child node can also optionally specify one or more of the pin - configuration that should be applied on all the pins listed in the - "samsung,pins" property of the child node. The following pin configuration - properties are supported. - - - samsung,pin-val: Initial value of pin output buffer. - - samsung,pin-pud: Pull up/down configuration. - - samsung,pin-drv: Drive strength configuration. - - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. - - samsung,pin-drv-pdn: Drive strength configuration in power down mode. - - The values specified by these config properties should be derived from the - hardware manual and these values are programmed as-is into the pin - pull up/down and driver strength register of the pin-controller. - - Note: A child should include at least a pin function selection property or - pin configuration property (one or more) or both. - - The client nodes that require a particular pin function selection and/or - pin configuration should use the bindings listed in the "pinctrl-bindings.txt" - file. - -External GPIO and Wakeup Interrupts: - -The controller supports two types of external interrupts over gpio. The first -is the external gpio interrupt and second is the external wakeup interrupts. -The difference between the two is that the external wakeup interrupts can be -used as system wakeup events. - -A. External GPIO Interrupts: For supporting external gpio interrupts, the - following properties should be specified in the pin-controller device node. - - - interrupts: interrupt specifier for the controller. The format and value of - the interrupt specifier depends on the interrupt parent for the controller. - - In addition, following properties must be present in node of every bank - of pins supporting GPIO interrupts: - - - interrupt-controller: identifies the controller node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2. - - First Cell: represents the external gpio interrupt number local to the - external gpio interrupt space of the controller. - - Second Cell: flags to identify the type of the interrupt - - 1 = rising edge triggered - - 2 = falling edge triggered - - 3 = rising and falling edge triggered - - 4 = high level triggered - - 8 = low level triggered - -B. External Wakeup Interrupts: For supporting external wakeup interrupts, a - child node representing the external wakeup interrupt controller should be - included in the pin-controller device node. - - Only one pin-controller device node can include external wakeup interrupts - child node (in other words, only one External Wakeup Interrupts - pin-controller is supported). - - This child node should include following properties: - - - compatible: identifies the type of the external wakeup interrupt controller - The possible values are: - - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C24xx SoCs except S3C2412 and S3C2413, - - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C2412 and S3C2413 SoCs, - - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C64xx SoCs, - - samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller - found on Samsung S5Pv210 SoCs, - - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller - found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. - - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller - found on Samsung Exynos7 SoC. - - interrupts: interrupt used by multiplexed wakeup interrupts. - - In addition, following properties must be present in node of every bank - of pins supporting wake-up interrupts: - - - interrupt-controller: identifies the node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2 - - First Cell: represents the external wakeup interrupt number local to - the external wakeup interrupt space of the controller. - - Second Cell: flags to identify the type of the interrupt - - 1 = rising edge triggered - - 2 = falling edge triggered - - 3 = rising and falling edge triggered - - 4 = high level triggered - - 8 = low level triggered - - Node of every bank of pins supporting direct wake-up interrupts (without - multiplexing) must contain following properties: - - - interrupts: interrupts of the interrupt parent which are used for external - wakeup interrupts from pins of the bank, must contain interrupts for all - pins of the bank. - -Aliases: - -All the pin controller nodes should be represented in the aliases node using -the following format 'pinctrl{n}' where n is a unique number for the alias. - -Aliases for controllers compatible with "samsung,exynos7-pinctrl": -- pinctrl0: pin controller of ALIVE block, -- pinctrl1: pin controller of BUS0 block, -- pinctrl2: pin controller of NFC block, -- pinctrl3: pin controller of TOUCH block, -- pinctrl4: pin controller of FF block, -- pinctrl5: pin controller of ESE block, -- pinctrl6: pin controller of FSYS0 block, -- pinctrl7: pin controller of FSYS1 block, -- pinctrl8: pin controller of BUS1 block, -- pinctrl9: pin controller of AUDIO block, - -Example: A pin-controller node with pin banks: - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; - - /* ... */ - - /* Pin bank without external interrupts */ - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - /* ... */ - - /* Pin bank with external GPIO or muxed wake-up interrupts */ - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* ... */ - - /* Pin bank with external direct wake-up interrupts */ - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; - #interrupt-cells = <2>; - }; - - /* ... */ - }; - -Example 1: A pin-controller node with pin groups. - - #include - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; - - /* ... */ - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - part-1 { - samsung,pins = "gpk0-3", "gpk0-4", - "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - part-2 { - samsung,pins = "gpk1-3", "gpk1-4", - "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - }; - -Example 2: A pin-controller node with external wakeup interrupt controller node. - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 46 0> - - /* ... */ - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - -Example 3: A uart client node that supports 'default' and 'flow-control' states. - - uart@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 52 0>; - pinctrl-names = "default", "flow-control; - pinctrl-0 = <&uart0_data>; - pinctrl-1 = <&uart0_data>, <&uart0_fctl>; - }; - -Example 4: Set up the default pin state for uart controller. - - static int s3c24xx_serial_probe(struct platform_device *pdev) { - struct pinctrl *pinctrl; - - /* ... */ - - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - } - -Example 5: A display port client node that supports 'default' pinctrl state - and gpio binding. - - display-port-controller { - /* ... */ - - samsung,hpd-gpio = <&gpx2 6 0>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - }; - -Example 6: Request the gpio for display port controller - - static int exynos_dp_probe(struct platform_device *pdev) - { - int hpd_gpio, ret; - struct device *dev = &pdev->dev; - struct device_node *dp_node = dev->of_node; - - /* ... */ - - hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0); - - /* ... */ - - ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN, - "hpd_gpio"); - /* ... */ - } diff --git a/MAINTAINERS b/MAINTAINERS index ea3e6c914384..89f23af16451 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15285,7 +15285,7 @@ L: linux-samsung-soc@vger.kernel.org S: Maintained Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git -F: Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +F: Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml F: drivers/pinctrl/samsung/ F: include/dt-bindings/pinctrl/samsung.h -- cgit v1.2.3 From 1755e227c21636ade047dc9b920f647c1d53b4e9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:19 +0100 Subject: dt-bindings: pinctrl: samsung: describe Exynos850 and ExynosAutov9 wake-ups Older Samsung Exynos SoCs (Exynos3250, Exynos4, Exynos5, Exynos5433) expected pin controller node with external wake-up interrupts to have one interrupt for multiplexing these wake-up interrupts. Also they expected to have exactly one such pin controller (capable of external wake-up interrupts). It seems however that newer ARMv8 Exynos SoCs like Exynos850 and ExynosAutov9 have differences of their pin controllers capable of external wake-up interrupts: 1. No multiplexed external wake-up interrupt, only direct, 2. More than one pin controller capable of external wake-up interrupts. Add dedicated Exynos850 and ExynosAutov9 compatibles. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220111201722.327219-19-krzysztof.kozlowski@canonical.com --- .../pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 27 +++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 6b684a53119b..a822f70f5702 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -16,9 +16,12 @@ description: | controller. External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller. - Only one pin-controller device node can include external wake-up interrupts - child node (in other words, only one External wake-up interrupts + For S3C24xx, S3C64xx, S5PV210 and Exynos4210 compatible wake-up interrupt + controllers, only one pin-controller device node can include external wake-up + interrupts child node (in other words, only one External wake-up interrupts pin-controller is supported). + For newer controllers, multiple pin-controller device node can include + external wake-up interrupts child node. See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for additional information and example. @@ -32,6 +35,8 @@ properties: - samsung,s5pv210-wakeup-eint - samsung,exynos4210-wakeup-eint - samsung,exynos7-wakeup-eint + - samsung,exynos850-wakeup-eint + - samsung,exynosautov9-wakeup-eint interrupts: description: @@ -41,7 +46,6 @@ properties: required: - compatible - - interrupts allOf: - if: @@ -56,6 +60,8 @@ allOf: interrupts: minItems: 6 maxItems: 6 + required: + - interrupts - if: properties: @@ -67,6 +73,8 @@ allOf: interrupts: minItems: 4 maxItems: 4 + required: + - interrupts - if: properties: @@ -81,5 +89,18 @@ allOf: interrupts: minItems: 1 maxItems: 1 + required: + - interrupts + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-wakeup-eint + - samsung,exynosautov9-wakeup-eint + then: + properties: + interrupts: false additionalProperties: false -- cgit v1.2.3 From 7dbb47d64acf4aac131a2aaade726913aa62abe7 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Wed, 15 Dec 2021 16:02:45 -0500 Subject: dt-bindings: soc: rockchip: add rk3568-usb2phy-grf Add the documentation for the rk3568-usb2phy-grf node, which is separate from the usb2phy node on this chip. Signed-off-by: Peter Geis Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211215210252.120923-2-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index dfebf425ca49..b2ba7bed89b2 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - rockchip,rk3288-sgrf + - rockchip,rk3568-usb2phy-grf - rockchip,rv1108-usbgrf - const: syscon - items: -- cgit v1.2.3 From 9998104515d4197d774e5384df750c6384915707 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Tue, 18 Jan 2022 19:57:44 +0100 Subject: dt-bindings: arm: samsung: document Chagall WiFi board binding Add binding for Samsung Galaxy Tab S 10.5", based on Exynos 5420 with codename chagall-wifi. It was released in 2014 and has several siblings with similar hardware. Signed-off-by: Henrik Grimler Link: https://lore.kernel.org/r/20220118185746.299832-2-henrik@grimler.se Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 052cd94113d4..a2a8bf44fe9b 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -140,6 +140,7 @@ properties: items: - enum: - insignal,arndale-octa # Insignal Arndale Octa + - samsung,chagall-wifi # Samsung SM-T800 - samsung,smdk5420 # Samsung SMDK5420 eval - const: samsung,exynos5420 - const: samsung,exynos5 -- cgit v1.2.3 From 210b3ef939c846f4af0602bdc660852e837bf4a8 Mon Sep 17 00:00:00 2001 From: Conley Lee Date: Sat, 15 Jan 2022 00:31:48 +0800 Subject: dt-bindings: arm: sunxi: add haoyu,a20-marsboard add haoyu,a20-marsboard dt-bindings Signed-off-by: Conley Lee Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/tencent_B6059C6C031E46EFCB05D5A5015B1C4DE608@qq.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c8a3102c0fde..086c68771d2b 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -444,6 +444,11 @@ properties: - const: haoyu,a10-marsboard - const: allwinner,sun4i-a10 + - description: HAOYU Electronics Marsboard A20 + items: + - const: haoyu,a20-marsboard + - const: allwinner,sun7i-a20 + - description: MapleBoard MP130 items: - const: mapleboard,mp130 -- cgit v1.2.3 From 509e1a8675fcab9861fe280ebb5bf17e47349c40 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 21 Dec 2021 09:47:02 +0000 Subject: dt-bindings: arm: renesas: Document Renesas RZ/V2L SoC on SMARC EVK Document the Renesas SMARC EVK board which is based on the Renesas RZ/V2L (R9A07G054) SoC. The SMARC EVK consists of an RZ/V2L SoM module and a SMARC carrier board. The SoM module sits on top of the carrier board. Signed-off-by: Biju Das Signed-off-by: Lad Prabhakar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211221094717.16187-2-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20211221094717.16187-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 6a9350ee690b..fa435d6fda77 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -421,6 +421,15 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 + - description: RZ/V2L (R9A07G054) + items: + - enum: + - renesas,smarc-evk # SMARC EVK + - enum: + - renesas,r9a07g054l1 # Single Cortex-A55 RZ/V2L + - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L + - const: renesas,r9a07g054 + additionalProperties: true ... -- cgit v1.2.3 From 4b4a0fd666303a06bbe159552bc055b490b77cdc Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Jan 2022 13:46:48 +0000 Subject: dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC Add DT binding documentation for the SYSC controller found on the RZ/V2L SoC. This SYSC controller is almost identical to the one found on the RZ/G2L SoC, the only difference being that SYSC on RZ/V2L has an additional register to control the DRP-AI. Signed-off-by: Biju Das Signed-off-by: Lad Prabhakar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220110134659.30424-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index 84ddc772b003..bb433e75a0ee 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -4,14 +4,14 @@ $id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/G2L System Controller (SYSC) +title: Renesas RZ/{G2L,V2L} System Controller (SYSC) maintainers: - Geert Uytterhoeven description: - The RZ/G2L System Controller (SYSC) performs system control of the LSI and - supports following functions, + The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI + and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -21,6 +21,7 @@ properties: compatible: enum: - renesas,r9a07g044-sysc # RZ/G2{L,LC} + - renesas,r9a07g054-sysc # RZ/V2L reg: maxItems: 1 -- cgit v1.2.3 From 506ca49ae7b4f0ddd9bd0ee5adff3e580218c32c Mon Sep 17 00:00:00 2001 From: Maxim Kutnij Date: Sun, 19 Dec 2021 23:31:34 +0500 Subject: dt-bindings: mediatek: Adds a DT binding documentation for the MT6582 SoC This adds a DT binding documentation for the MT6582 SoC. Signed-off-by: Maxim Kutnij Link: https://lore.kernel.org/r/20211219183134.3849-3-gtk3@inbox.ru [mb: fix commit subject line and compatible order] Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 + Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 3 files changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 0ffe1acf1344..ab0593c77321 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -30,6 +30,10 @@ properties: - enum: - mediatek,mt6580-evbp1 - const: mediatek,mt6580 + - items: + - enum: + - prestigio,pmt5008-3g + - const: mediatek,mt6582 - items: - enum: - fairphone,fp1 diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index e5c57d6e0186..fbd76a8e023b 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -12,6 +12,7 @@ Required properties: For those SoCs that use GPT * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) + * "mediatek,mt6582-timer" for MT6582 compatible timers (GPT) * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT) * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 0114871f887a..a97418c74f6b 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -8,6 +8,7 @@ Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 "mediatek,mt2712-wdt": for MT2712 + "mediatek,mt6582-wdt", "mediatek,mt6589-wdt": for MT6582 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 -- cgit v1.2.3 From d218159f19bf6697448d86d86ee5bb0d23faefe4 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 20 Dec 2021 22:18:41 +0100 Subject: dt-bindings: Add vendor prefix for Airoha Add vendor prefix "airoha" for Airoha, a subsidiary of MediaTek Acked-by: Rob Herring Signed-off-by: John Crispin Signed-off-by: Bert Vermeulen Signed-off-by: Felix Fietkau Link: https://lore.kernel.org/r/20211220211854.89452-2-nbd@nbd.name Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 294093d45a23..05f86bfd0b31 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -61,6 +61,8 @@ patternProperties: description: Aeroflex Gaisler AB "^aesop,.*": description: AESOP Embedded Forum + "^airoha,.*": + description: Airoha "^al,.*": description: Annapurna Labs "^alcatel,.*": -- cgit v1.2.3 From 51911d1c1bb3e30b57e3af1072a3b6e583f3df5f Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 20 Dec 2021 22:18:42 +0100 Subject: dt-bindings: arm: airoha: Add binding for EN7523 SoC and EVB Add devicetree binding for Airoha EN7523 SoC and evaluation board. Reviewed-by: Rob Herring Signed-off-by: John Crispin Signed-off-by: Bert Vermeulen Signed-off-by: Felix Fietkau Link: https://lore.kernel.org/r/20211220211854.89452-3-nbd@nbd.name Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/airoha.yaml | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/airoha.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml new file mode 100644 index 000000000000..fc19b1a6f37b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/airoha.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/airoha.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha SoC based Platforms Device Tree Bindings + +maintainers: + - Felix Fietkau + - John Crispin + +description: + Boards with an Airoha SoC shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - airoha,en7523-evb + - const: airoha,en7523 + +additionalProperties: true + +... -- cgit v1.2.3 From 8d4d0d7c43e6f87df02a0acac206b50c265962d1 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Mon, 24 Jan 2022 14:12:40 +0100 Subject: dt-bindings: arm: samsung: document Klimt WiFi board binding Add binding for Galaxy Tab S 8.4", based on Exynos 5420 with codename klimt-wifi. Signed-off-by: Henrik Grimler Link: https://lore.kernel.org/r/20220124131241.29946-2-henrik@grimler.se Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index a2a8bf44fe9b..faea33e4f731 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -141,6 +141,7 @@ properties: - enum: - insignal,arndale-octa # Insignal Arndale Octa - samsung,chagall-wifi # Samsung SM-T800 + - samsung,klimt-wifi # Samsung SM-T700 - samsung,smdk5420 # Samsung SMDK5420 eval - const: samsung,exynos5420 - const: samsung,exynos5 -- cgit v1.2.3 From a5a93e9b9ab9b4f367a773b32bbe1687006d75b7 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Mon, 24 Jan 2022 19:46:29 +0530 Subject: dt-bindings: add vendor prefix for Tesla Add vendor prefix for the Tesla (https://www.tesla.com) Cc: linux-fsd@tesla.com Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alim Akhtar Link: https://lore.kernel.org/r/20220124141644.71052-2-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 294093d45a23..e7a362c17df7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1205,6 +1205,8 @@ patternProperties: description: Shenzhen Techstar Electronics Co., Ltd. "^terasic,.*": description: Terasic Inc. + "^tesla,.*": + description: Tesla, Inc. "^tfc,.*": description: Three Five Corp "^thead,.*": -- cgit v1.2.3 From d25c5eb511df3439cd91517bcbce4b274f8972b9 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Mon, 24 Jan 2022 19:46:41 +0530 Subject: dt-bindings: arm: add Tesla FSD ARM SoC Add device tree bindings for the Tesla FSD ARM SoC. Cc: linux-fsd@tesla.com Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alim Akhtar Link: https://lore.kernel.org/r/20220124141644.71052-14-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/tesla.yaml | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml b/Documentation/devicetree/bindings/arm/tesla.yaml new file mode 100644 index 000000000000..09856da657dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tesla.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tesla.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla Full Self Driving(FSD) platforms device tree bindings + +maintainers: + - Alim Akhtar + - linux-fsd@tesla.com + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: FSD SoC board + items: + - enum: + - tesla,fsd-evb # Tesla FSD Evaluation + - const: tesla,fsd + +additionalProperties: true + +... -- cgit v1.2.3 From c04421c68fd40ee33df87eea69c1a447b7985d0d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 18 Nov 2021 22:02:08 +0100 Subject: dt-bindings: phy: qcom,usb-hs-phy: add MSM8226 compatible Add a compatible for MSM8226 which also uses the USB HS PHY. Signed-off-by: Luca Weiss Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211118210210.160895-5-luca@z3ntu.xyz --- Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt index b3b75c1e6285..6814dccb390c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt @@ -9,6 +9,7 @@ PROPERTIES following: "qcom,usb-hs-phy-apq8064" + "qcom,usb-hs-phy-msm8226" "qcom,usb-hs-phy-msm8916" "qcom,usb-hs-phy-msm8974" -- cgit v1.2.3 From 42d3ce71ebcee2233f8a21adb44cb707f2ea3a57 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 3 Feb 2022 14:30:30 +0530 Subject: dt-bindings: arm: qcom: Document SM8450 HDK boards Document the SM8450 HDK board Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220203090031.3128702-1-vkoul@kernel.org --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 370aab274cd1..9a75274f9ae4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -268,6 +268,7 @@ properties: - items: - enum: + - qcom,sm8450-hdk - qcom,sm8450-qrd - const: qcom,sm8450 -- cgit v1.2.3 From 7f25465e779d9eda845ec3d47151a2acd1d9e383 Mon Sep 17 00:00:00 2001 From: Reinhold Mueller Date: Thu, 9 Dec 2021 11:49:46 +0100 Subject: dt-binding: arm/stm32: Add emtrion hardware emSBC-Argon This patch presents the yaml patch for the emtrion GmbH Argon board series. Signed-off-by: Reinhold Mueller Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index b07720ea9611..fa0a1b84122e 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -28,6 +28,12 @@ properties: - enum: - st,stm32mp153 - st,stm32mp157 + + - description: emtrion STM32MP1 Argon based Boards + items: + - const: emtrion,stm32mp157c-emsbc-argon + - const: emtrion,stm32mp157c-emstamp-argon + - const: st,stm32mp157 - items: - enum: - st,stm32f429i-disco -- cgit v1.2.3 From 8ad885126daadba5dc388c7f06d5cb93206e40b1 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 23 Jan 2022 14:51:15 +0100 Subject: dt-bindings: rockchip: Add BananaPi R2 Pro Board Add Devicetree Binding for Bananapi R2 Pro Board based on rk3568 SoC Co-developed-by: Peter Geis Signed-off-by: Peter Geis Signed-off-by: Frank Wunderlich Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220123135116.136846-2-linux@fw-web.de Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 4aed16176434..33d6423fe6c3 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -651,6 +651,11 @@ properties: - const: rockchip,rk3568-evb1-v10 - const: rockchip,rk3568 + - description: Rockchip RK3568 Banana Pi R2 Pro + items: + - const: rockchip,rk3568-bpi-r2pro + - const: rockchip,rk3568 + additionalProperties: true ... -- cgit v1.2.3 From b08e569abc91f525834deda751d6ddd1ffe4ab5a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:31:14 +0100 Subject: dt-bindings: altera: document existing Cyclone 5 board compatibles Several Cyclone 5 SoCFPGA based boards have additional board compatibles which are not documented in the bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 30 ++++++++++++++++++----- 1 file changed, 24 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index c15c92fdf2ed..0d62c2bde053 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -13,12 +13,30 @@ properties: $nodename: const: "/" compatible: - items: - - enum: - - altr,socfpga-cyclone5 - - altr,socfpga-arria5 - - altr,socfpga-arria10 - - const: altr,socfpga + oneOf: + - description: Arria 5 boards + items: + - const: altr,socfpga-arria5 + - const: altr,socfpga + + - description: Arria 10 boards + items: + - const: altr,socfpga-arria10 + - const: altr,socfpga + + - description: Cyclone 5 boards + items: + - enum: + - altr,socfpga-cyclone5-socdk + - denx,mcvevk + - ebv,socrates + - macnica,sodia + - novtech,chameleon96 + - samtec,vining + - terasic,de0-atlas + - terasic,socfpga-cyclone5-sockit + - const: altr,socfpga-cyclone5 + - const: altr,socfpga additionalProperties: true -- cgit v1.2.3 From 8227e63ddf8d1b208f5d0fd58aeb5fec9ab57330 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:31:15 +0100 Subject: dt-bindings: altera: document Arria 5 based board compatibles Add new compatible for Arria 5 based boards. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 0d62c2bde053..3d7a2f699279 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -16,6 +16,8 @@ properties: oneOf: - description: Arria 5 boards items: + - enum: + - altr,socfpga-arria5-socdk - const: altr,socfpga-arria5 - const: altr,socfpga -- cgit v1.2.3 From 15dc346c7a1940cf438495162fedf29d86924fa4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:31:16 +0100 Subject: dt-bindings: altera: document Arria 10 based board compatibles Add new compatible for Arria 10 based boards. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 3d7a2f699279..963c83904010 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -23,6 +23,9 @@ properties: - description: Arria 10 boards items: + - enum: + - altr,socfpga-arria10-socdk + - enclustra,mercury-aa1 - const: altr,socfpga-arria10 - const: altr,socfpga -- cgit v1.2.3 From 53d50b4f6fa8a6da4ff6fe6cf58a88a92fa15acb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:31:17 +0100 Subject: dt-bindings: altera: document VT compatibles Add new compatible for SoCFPGA VT boards/designs. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 963c83904010..f4e07a21aaf5 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -43,6 +43,11 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: SoCFPGA VT + items: + - const: altr,socfpga-vt + - const: altr,socfpga + additionalProperties: true ... -- cgit v1.2.3 From f8aa14dd365ab3f0608931503dab3e8665226b25 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:32 +0100 Subject: dt-bindings: altera: document Stratix 10 based board compatibles Add new compatible for Stratix 10 based boards. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index f4e07a21aaf5..5e2017c0a051 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -43,6 +43,12 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: Stratix 10 boards + items: + - enum: + - altr,socfpga-stratix10-socdk + - const: altr,socfpga-stratix10 + - description: SoCFPGA VT items: - const: altr,socfpga-vt -- cgit v1.2.3 From abca30aa14b1ec3d96547ec71d690aa1169cc4e6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:46 +0100 Subject: dt-bindings: intel: document Agilex based board compatibles Add new compatible for Agilex based boards. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/arm/intel,socfpga.yaml | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel,socfpga.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml new file mode 100644 index 000000000000..6e043459fcd5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA platform device tree bindings + +maintainers: + - Dinh Nguyen + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - description: AgileX boards + items: + - enum: + - intel,n5x-socdk + - intel,socfpga-agilex-socdk + - const: intel,socfpga-agilex + +additionalProperties: true + +... -- cgit v1.2.3 From ad7f9f3ad1bc7403d0b6d655d92fa7b4b1899629 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:47 +0100 Subject: dt-bindings: clock: intel,stratix10: convert to dtschema Convert the Intel Stratix 10 clock controller bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/clock/intc_stratix10.txt | 20 ------------- .../devicetree/bindings/clock/intel,stratix10.yaml | 35 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/intc_stratix10.txt create mode 100644 Documentation/devicetree/bindings/clock/intel,stratix10.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt deleted file mode 100644 index 9f4ec5cb5c6b..000000000000 --- a/Documentation/devicetree/bindings/clock/intc_stratix10.txt +++ /dev/null @@ -1,20 +0,0 @@ -Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be - "intel,stratix10-clkmgr" - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. - -- #clock-cells : from common clock binding, shall be set to 1. - -Example: - clkmgr: clock-controller@ffd10000 { - compatible = "intel,stratix10-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/intel,stratix10.yaml b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml new file mode 100644 index 000000000000..f506e3db9782 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Stratix10 platform clock controller binding + +maintainers: + - Dinh Nguyen + +properties: + compatible: + const: intel,stratix10-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@ffd10000 { + compatible = "intel,stratix10-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; -- cgit v1.2.3 From 134cfc5565d3b9abf9c406791bbc96008e80f0d5 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 3 Feb 2022 07:25:13 +0000 Subject: dt-bindings: arm: qcom: Add msm8996 and apq8096 compatibles Add compatibles for MSM8996 and APQ8096 and all supported devices that have them. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220203072226.51482-2-y.oudjana@protonmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 9a75274f9ae4..298d7129f907 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -173,7 +173,21 @@ properties: - const: qcom,apq8094 - items: - - const: qcom,msm8996-mtp + - enum: + - arrow,apq8096-db820c + - inforce,ifc6640 + - const: qcom,apq8096-sbc + - const: qcom,apq8096 + + - items: + - enum: + - qcom,msm8996-mtp + - sony,dora-row + - sony,kagura-row + - sony,keyaki-row + - xiaomi,gemini + - xiaomi,scorpio + - const: qcom,msm8996 - items: - enum: -- cgit v1.2.3 From 182c4e1f92c1f1c1c6d14e2409aa85a11d8136ba Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 25 Jan 2022 11:11:20 -0600 Subject: dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl This adds the DT binding for the i.MX8MQ VPU blk-ctrl. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml new file mode 100644 index 000000000000..7263ebedf09f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MQ VPU blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mq-vpu-blk-ctrl + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 3 + maxItems: 3 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: g1 + - const: g2 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; + }; -- cgit v1.2.3 From 5f558b6dbf21c782a4c8f2f5f01d5bfb6792f818 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 17 Dec 2021 22:36:16 +0100 Subject: dt-bindings: arm: imx: add Protonic PRT8MM board compatible Add the compatible string for the Protonic PRT8MM board, which is a reference design for a low-cost agricultural terminal. Signed-off-by: Lucas Stach Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 97f6eebad76a..5075fd8c1b42 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -771,6 +771,7 @@ properties: - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module + - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm - description: Engicam i.Core MX8M Mini SoM based boards -- cgit v1.2.3 From 00ffe9e0833cb6c28454ccb22bd3dc818bb84ace Mon Sep 17 00:00:00 2001 From: Reinhold Mueller Date: Thu, 27 Jan 2022 16:34:59 +0100 Subject: dt-bindings: arm: Add emtrion hardware emCON-MX8M Mini This patch presents the yaml patch for the emtrion GmbH emCON-MX8M Mini. Signed-off-by: Reinhold Mueller Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 5075fd8c1b42..e58e21efdf0b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -762,6 +762,7 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board + - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit -- cgit v1.2.3 From 6ba8986b35ed2cafb573ad19c74e838d8b21cbab Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 11 Feb 2022 10:23:21 +0100 Subject: dt-bindings: arm: fsl: add toradex,verdin-imx8mm et al. Add toradex,verdin-imx8mm for our new Verdin iMX8M Mini modules, its nonwifi and wifi variants and the carrier boards (both Dahlia and the Verdin Development Board) they may be mated in. Signed-off-by: Marcel Ziswiler Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index e58e21efdf0b..23e678232451 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -771,6 +771,9 @@ properties: - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM + - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules + - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT + - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm @@ -789,6 +792,24 @@ properties: - const: kontron,imx8mm-n801x-som - const: fsl,imx8mm + - description: Toradex Boards with Verdin iMX8M Mini Modules + items: + - enum: + - toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia + - toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board + - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT + - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module + - const: fsl,imx8mm + + - description: Toradex Boards with Verdin iMX8M Mini Wi-Fi / BT Modules + items: + - enum: + - toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia + - toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B. + - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module + - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module + - const: fsl,imx8mm + - description: Variscite VAR-SOM-MX8MM based boards items: - const: variscite,var-som-mx8mm-symphony -- cgit v1.2.3 From 269923def7ab613f37269439ede7d4cbf9375058 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Thu, 23 Sep 2021 19:07:46 +0200 Subject: dt-bindings: add vendor prefix for Wireless Tag This adds a vendor prefix for wireless tag boards and SOMs. Signed-off-by: Romain Perier Acked-by: Rob Herring Signed-off-by: Daniel Palmer --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 294093d45a23..d9c0647e9d56 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1348,6 +1348,8 @@ patternProperties: description: WinLink Co., Ltd "^winstar,.*": description: Winstar Display Corp. + "^wirelesstag,.*": + description: Wireless Tag (qiming yunduan) "^wits,.*": description: Shenzhen Merrii Technology Co., Ltd. (WITS) "^wlf,.*": -- cgit v1.2.3 From 42bd9c510b9ae91ba332b27cdc1edcfa78a64320 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Thu, 23 Sep 2021 19:07:47 +0200 Subject: ARM: dts: mstar: Add the Wireless Tag IDO-SBC2D06-V1B-22W The Wireless Tag IDO-SBC2D06-V1B-22W[1] is an SBC powered by SSD202D with a dual Ethernet and a connector for a 4-inch and 7-inch display. It embeds a System-On-Module IDO-SOM2D01[2] with an Mstar SSD202 SoC dual-core Cortex-A7 CPU @ 1.2Ghz , 2D GPU, 128 MB DDR3 (on-chip) and a 256MB SPI NAND flash. This commit adds basic definition for this board. 1. http://linux-chenxing.org/infinity2/ido-sbc2d06 2. http://www.wireless-tag.com/portfolio/ido-som2d01 Signed-off-by: Romain Perier Reviewed-by: Rob Herring Signed-off-by: Daniel Palmer --- .../devicetree/bindings/arm/mstar/mstar.yaml | 2 ++ arch/arm/boot/dts/Makefile | 1 + .../boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi | 20 ++++++++++++++++ ...y2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts | 23 ++++++++++++++++++ ...infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi | 28 ++++++++++++++++++++++ 5 files changed, 74 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml index a316eef1b728..10efd703717e 100644 --- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -25,6 +25,8 @@ properties: - enum: - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit - m5stack,unitv2 # M5Stack UnitV2 + - wirelesstag,ido-som2d01 # Wireless Tag IDO-SOM2D01 + - wirelesstag,ido-sbc2d06-v1b-22w # Wireless Tag IDO-SBC2D06-1VB-22W - const: mstar,infinity2m - description: infinity3 boards diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 235ad559acb2..1069c4cdcff0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1492,6 +1492,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ mstar-infinity2m-ssd202d-ssd201htv2.dtb \ mstar-infinity2m-ssd202d-unitv2.dtb \ mstar-infinity3-msc313e-breadbee.dtb \ diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi new file mode 100644 index 000000000000..34df472fed71 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/ { + reg_vcc_dram: regulator-vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc_dram"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts new file mode 100644 index 000000000000..b15c40762bc0 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi" +#include + +/ { + model = "Wireless Tag IDO-SBC2D06-1VB-22W"; + compatible = "wirelesstag,ido-sbc2d06-v1b-22w", "mstar,infinity2m"; + + leds { + compatible = "gpio-leds"; + sys_led { + gpios = <&gpio SSD20XD_GPIO_GPIO85 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi new file mode 100644 index 000000000000..d877aff85033 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" +#include "mstar-infinity2m-ssd201-som2d01.dtsi" + +/ { + model = "Wireless Tag IDO-SOM2D01 (SSD202D)"; + compatible = "wirelesstag,ido-som2d01", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +®_vcc_dram { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; -- cgit v1.2.3 From 365e7ecaaf8ed554729c9fc26e9734d027807f02 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Mon, 13 Dec 2021 18:54:03 +0900 Subject: dt-bindings: vendor-prefixes: Add prefix for Miyoo Add a prefix for "miyoo". The only details I can find about the company is their aliexpress store "miyoo global store": https://www.aliexpress.com/store/912663639 Signed-off-by: Daniel Palmer Acked-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index d9c0647e9d56..b745cf748ff8 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -769,6 +769,8 @@ patternProperties: description: MiraMEMS Sensing Technology Co., Ltd. "^mitsubishi,.*": description: Mitsubishi Electric Corporation + "^miyoo,.*": + description: Miyoo "^mntre,.*": description: MNT Research GmbH "^modtronix,.*": -- cgit v1.2.3 From 2c63dddadf381cfee8cc7a3b14eff7f289db944c Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Mon, 13 Dec 2021 18:54:10 +0900 Subject: dt-bindings: arm: mstar: Add compatible for Miyoo Mini The Miyoo Mini is a SigmaStar SSD202D based retro emulation device. Add a compatible for it to the list of infinity2m devices. Link: http://linux-chenxing.org/infinity2/miyoomini/ Signed-off-by: Daniel Palmer Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/mstar/mstar.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml index 10efd703717e..4365efd9c36b 100644 --- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -25,6 +25,7 @@ properties: - enum: - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit - m5stack,unitv2 # M5Stack UnitV2 + - miyoo,miyoo-mini # Miyoo Mini - wirelesstag,ido-som2d01 # Wireless Tag IDO-SOM2D01 - wirelesstag,ido-sbc2d06-v1b-22w # Wireless Tag IDO-SBC2D06-1VB-22W - const: mstar,infinity2m -- cgit v1.2.3 From 1eef31660001a996114b26cd2fc05551d77bd02e Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Thu, 9 Dec 2021 19:39:07 +0900 Subject: dt-bindings: vendor-prefixes: Add prefix for 100ask 100ask is Linux SBC/module/training provider. Add a prefix for them. Link: https://www.100ask.net Signed-off-by: Daniel Palmer Acked-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b745cf748ff8..44483d0de9c4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -23,6 +23,8 @@ patternProperties: "^(simple-audio-card|st-plgpio|st-spics|ts),.*": true # Keep list in alphabetical order. + "^100ask,.*": + description: Baiwen.com (100ask). "^70mai,.*": description: 70mai Co., Ltd. "^8dev,.*": -- cgit v1.2.3 From 79f1e65a94d77088efbbc78872564ed027c232e7 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Thu, 9 Dec 2021 19:44:31 +0900 Subject: dt-bindings: arm: mstar: Add compatible for 100ask DongShanPiOne The DongShanPiOne is a SigmaStar SSD202D based module. Add a compatible for it to the list of infinity2m boards. Link: http://linux-chenxing.org/infinity2/dongshanpione/ Signed-off-by: Daniel Palmer Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/mstar/mstar.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml index 4365efd9c36b..8892eb6bd3ef 100644 --- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -23,6 +23,7 @@ properties: - description: infinity2m boards items: - enum: + - 100ask,dongshanpione # 100ask DongShanPiOne - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit - m5stack,unitv2 # M5Stack UnitV2 - miyoo,miyoo-mini # Miyoo Mini -- cgit v1.2.3 From e5eb80f0c076346d5e837dc09e3604f79a8c6814 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 1 Feb 2022 18:27:45 +0100 Subject: dt-bindings: arm: bcm2835: Add Raspberry Pi Zero 2 W Add the Raspberry Pi Zero 2 W to DT schema. Signed-off-by: Stefan Wahren Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 5dc48241efb3..8051a75c2c79 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -51,6 +51,7 @@ properties: - raspberrypi,3-model-b-plus - raspberrypi,3-compute-module - raspberrypi,3-compute-module-lite + - raspberrypi,model-zero-2-w - const: brcm,bcm2837 additionalProperties: true -- cgit v1.2.3 From a7c9013216f399791ca354cc2e0f4a444837fe39 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 29 Jan 2022 23:38:01 -0600 Subject: dt-bindings: arm: rockchip: Add Pine64 PineNote board The PineNote is a tablet from Pine64 based on the RK3566 SoC. There are two existing variants of the board. v1.1 was contained in some early samples, and v1.2 was sold as the "PineNote Developer Edition". Signed-off-by: Samuel Holland Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220130053803.43660-1-samuel@sholland.org Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 33d6423fe6c3..eece92f83a2d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -481,6 +481,14 @@ properties: - const: pine64,pinebook-pro - const: rockchip,rk3399 + - description: Pine64 PineNote + items: + - enum: + - pine64,pinenote-v1.1 + - pine64,pinenote-v1.2 + - const: pine64,pinenote + - const: rockchip,rk3566 + - description: Pine64 Rock64 items: - const: pine64,rock64 -- cgit v1.2.3 From 39d01d9c4522c4ac9e0f041eaaf7cee670a6a574 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 7 Feb 2022 20:25:40 +0100 Subject: dt-bindings: power: add defines for i.MX8MP power domain This adds the DT defines for the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/power/fsl,imx-gpcv2.yaml | 2 ++ include/dt-bindings/power/imx8mp-power.h | 29 ++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/power/imx8mp-power.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index 01bdda167eef..747622bdc57b 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -28,6 +28,7 @@ properties: - fsl,imx8mn-gpc - fsl,imx8mq-gpc - fsl,imx8mm-gpc + - fsl,imx8mp-gpc reg: maxItems: 1 @@ -57,6 +58,7 @@ properties: include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc + include/dt-bindings/power/imx8mp-power.h for fsl,imx8mp-gpc maxItems: 1 clocks: diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h new file mode 100644 index 000000000000..7c67689e4faf --- /dev/null +++ b/include/dt-bindings/power/imx8mp-power.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Sascha Hauer + */ + +#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ +#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ + +#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0 +#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1 +#define IMX8MP_POWER_DOMAIN_USB1_PHY 2 +#define IMX8MP_POWER_DOMAIN_USB2_PHY 3 +#define IMX8MP_POWER_DOMAIN_MLMIX 4 +#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5 +#define IMX8MP_POWER_DOMAIN_GPU2D 6 +#define IMX8MP_POWER_DOMAIN_GPUMIX 7 +#define IMX8MP_POWER_DOMAIN_VPUMIX 8 +#define IMX8MP_POWER_DOMAIN_GPU3D 9 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10 +#define IMX8MP_POWER_DOMAIN_VPU_G1 11 +#define IMX8MP_POWER_DOMAIN_VPU_G2 12 +#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13 +#define IMX8MP_POWER_DOMAIN_HDMIMIX 14 +#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15 +#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16 +#define IMX8MP_POWER_DOMAIN_HSIOMIX 17 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 + +#endif -- cgit v1.2.3 From 8a473f456090d13c228c41623104a07db6d958ef Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 7 Feb 2022 20:25:43 +0100 Subject: dt-bindings: soc: add binding for i.MX8MP HSIO blk-ctrl This adds the binding for the HSIO blk-ctrl on the i.MX8MP SoC. Signed-off-by: Lucas Stach Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml new file mode 100644 index 000000000000..c1e29d94f40e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP HSIO blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the high-speed IO + (USB an PCIe) peripherals located in the HSIO domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mp-hsio-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 6 + maxItems: 6 + + power-domain-names: + items: + - const: bus + - const: usb + - const: usb-phy1 + - const: usb-phy2 + - const: pcie + - const: pcie-phy + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: usb + - const: pcie + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; -- cgit v1.2.3 From a268b155100b37cd280fcfd3ef72be536f33dfa0 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 29 Jan 2022 12:52:20 +0100 Subject: dt-bindings: arm/npcm: Add binding for global control registers (GCR) A nuvoton,*-gcr node is present in nuvoton-common-npcm7xx.dtsi and will be added to nuvoton-wpcm450.dtsi. It is necessary for the NPCM7xx and WPCM450 pinctrl drivers, and may later be used to retrieve SoC model and version information. This patch adds a binding to describe this node. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220129115228.2257310-2-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- .../devicetree/bindings/arm/npcm/nuvoton,gcr.yaml | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml new file mode 100644 index 000000000000..fcb211add7d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Control Registers block in Nuvoton SoCs + +maintainers: + - Jonathan Neuschäfer + +description: + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs + that expose misc functionality such as chip model and version information or + pinmux settings. + +properties: + compatible: + items: + - enum: + - nuvoton,wpcm450-gcr + - nuvoton,npcm750-gcr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + gcr: syscon@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; + }; -- cgit v1.2.3 From c952e5075de1f76e092bc780503ebc5cb8222a01 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 23 Feb 2021 15:18:23 +0900 Subject: dt-bindings: clk: mstar msc313 cpupll binding description Add a binding description for the MStar/SigmaStar CPU PLL block. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring --- .../bindings/clock/mstar,msc313-cpupll.yaml | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml new file mode 100644 index 000000000000..a9ad7ab5230c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 CPU PLL + +maintainers: + - Daniel Palmer + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable + PLL that can be used as the clock source for the CPU(s). + +properties: + compatible: + const: mstar,msc313-cpupll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + #include + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <1>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; -- cgit v1.2.3 From 039facb4323b9ff22e50c017c60f7020811a7229 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 11 Feb 2022 11:04:17 -0800 Subject: dt-bindings: arm: imx: add imx8mm gw7903 support The GW7903 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD connector with UHS support - LIS2DE12 3-axis accelerometer - Gateworks System Controller - IMX8M FEC - software selectable RS232/RS485/RS422 serial transceiver - PMIC - 2x off-board bi-directional opto-isolated digital I/O - 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe (resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket) Signed-off-by: Tim Harvey Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 23e678232451..08bdd30e511c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -770,6 +770,7 @@ properties: - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board + - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT -- cgit v1.2.3 From 41654043226f517a8b37cab34f1eab5c6ef16947 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Fri, 11 Feb 2022 10:53:09 +0000 Subject: dt-bindings: vendor-prefixes: add osmc prefix Open Source Media Centre (Sam Nazarko Trading Ltd.) are a manufacturer of Linux Set-Top Box devices. Signed-off-by: Christian Hewitt Acked-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220211105311.30320-2-christianshewitt@gmail.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 52ff63248892..b97fd8dfe601 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -882,6 +882,8 @@ patternProperties: description: Ortus Technology Co., Ltd. "^osddisplays,.*": description: OSD Displays + "^osmc,.*": + description: Sam Nazarko Trading Ltd. (Open Source Media Centre) "^ouya,.*": description: Ouya Inc. "^overkiz,.*": -- cgit v1.2.3 From 3f7dbd336f360a76103153b85ce616b86d85c6cd Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Fri, 11 Feb 2022 10:53:10 +0000 Subject: dt-bindings: arm: amlogic: add Vero 4K+ bindings Add the board binding for the OSMC Vero 4K+ STB device Signed-off-by: Christian Hewitt Acked-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220211105311.30320-3-christianshewitt@gmail.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index a073a959232c..61a6cabb375b 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -108,6 +108,7 @@ properties: - amlogic,p230 - amlogic,p231 - libretech,aml-s905d-pc + - osmc,vero4k-plus - phicomm,n1 - smartlabs,sml5442tw - videostrong,gxl-kii-pro -- cgit v1.2.3 From d978ab1a7b7a334634e60ed2467e657ca13b76d6 Mon Sep 17 00:00:00 2001 From: Mohan Kumar Date: Wed, 16 Feb 2022 14:52:39 +0530 Subject: dt-bindings: Document Tegra234 HDA support Update binding document for HDA support on Tegra234 chip. Tegra234 has max of 2 clocks and 2 resets which requires to add minItems and maxItems for clocks and resets as Tegra chips can now have minimum of 2 and maximum of 3 clocks and reset support. Signed-off-by: Mohan Kumar Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml index 2c913aa44fee..12c31b4b99e1 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml @@ -23,6 +23,7 @@ properties: - const: nvidia,tegra30-hda - items: - enum: + - nvidia,tegra234-hda - nvidia,tegra194-hda - nvidia,tegra186-hda - nvidia,tegra210-hda @@ -41,9 +42,11 @@ properties: maxItems: 1 clocks: + minItems: 2 maxItems: 3 clock-names: + minItems: 2 items: - const: hda - const: hda2hdmi -- cgit v1.2.3 From e74964d0236f34b2abded4fead22dbec2272e213 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 10 Feb 2022 14:18:17 +0100 Subject: dt-bindings: arm: at91: add Kontron's new KSwitches The Kontron KSwitch D10 MMT series ethernet switches features a LAN9668 SoC with either 8 copper ports or 6 copper port and two SFP cages. Signed-off-by: Michael Walle Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20220210131817.484922-1-michael@walle.cc --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index c612e1f48dba..9d46ff78739f 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -174,6 +174,15 @@ properties: - const: microchip,lan9668 - const: microchip,lan966 + - description: Kontron KSwitch D10 MMT series + items: + - enum: + - kontron,kswitch-d10-mmt-8g + - kontron,kswitch-d10-mmt-6g-2gs + - const: kontron,s1921 + - const: microchip,lan9668 + - const: microchip,lan966 + - items: - enum: - atmel,sams70j19 -- cgit v1.2.3 From 08b25f7d99e15f2aa5f4cce3f13ad0c67a4c1e34 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 20 Feb 2022 21:18:57 +0100 Subject: dt-bindings: arm: cpus: Add Kryo 250 CPUs Document Kryo 250 CPUs found in Qualcomm Snapdragon 632 (SDM632). Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220220201909.445468-5-luca@z3ntu.xyz --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 0dcebc48ea22..3aad1b93742c 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -173,6 +173,7 @@ properties: - nvidia,tegra194-carmel - qcom,krait - qcom,kryo + - qcom,kryo250 - qcom,kryo260 - qcom,kryo280 - qcom,kryo385 -- cgit v1.2.3 From cb898d5e59b41a268dcf4dbef31d651c393dfbae Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 20 Feb 2022 21:19:02 +0100 Subject: dt-bindings: arm: qcom: Document sdm632 and fairphone,fp3 board Add binding documentation for Fairphone 3 smartphone which is based on Snapdragon 632 (sm632). Signed-off-by: Luca Weiss Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220220201909.445468-10-luca@z3ntu.xyz --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 298d7129f907..f4336ea0c6a7 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -42,6 +42,7 @@ description: | sc7180 sc7280 sdm630 + sdm632 sdm660 sdm845 sdx55 @@ -225,6 +226,11 @@ properties: - google,senor - const: qcom,sc7280 + - items: + - enum: + - fairphone,fp3 + - const: qcom,sdm632 + - items: - enum: - xiaomi,lavender -- cgit v1.2.3 From c4dda0cb4574a5541ca92a6ebb5e33798de1c59e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 25 Feb 2022 17:32:36 +0530 Subject: dt-bindings: arm: ti: Add bindings for AM625 SoC The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220225120239.1303821-3-vigneshr@ti.com --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index b03c10fa2e7a..61c6ab4f52e2 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -46,6 +46,12 @@ properties: - ti,j7200-evm - const: ti,j7200 + - description: K3 AM625 SoC + items: + - enum: + - ti,am625-sk + - const: ti,am625 + - description: K3 AM642 SoC items: - enum: -- cgit v1.2.3 From 643d6a78ac76bc87cdf65183c0dec2457390b383 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Tue, 15 Feb 2022 17:39:23 +0100 Subject: dt-bindings: vendor-prefixes: Add Ctera Networks CTERA Networks Intl. is a company based in Israel. They manufacture NASes, network devices and provide software products for cloud storage and IT security. Signed-off-by: Pawel Dembicki Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 294093d45a23..dececb66b206 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -277,6 +277,8 @@ patternProperties: description: Hangzhou C-SKY Microsystems Co., Ltd "^csq,.*": description: Shenzen Chuangsiqi Technology Co.,Ltd. + "^ctera,.*": + description: CTERA Networks Intl. "^cubietech,.*": description: Cubietech, Ltd. "^cui,.*": -- cgit v1.2.3 From 448841d9a2bcb81962bcf8beb6db8da4d377ee29 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 18 Feb 2022 17:15:19 +0100 Subject: dt-bindings: usb: dwc2: fix compatible of Intel Agilex Intel Agilex USB DWC2 node is used as compatible with generic snps,dwc2 (just like Altera's Stratix10). Acked-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/usb/dwc2.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index f00867ebc147..048e352c531a 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -41,6 +41,7 @@ properties: - amlogic,meson8b-usb - amlogic,meson-gxbb-usb - amlogic,meson-g12a-usb + - intel,socfpga-agilex-hsotg - const: snps,dwc2 - const: amcc,dwc-otg - const: apm,apm82181-dwc-otg -- cgit v1.2.3 From 1b5f9a0487594bae57a6b60d11ee2e274648ec05 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 18 Feb 2022 17:15:20 +0100 Subject: dt-bindings: usb: dwc2: add iommus The DWC2 node might use IOMMU (e.g. Altera Stratix10), so add "iommus" property. This fixes warnings like: arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dt.yaml: usb@ffb40000: 'iommus' does not match any of the regexes: 'pinctrl-[0-9]+' Acked-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/usb/dwc2.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index 048e352c531a..1ba96706bbcb 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -68,6 +68,9 @@ properties: items: - const: otg + iommus: + maxItems: 1 + resets: items: - description: common reset -- cgit v1.2.3 From 4b9ff41f22d69f06dd6bfc929eec0f2a1f05789c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 18 Feb 2022 17:15:21 +0100 Subject: dt-bindings: usb: dwc2: add disable-over-current The driver parses disable-over-current protection and some implementations use it (e.g. Altera Stratix10), so document it in the bindings. Acked-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index 1ba96706bbcb..1addab83f4fd 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -68,6 +68,10 @@ properties: items: - const: otg + disable-over-current: + type: boolean + description: whether to disable detection of over-current condition. + iommus: maxItems: 1 -- cgit v1.2.3