From a44c1d700c848e221d80aab1029d36a60d21a0f4 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 14 Nov 2018 19:13:02 +0000 Subject: ARM: riscpc: replace gettimeoffset() with clocksource Replace the old gettimeoffset() interface (which became buggy in several ways) with a clocksource that atomically reads the count and status from the timer, and corrects the count as appropriate ensuring proper resolution of time without time warping backwards. We keep the original periodic timer non-clock event implementation to provide the kernel with a regular source of interrupts, which are required to keep the clocksource properly updated. Signed-off-by: Russell King --- arch/arm/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9aed25a6019b..08a4915a69d2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -528,7 +528,6 @@ config ARCH_RPC select ARCH_ACORN select ARCH_MAY_HAVE_PC_FDC select ARCH_SPARSEMEM_ENABLE - select ARCH_USES_GETTIMEOFFSET select CPU_SA110 select FIQ select HAVE_IDE -- cgit v1.2.3 From 0b40deeef6d94ac21f4cdee4b1cda94a69c54ff9 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 May 2019 13:35:12 +0100 Subject: ARM: riscpc: enable chained scatterlist support There's no reason why we can't enable chained scatterlist for RiscPC, we already support chained scatterlists in the IOMD DMA support code. Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 08a4915a69d2..e94619684a82 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -528,6 +528,7 @@ config ARCH_RPC select ARCH_ACORN select ARCH_MAY_HAVE_PC_FDC select ARCH_SPARSEMEM_ENABLE + select ARM_HAS_SG_CHAIN select CPU_SA110 select FIQ select HAVE_IDE -- cgit v1.2.3 From d6c8204659eb1846c444997ee28fe9d7e5442f4e Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 31 Aug 2016 08:49:53 +0100 Subject: ARM: sa1100: convert to common clock framework Convert sa1100 to use the common clock framework. Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + arch/arm/mach-sa1100/clock.c | 220 ++++++++++++++++++------------------------- 2 files changed, 95 insertions(+), 126 deletions(-) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8869742a85df..70aebb6d2905 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -549,6 +549,7 @@ config ARCH_SA1100 select CLKSRC_MMIO select CLKSRC_PXA select TIMER_OF if OF + select COMMON_CLK select CPU_FREQ select CPU_SA1100 select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index 6199e87447ca..e8691921c69a 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -2,176 +2,144 @@ /* * linux/arch/arm/mach-sa1100/clock.c */ -#include #include -#include -#include #include #include -#include #include -#include -#include -#include #include +#include +#include +#include #include #include -struct clkops { - void (*enable)(struct clk *); - void (*disable)(struct clk *); - unsigned long (*get_rate)(struct clk *); +static const char * const clk_tucr_parents[] = { + "clk32768", "clk3686400", }; -struct clk { - const struct clkops *ops; - unsigned int enabled; -}; - -#define DEFINE_CLK(_name, _ops) \ -struct clk clk_##_name = { \ - .ops = _ops, \ - } - -static DEFINE_SPINLOCK(clocks_lock); - -/* Dummy clk routine to build generic kernel parts that may be using them */ -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - return clk_get_rate(clk); -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - return 0; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - return 0; -} -EXPORT_SYMBOL(clk_set_parent); +static DEFINE_SPINLOCK(tucr_lock); -struct clk *clk_get_parent(struct clk *clk) +static int clk_gpio27_enable(struct clk_hw *hw) { - return NULL; -} -EXPORT_SYMBOL(clk_get_parent); + unsigned long flags; -static void clk_gpio27_enable(struct clk *clk) -{ /* * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: * (SA-1110 Developer's Manual, section 9.1.2.1) */ + local_irq_save(flags); GAFR |= GPIO_32_768kHz; GPDR |= GPIO_32_768kHz; - TUCR = TUCR_3_6864MHz; + local_irq_restore(flags); + + return 0; } -static void clk_gpio27_disable(struct clk *clk) +static void clk_gpio27_disable(struct clk_hw *hw) { - TUCR = 0; + unsigned long flags; + + local_irq_save(flags); GPDR &= ~GPIO_32_768kHz; GAFR &= ~GPIO_32_768kHz; + local_irq_restore(flags); } -static void clk_cpu_enable(struct clk *clk) -{ -} +static const struct clk_ops clk_gpio27_ops = { + .enable = clk_gpio27_enable, + .disable = clk_gpio27_disable, +}; -static void clk_cpu_disable(struct clk *clk) -{ -} +static const char * const clk_gpio27_parents[] = { + "tucr-mux", +}; -static unsigned long clk_cpu_get_rate(struct clk *clk) +static const struct clk_init_data clk_gpio27_init_data __initconst = { + .name = "gpio27", + .ops = &clk_gpio27_ops, + .parent_names = clk_gpio27_parents, + .num_parents = ARRAY_SIZE(clk_gpio27_parents), +}; + +/* + * Derived from the table 8-1 in the SA1110 manual, the MPLL appears to + * multiply its input rate by 4 x (4 + PPCR). This calculation gives + * the exact rate. The figures given in the table are the rates rounded + * to 100kHz. Stick with sa11x0_getspeed() for the time being. + */ +static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw, + unsigned long prate) { return sa11x0_getspeed(0) * 1000; } -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - if (clk) { - spin_lock_irqsave(&clocks_lock, flags); - if (clk->enabled++ == 0) - clk->ops->enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - } - - return 0; -} -EXPORT_SYMBOL(clk_enable); +static const struct clk_ops clk_mpll_ops = { + .recalc_rate = clk_mpll_recalc_rate, +}; -void clk_disable(struct clk *clk) -{ - unsigned long flags; +static const char * const clk_mpll_parents[] = { + "clk3686400", +}; - if (clk) { - WARN_ON(clk->enabled == 0); - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->enabled == 0) - clk->ops->disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - } -} -EXPORT_SYMBOL(clk_disable); +static const struct clk_init_data clk_mpll_init_data __initconst = { + .name = "mpll", + .ops = &clk_mpll_ops, + .parent_names = clk_mpll_parents, + .num_parents = ARRAY_SIZE(clk_mpll_parents), + .flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL, +}; -unsigned long clk_get_rate(struct clk *clk) +int __init sa11xx_clk_init(void) { - if (clk && clk->ops && clk->ops->get_rate) - return clk->ops->get_rate(clk); - - return 0; -} -EXPORT_SYMBOL(clk_get_rate); + struct clk_hw *hw; + int ret; -const struct clkops clk_gpio27_ops = { - .enable = clk_gpio27_enable, - .disable = clk_gpio27_disable, -}; + hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768); + if (IS_ERR(hw)) + return PTR_ERR(hw); -const struct clkops clk_cpu_ops = { - .enable = clk_cpu_enable, - .disable = clk_cpu_disable, - .get_rate = clk_cpu_get_rate, -}; + clk_hw_register_clkdev(hw, NULL, "sa1100-rtc"); -static DEFINE_CLK(gpio27, &clk_gpio27_ops); + hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400); + if (IS_ERR(hw)) + return PTR_ERR(hw); -static DEFINE_CLK(cpu, &clk_cpu_ops); + clk_hw_register_clkdev(hw, "OSTIMER0", NULL); -static unsigned long clk_36864_get_rate(struct clk *clk) -{ - return 3686400; -} + hw = kzalloc(sizeof(*hw), GFP_KERNEL); + if (!hw) + return -ENOMEM; + hw->init = &clk_mpll_init_data; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(hw); + return ret; + } -static struct clkops clk_36864_ops = { - .enable = clk_cpu_enable, - .disable = clk_cpu_disable, - .get_rate = clk_36864_get_rate, -}; + clk_hw_register_clkdev(hw, NULL, "sa11x0-fb"); + clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia"); + clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0"); + clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1"); + clk_hw_register_clkdev(hw, NULL, "1800"); + + hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents, + ARRAY_SIZE(clk_tucr_parents), 0, + (void __iomem *)&TUCR, FShft(TUCR_TSEL), + FAlnMsk(TUCR_TSEL), 0, &tucr_lock); + clk_set_rate(hw->clk, 3686400); + + hw = kzalloc(sizeof(*hw), GFP_KERNEL); + if (!hw) + return -ENOMEM; + hw->init = &clk_gpio27_init_data; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(hw); + return ret; + } -static DEFINE_CLK(36864, &clk_36864_ops); - -static struct clk_lookup sa11xx_clkregs[] = { - CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), - CLKDEV_INIT("sa1100-rtc", NULL, NULL), - CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu), - CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu), - CLKDEV_INIT("sa11x0-pcmcia.0", NULL, &clk_cpu), - CLKDEV_INIT("sa11x0-pcmcia.1", NULL, &clk_cpu), - /* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */ - CLKDEV_INIT("1800", NULL, &clk_cpu), - CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864), -}; + clk_hw_register_clkdev(hw, NULL, "sa1111.0"); -int __init sa11xx_clk_init(void) -{ - clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); return 0; } -- cgit v1.2.3