From 4d9d18a560a50920691865c1efdad6577616eaa9 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 27 Aug 2013 14:50:00 +0200 Subject: ARM: imx: remove custom .init_time hook With arch/arm calling of_clk_init(NULL) from time_init(), we can now remove custom .init_time hooks. Signed-off-by: Sebastian Hesselbarth Acked-by: Shawn Guo --- arch/arm/mach-imx/clk-imx51-imx53.c | 29 ++++++++++------------------- arch/arm/mach-imx/common.h | 4 ---- arch/arm/mach-imx/imx51-dt.c | 6 ------ arch/arm/mach-imx/mach-imx53.c | 6 ------ arch/arm/mach-imx/mach-imx6q.c | 14 +++----------- arch/arm/mach-imx/mach-imx6sl.c | 7 ------- arch/arm/mach-imx/mach-vf610.c | 9 --------- 7 files changed, 13 insertions(+), 62 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 1a56a3319997..1b796db7652c 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -131,8 +132,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, { int i; - of_clk_init(NULL); - clk[dummy] = imx_clk_fixed("dummy", 0); clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); @@ -465,12 +464,16 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, return 0; } -int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, - unsigned long rate_ckih1, unsigned long rate_ckih2) +static void __init mx51_clocks_init_dt(struct device_node *np) +{ + mx51_clocks_init(0, 0, 0, 0); +} +CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); + +static void __init mx53_clocks_init(struct device_node *np) { int i; unsigned long r; - struct device_node *np; clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); @@ -529,12 +532,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, pr_err("i.MX53 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm"); clk_data.clks = clk; clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); + mx5_clocks_common_init(0, 0, 0, 0); clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); @@ -566,16 +568,5 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, r = clk_round_rate(clk[usboh3_per_gate], 54000000); clk_set_rate(clk[usboh3_per_gate], r); - - return 0; -} - -int __init mx51_clocks_init_dt(void) -{ - return mx51_clocks_init(0, 0, 0, 0); -} - -int __init mx53_clocks_init_dt(void) -{ - return mx53_clocks_init(0, 0, 0, 0); } +CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 4517fd760bfc..28e8ca0871e8 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -63,13 +63,9 @@ extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); -extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2); extern int mx25_clocks_init_dt(void); extern int mx27_clocks_init_dt(void); extern int mx31_clocks_init_dt(void); -extern int mx51_clocks_init_dt(void); -extern int mx53_clocks_init_dt(void); extern struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); extern void mxc_set_cpu_type(unsigned int type); diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index 53e43e579dd7..bece8a65e6f0 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c @@ -34,17 +34,11 @@ static const char *imx51_dt_board_compat[] __initdata = { NULL }; -static void __init imx51_timer_init(void) -{ - mx51_clocks_init_dt(); -} - DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") .map_io = mx51_map_io, .init_early = imx51_init_early, .init_irq = mx51_init_irq, .handle_irq = imx51_handle_irq, - .init_time = imx51_timer_init, .init_machine = imx51_dt_init, .init_late = imx51_init_late, .dt_compat = imx51_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 98c58944015a..c9c4d8d96931 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -36,17 +36,11 @@ static const char *imx53_dt_board_compat[] __initdata = { NULL }; -static void __init imx53_timer_init(void) -{ - mx53_clocks_init_dt(); -} - DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") .map_io = mx53_map_io, .init_early = imx53_init_early, .init_irq = mx53_init_irq, .handle_irq = imx53_handle_irq, - .init_time = imx53_timer_init, .init_machine = imx53_dt_init, .init_late = imx53_init_late, .dt_compat = imx53_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85a1b51346c8..47ebc36636a7 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -11,9 +11,7 @@ */ #include -#include #include -#include #include #include #include @@ -192,6 +190,9 @@ static void __init imx6q_1588_init(void) static void __init imx6q_init_machine(void) { + imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", + imx6q_revision()); + imx6q_enet_phy_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -288,14 +289,6 @@ static void __init imx6q_init_irq(void) irqchip_init(); } -static void __init imx6q_timer_init(void) -{ - of_clk_init(NULL); - clocksource_of_init(); - imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", - imx6q_revision()); -} - static const char *imx6q_dt_compat[] __initdata = { "fsl,imx6dl", "fsl,imx6q", @@ -306,7 +299,6 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq, - .init_time = imx6q_timer_init, .init_machine = imx6q_init_machine, .init_late = imx6q_init_late, .dt_compat = imx6q_dt_compat, diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 0d75dc54f715..c70bd7c64974 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include @@ -31,11 +30,6 @@ static void __init imx6sl_init_irq(void) irqchip_init(); } -static void __init imx6sl_timer_init(void) -{ - of_clk_init(NULL); -} - static const char *imx6sl_dt_compat[] __initdata = { "fsl,imx6sl", NULL, @@ -44,7 +38,6 @@ static const char *imx6sl_dt_compat[] __initdata = { DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") .map_io = debug_ll_io_init, .init_irq = imx6sl_init_irq, - .init_time = imx6sl_timer_init, .init_machine = imx6sl_init_machine, .dt_compat = imx6sl_dt_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index 816991deb9b8..af0cb8a9dc48 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c @@ -8,9 +8,7 @@ */ #include -#include #include -#include #include #include @@ -28,12 +26,6 @@ static void __init vf610_init_irq(void) irqchip_init(); } -static void __init vf610_init_time(void) -{ - of_clk_init(NULL); - clocksource_of_init(); -} - static const char *vf610_dt_compat[] __initdata = { "fsl,vf610", NULL, @@ -41,7 +33,6 @@ static const char *vf610_dt_compat[] __initdata = { DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)") .init_irq = vf610_init_irq, - .init_time = vf610_init_time, .init_machine = vf610_init_machine, .dt_compat = vf610_dt_compat, .restart = mxc_restart, -- cgit v1.2.3 From 25f73ed5c67d17ecf8cefd560f55211cce726086 Mon Sep 17 00:00:00 2001 From: Vivien Didelot Date: Fri, 27 Sep 2013 15:06:28 -0400 Subject: misc: (at24) move header to linux/platform_data/ This patch moves the at24.h header from include/linux/i2c to include/linux/platform_data and updates existing support accordingly. It also fixes the following checkpatch warning: WARNING: please, no space before tabs #436: FILE: include/linux/platform_data/at24.h:31: + * ^Iu8 *mac_addr = ethernet_pdata->mac_addr;$ Signed-off-by: Vivien Didelot Signed-off-by: Wolfram Sang --- MAINTAINERS | 2 +- arch/arm/mach-at91/board-sam9260ek.c | 2 +- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-davinci/board-da830-evm.c | 2 +- arch/arm/mach-davinci/board-da850-evm.c | 2 +- arch/arm/mach-davinci/board-dm365-evm.c | 2 +- arch/arm/mach-davinci/board-dm644x-evm.c | 2 +- arch/arm/mach-davinci/board-dm646x-evm.c | 2 +- arch/arm/mach-davinci/board-mityomapl138.c | 2 +- arch/arm/mach-davinci/board-sffsdr.c | 2 +- arch/arm/mach-imx/mach-pca100.c | 2 +- arch/arm/mach-imx/mach-pcm037.c | 2 +- arch/arm/mach-imx/mach-pcm038.c | 2 +- arch/arm/mach-imx/mach-pcm043.c | 2 +- arch/arm/mach-imx/mach-vpr200.c | 2 +- arch/arm/mach-kirkwood/lacie_v2-common.c | 2 +- arch/arm/mach-omap1/board-osk.c | 2 +- arch/arm/mach-omap2/board-cm-t35.c | 2 +- arch/arm/mach-omap2/board-h4.c | 2 +- arch/arm/mach-omap2/board-omap3stalker.c | 2 +- arch/arm/mach-pxa/stargate2.c | 2 +- arch/arm/mach-s3c24xx/mach-mini2440.c | 2 +- drivers/misc/eeprom/at24.c | 2 +- include/linux/i2c/at24.h | 55 ------------------------------ include/linux/platform_data/at24.h | 55 ++++++++++++++++++++++++++++++ 25 files changed, 78 insertions(+), 78 deletions(-) delete mode 100644 include/linux/i2c/at24.h create mode 100644 include/linux/platform_data/at24.h (limited to 'arch/arm/mach-imx') diff --git a/MAINTAINERS b/MAINTAINERS index 284969fa2896..b9d19a7f3144 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1396,7 +1396,7 @@ M: Wolfram Sang L: linux-i2c@vger.kernel.org S: Maintained F: drivers/misc/eeprom/at24.c -F: include/linux/i2c/at24.h +F: include/linux/platform_data/at24.h ATA OVER ETHERNET (AOE) DRIVER M: "Ed L. Cashin" diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index 0b153c87521d..f4f8735315da 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 3284df05df14..947e134ac4c3 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index c4bdc0a1c36e..66b5b3cb5376 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index dd1fb24521aa..f25a569b0009 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 92b7f770615a..30ee81fac925 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 40bb9b5b87e8..f21fde9dce00 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 2bc3651d56cc..db2df32da6a8 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index cd0f58730c2b..7aa105b1fd0f 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index d84360148100..41c7c9615791 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 19bb6441a7d4..c5f95674e9b7 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index bc0261e99d39..20cc53f4cee1 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index e805ac273e9c..592ddbe031ac 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -18,7 +18,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index b726cb1c5fdd..ac504b67326b 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 0910761e8280..8825d1217d18 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -29,7 +29,7 @@ #include #include -#include +#include #include #include "common.h" diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c index 489495976fcd..8e3e4331c380 100644 --- a/arch/arm/mach-kirkwood/lacie_v2-common.c +++ b/arch/arm/mach-kirkwood/lacie_v2-common.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index a7ce69286688..d68909b095f1 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -300,7 +300,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = { #ifdef CONFIG_OMAP_OSK_MISTRAL #include -#include +#include #include #include diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 33d159e2386e..8dd0ec858cf1 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 87e41a8b8d46..f7808349a734 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index ba8342fef799..119efaf5808a 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 62aea3e835f3..01de542432a6 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index a83db46320bc..4a18d49a63e0 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c index 5d4fd69d04ca..4ef01ab67853 100644 --- a/drivers/misc/eeprom/at24.c +++ b/drivers/misc/eeprom/at24.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include /* * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable. diff --git a/include/linux/i2c/at24.h b/include/linux/i2c/at24.h deleted file mode 100644 index 285025a9cdc9..000000000000 --- a/include/linux/i2c/at24.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * at24.h - platform_data for the at24 (generic eeprom) driver - * (C) Copyright 2008 by Pengutronix - * (C) Copyright 2012 by Wolfram Sang - * same license as the driver - */ - -#ifndef _LINUX_AT24_H -#define _LINUX_AT24_H - -#include -#include - -/** - * struct at24_platform_data - data to set up at24 (generic eeprom) driver - * @byte_len: size of eeprom in byte - * @page_size: number of byte which can be written in one go - * @flags: tunable options, check AT24_FLAG_* defines - * @setup: an optional callback invoked after eeprom is probed; enables kernel - code to access eeprom via memory_accessor, see example - * @context: optional parameter passed to setup() - * - * If you set up a custom eeprom type, please double-check the parameters. - * Especially page_size needs extra care, as you risk data loss if your value - * is bigger than what the chip actually supports! - * - * An example in pseudo code for a setup() callback: - * - * void get_mac_addr(struct memory_accessor *mem_acc, void *context) - * { - * u8 *mac_addr = ethernet_pdata->mac_addr; - * off_t offset = context; - * - * // Read MAC addr from EEPROM - * if (mem_acc->read(mem_acc, mac_addr, offset, ETH_ALEN) == ETH_ALEN) - * pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr); - * } - * - * This function pointer and context can now be set up in at24_platform_data. - */ - -struct at24_platform_data { - u32 byte_len; /* size (sum of all addr) */ - u16 page_size; /* for writes */ - u8 flags; -#define AT24_FLAG_ADDR16 0x80 /* address pointer is 16 bit */ -#define AT24_FLAG_READONLY 0x40 /* sysfs-entry will be read-only */ -#define AT24_FLAG_IRUGO 0x20 /* sysfs-entry will be world-readable */ -#define AT24_FLAG_TAKE8ADDR 0x10 /* take always 8 addresses (24c00) */ - - void (*setup)(struct memory_accessor *, void *context); - void *context; -}; - -#endif /* _LINUX_AT24_H */ diff --git a/include/linux/platform_data/at24.h b/include/linux/platform_data/at24.h new file mode 100644 index 000000000000..c42aa89d34ee --- /dev/null +++ b/include/linux/platform_data/at24.h @@ -0,0 +1,55 @@ +/* + * at24.h - platform_data for the at24 (generic eeprom) driver + * (C) Copyright 2008 by Pengutronix + * (C) Copyright 2012 by Wolfram Sang + * same license as the driver + */ + +#ifndef _LINUX_AT24_H +#define _LINUX_AT24_H + +#include +#include + +/** + * struct at24_platform_data - data to set up at24 (generic eeprom) driver + * @byte_len: size of eeprom in byte + * @page_size: number of byte which can be written in one go + * @flags: tunable options, check AT24_FLAG_* defines + * @setup: an optional callback invoked after eeprom is probed; enables kernel + code to access eeprom via memory_accessor, see example + * @context: optional parameter passed to setup() + * + * If you set up a custom eeprom type, please double-check the parameters. + * Especially page_size needs extra care, as you risk data loss if your value + * is bigger than what the chip actually supports! + * + * An example in pseudo code for a setup() callback: + * + * void get_mac_addr(struct memory_accessor *mem_acc, void *context) + * { + * u8 *mac_addr = ethernet_pdata->mac_addr; + * off_t offset = context; + * + * // Read MAC addr from EEPROM + * if (mem_acc->read(mem_acc, mac_addr, offset, ETH_ALEN) == ETH_ALEN) + * pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr); + * } + * + * This function pointer and context can now be set up in at24_platform_data. + */ + +struct at24_platform_data { + u32 byte_len; /* size (sum of all addr) */ + u16 page_size; /* for writes */ + u8 flags; +#define AT24_FLAG_ADDR16 0x80 /* address pointer is 16 bit */ +#define AT24_FLAG_READONLY 0x40 /* sysfs-entry will be read-only */ +#define AT24_FLAG_IRUGO 0x20 /* sysfs-entry will be world-readable */ +#define AT24_FLAG_TAKE8ADDR 0x10 /* take always 8 addresses (24c00) */ + + void (*setup)(struct memory_accessor *, void *context); + void *context; +}; + +#endif /* _LINUX_AT24_H */ -- cgit v1.2.3 From 07d8a49c263c89c21d1e10b5550706ed8a58eb5e Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 1 Oct 2013 11:08:56 +0200 Subject: ARM: drop explicit selection of HAVE_CLK and CLKDEV_LOOKUP CLKDEV_LOOKUP selects HAVE_CLK and COMMON_CLK selects CLKDEV_LOOKUP. So all symbols that select at least two of these symbols can be simplified. For imx, omap2 and ux500 some rearrangements were necessary before the simplification. Acked-by: Tony Lindgren Acked-by: Stephen Boyd Acked-by: Dinh Nguyen Acked-by: Nicolas Ferre Acked-by: Pawel Moll Acked-by: Linus Walleij Signed-off-by: Uwe Kleine-König Signed-off-by: Olof Johansson --- arch/arm/Kconfig | 12 ------------ arch/arm/mach-highbank/Kconfig | 1 - arch/arm/mach-imx/Kconfig | 10 +--------- arch/arm/mach-omap2/Kconfig | 9 +-------- arch/arm/mach-socfpga/Kconfig | 1 - arch/arm/mach-spear/Kconfig | 2 -- arch/arm/mach-tegra/Kconfig | 2 -- arch/arm/mach-u300/Kconfig | 1 - arch/arm/mach-ux500/Kconfig | 29 ++++++++++++----------------- arch/arm/mach-vexpress/Kconfig | 2 -- arch/arm/mach-vt8500/Kconfig | 1 - 11 files changed, 14 insertions(+), 56 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2b8faa337e8b..f55f7ac4b135 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -358,7 +358,6 @@ config ARCH_AT91 bool "Atmel AT91" select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP - select HAVE_CLK select IRQ_DOMAIN select NEED_MACH_GPIO_H select NEED_MACH_IO_H if PCCARD @@ -372,7 +371,6 @@ config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB select AUTO_ZRELADDR - select CLKDEV_LOOKUP select CLKSRC_MMIO select COMMON_CLK select CPU_ARM720T @@ -631,7 +629,6 @@ config ARCH_PXA config ARCH_MSM bool "Qualcomm MSM" select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP select CLKSRC_OF if OF select COMMON_CLK select GENERIC_CLOCKEVENTS @@ -649,7 +646,6 @@ config ARCH_SHMOBILE select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_CLK select HAVE_MACH_CLKDEV select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 @@ -706,7 +702,6 @@ config ARCH_S3C24XX select CLKSRC_SAMSUNG_PWM select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -730,7 +725,6 @@ config ARCH_S3C64XX select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_TCM @@ -754,7 +748,6 @@ config ARCH_S5P64X0 select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -773,7 +766,6 @@ config ARCH_S5PC100 select CPU_V7 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -793,7 +785,6 @@ config ARCH_S5PV210 select CPU_V7 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -810,11 +801,9 @@ config ARCH_EXYNOS select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE select ARM_GIC - select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -851,7 +840,6 @@ config ARCH_OMAP1 select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select HAVE_CLK select HAVE_IDE select IRQ_DOMAIN select NEED_MACH_IO_H if PCCARD diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index 8e8437dea3ce..616408d76be5 100644 --- a/arch/arm/mach-highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig @@ -12,7 +12,6 @@ config ARCH_HIGHBANK select ARM_GIC select ARM_TIMER_SP804 select CACHE_L2X0 - select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 29a8af6922a8..a91909b95601 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -4,8 +4,8 @@ config ARCH_MXC select ARM_CPU_SUSPEND if PM select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR if !ZBOOT_ROM - select CLKDEV_LOOKUP select CLKSRC_MMIO + select COMMON_CLK select GENERIC_ALLOCATOR select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP @@ -92,14 +92,12 @@ config MACH_MX27 config SOC_IMX1 bool select ARCH_MX1 - select COMMON_CLK select CPU_ARM920T select IMX_HAVE_IOMUX_V1 select MXC_AVIC config SOC_IMX21 bool - select COMMON_CLK select CPU_ARM926T select IMX_HAVE_IOMUX_V1 select MXC_AVIC @@ -108,7 +106,6 @@ config SOC_IMX25 bool select ARCH_MX25 select ARCH_MXC_IOMUX_V3 - select COMMON_CLK select CPU_ARM926T select MXC_AVIC @@ -116,7 +113,6 @@ config SOC_IMX27 bool select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP - select COMMON_CLK select CPU_ARM926T select IMX_HAVE_IOMUX_V1 select MACH_MX27 @@ -124,7 +120,6 @@ config SOC_IMX27 config SOC_IMX31 bool - select COMMON_CLK select CPU_V6 select IMX_HAVE_PLATFORM_MXC_RNGA select MXC_AVIC @@ -133,7 +128,6 @@ config SOC_IMX31 config SOC_IMX35 bool select ARCH_MXC_IOMUX_V3 - select COMMON_CLK select CPU_V6K select HAVE_EPIT select MXC_AVIC @@ -144,7 +138,6 @@ config SOC_IMX5 select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP select ARCH_MXC_IOMUX_V3 - select COMMON_CLK select CPU_V7 select MXC_TZIC @@ -791,7 +784,6 @@ config SOC_IMX6Q select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 select ARM_GIC - select COMMON_CLK select CPU_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b5fb5f7992df..c94624429680 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -8,7 +8,6 @@ config ARCH_OMAP2 select CPU_V6 select MULTI_IRQ_HANDLER select SOC_HAS_OMAP2_SDRC - select COMMON_CLK config ARCH_OMAP3 bool "TI OMAP3" @@ -22,7 +21,6 @@ config ARCH_OMAP3 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select SOC_HAS_OMAP2_SDRC - select COMMON_CLK select USB_ARCH_HAS_EHCI if USB_SUPPORT config ARCH_OMAP4 @@ -45,7 +43,6 @@ config ARCH_OMAP4 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select USB_ARCH_HAS_EHCI if USB_SUPPORT - select COMMON_CLK select ARM_ERRATA_754322 select ARM_ERRATA_775420 @@ -59,7 +56,6 @@ config SOC_OMAP5 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP - select COMMON_CLK select HAVE_ARM_ARCH_TIMER select ARM_ERRATA_798181 if SMP @@ -70,7 +66,6 @@ config SOC_AM33XX select ARM_CPU_SUSPEND if PM select CPU_V7 select MULTI_IRQ_HANDLER - select COMMON_CLK config SOC_AM43XX bool "TI AM43x" @@ -79,7 +74,6 @@ config SOC_AM43XX select ARCH_OMAP2PLUS select MULTI_IRQ_HANDLER select ARM_GIC - select COMMON_CLK select MACH_OMAP_GENERIC config ARCH_OMAP2PLUS @@ -89,11 +83,10 @@ config ARCH_OMAP2PLUS select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_OMAP select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP select CLKSRC_MMIO + select COMMON_CLK select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select HAVE_CLK select OMAP_DM_TIMER select PINCTRL select PROC_DEVICETREE if PROC_FS diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index dd86db467521..037100a1563a 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -4,7 +4,6 @@ config ARCH_SOCFPGA select ARM_AMBA select ARM_GIC select CACHE_L2X0 - select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select DW_APB_TIMER_OF diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig index df0d59afeb40..ac1710e64d9a 100644 --- a/arch/arm/mach-spear/Kconfig +++ b/arch/arm/mach-spear/Kconfig @@ -7,11 +7,9 @@ menuconfig PLAT_SPEAR default PLAT_SPEAR_SINGLE select ARCH_REQUIRE_GPIOLIB select ARM_AMBA - select CLKDEV_LOOKUP select CLKSRC_MMIO select COMMON_CLK select GENERIC_CLOCKEVENTS - select HAVE_CLK if PLAT_SPEAR diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 67a76f2dfb9f..0c2f44aed404 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -3,7 +3,6 @@ config ARCH_TEGRA select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select ARM_GIC - select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK @@ -11,7 +10,6 @@ config ARCH_TEGRA select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index a1659863bfd5..8e23071bd1b3 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -5,7 +5,6 @@ config ARCH_U300 select ARM_AMBA select ARM_PATCH_PHYS_VIRT select ARM_VIC - select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 99a28d628297..c67f8ad5ccd5 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -1,37 +1,32 @@ config ARCH_U8500 bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7 depends on MMU + select AB8500_CORE + select ABX500_CORE select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select ARM_AMBA - select CLKDEV_LOOKUP + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select ARM_GIC + select CACHE_L2X0 + select CLKSRC_NOMADIK_MTU + select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 + select PINCTRL + select PINCTRL_ABX500 + select PINCTRL_NOMADIK + select PL310_ERRATA_753970 if CACHE_PL310 help Support for ST-Ericsson's Ux500 architecture if ARCH_U8500 -config UX500_SOC_COMMON - bool - default y - select ABX500_CORE - select AB8500_CORE - select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP - select ARM_GIC - select CACHE_L2X0 - select CLKSRC_NOMADIK_MTU - select COMMON_CLK - select PINCTRL - select PINCTRL_NOMADIK - select PINCTRL_ABX500 - select PL310_ERRATA_753970 if CACHE_PL310 - config UX500_SOC_DB8500 bool select CPU_FREQ_TABLE if CPU_FREQ diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 365795447804..d7e7422527ca 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -4,14 +4,12 @@ config ARCH_VEXPRESS select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 - select CLKDEV_LOOKUP select COMMON_CLK select COMMON_CLK_VERSATILE select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_CLK select HAVE_PATA_PLATFORM select HAVE_SMP select ICST diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig index 9b252934b206..927be93b692e 100644 --- a/arch/arm/mach-vt8500/Kconfig +++ b/arch/arm/mach-vt8500/Kconfig @@ -5,7 +5,6 @@ config ARCH_VT8500 select CLKDEV_LOOKUP select CLKSRC_OF select GENERIC_CLOCKEVENTS - select HAVE_CLK select VT8500_TIMER select PINCTRL help -- cgit v1.2.3 From 64990a431469a58b2949aca5be9d69e220d53892 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Fri, 23 Aug 2013 19:20:34 +0800 Subject: ARM: imx6q: Add pll4_audio_div to clock tree There's a pll4_audio_div clock, an extra divider for pll4, missing in current clock tree, thus add it. Signed-off-by: Nicolin Chen Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/clock/imx6q-clock.txt | 1 + arch/arm/mach-imx/clk-imx6q.c | 9 +++++---- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index 5a90a724b520..e8b1baae9ae4 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -215,6 +215,7 @@ clocks and IDs. cko2 200 cko 201 vdoa 202 + pll4_audio_div 203 Examples: diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 9181a241d3a8..913ad85ad621 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -182,7 +182,7 @@ static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; -static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; +static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; @@ -196,7 +196,7 @@ static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; static const char *pcie_axi_sels[] = { "axi", "ahb", }; -static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", }; +static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; @@ -205,7 +205,7 @@ static const char *vdo_axi_sels[] = { "axi", "ahb", }; static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", - "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; + "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; static const char *cko2_sels[] = { "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", @@ -251,7 +251,7 @@ enum mx6q_clks { ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, - spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max + spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max }; static struct clk *clk[clk_max]; @@ -359,6 +359,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); + clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); -- cgit v1.2.3 From a9aec30dcf2aae5929bc43ada552a33c8d737967 Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Wed, 4 Sep 2013 10:58:17 +0800 Subject: ARM: imx6sl: config iomux-gpr1 to select clock for fec Config iomux-gpr1 to select clock source for fec system clock. Clear gpr1[14], gpr1[18-17] bit to select the fec clock source from internal anatop PLL. Signed-off-by: Fugang Duan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6sl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index c70bd7c64974..21cde21daf9b 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -10,16 +10,37 @@ #include #include #include +#include +#include +#include #include #include #include "common.h" +static void __init imx6sl_fec_init(void) +{ + struct regmap *gpr; + + /* set FEC clock from internal PLL clock source */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + regmap_update_bits(gpr, IOMUXC_GPR1, + IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0); + regmap_update_bits(gpr, IOMUXC_GPR1, + IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0); + } else { + pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n"); + } +} + static void __init imx6sl_init_machine(void) { mxc_arch_reset_init_dt(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + + imx6sl_fec_init(); } static void __init imx6sl_init_irq(void) -- cgit v1.2.3 From 4c1dd3e5edc1619199b4a42618169ac3ac457cb5 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 4 Sep 2013 07:04:39 +0200 Subject: ARM: imx: remove IRQF_DISABLED This flag is a NOOP since 2.6.35 and can be removed. This is an update for 3.11 of a patch already sent for 3.10 Signed-off-by: Michael Opdenacker Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 2 +- arch/arm/mach-imx/epit.c | 2 +- arch/arm/mach-imx/mach-armadillo5x0.c | 3 +-- arch/arm/mach-imx/mach-mx31_3ds.c | 2 +- arch/arm/mach-imx/mach-pcm037.c | 3 +-- arch/arm/mach-imx/mx31lilly-db.c | 3 +-- arch/arm/mach-imx/time.c | 2 +- 7 files changed, 7 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 29a8af6922a8..9f67338ac2ee 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -24,7 +24,7 @@ config MXC_IRQ_PRIOR help Select this if you want to use prioritized IRQ handling. This feature prevents higher priority ISR to be interrupted - by lower priority IRQ even IRQF_DISABLED flag is not set. + by lower priority IRQ. This may be useful in embedded applications, where are strong requirements for timing. Say N here, unless you have a specialized requirement. diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c index e02de188ae83..074b1a81ba76 100644 --- a/arch/arm/mach-imx/epit.c +++ b/arch/arm/mach-imx/epit.c @@ -171,7 +171,7 @@ static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) static struct irqaction epit_timer_irq = { .name = "i.MX EPIT Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = epit_timer_interrupt, }; diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index 368a6e3f5926..58b864a3fc20 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c @@ -404,8 +404,7 @@ static int armadillo5x0_sdhc1_init(struct device *dev, /* When supported the trigger type have to be BOTH */ ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), - detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, + detect_irq, IRQF_TRIGGER_FALLING, "sdhc-detect", data); if (ret) diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 1ed916175d41..50044a21b388 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -311,7 +311,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev, } ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), - detect_irq, IRQF_DISABLED | + detect_irq, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-detect", data); if (ret) { diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index bc0261e99d39..45303bd62902 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -371,8 +371,7 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, #endif ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "sdhc-detect", data); + IRQF_TRIGGER_FALLING, "sdhc-detect", data); if (ret) goto err_gpio_free_2; diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c index d4361b80c5fb..649fe49ce85e 100644 --- a/arch/arm/mach-imx/mx31lilly-db.c +++ b/arch/arm/mach-imx/mx31lilly-db.c @@ -130,8 +130,7 @@ static int mxc_mmc1_init(struct device *dev, gpio_direction_input(gpio_wp); ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), - detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, + detect_irq, IRQF_TRIGGER_FALLING, "MMC detect", data); if (ret) goto exit_free_wp; diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index cd46529e9eaa..9b6638aadeaa 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -250,7 +250,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) static struct irqaction mxc_timer_irq = { .name = "i.MX Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = mxc_timer_interrupt, }; -- cgit v1.2.3 From bfefdff8f91aa0a9ff1291d18d54498af276a6e5 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 13 Aug 2013 13:54:02 +0800 Subject: ARM: imx: add soc revision helper functions Similar to what we do for cpu type, the patch adds helper functions imx_set_soc_revision() and imx_get_soc_revision() to maintain imx_soc_revision in cpu.c. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/cpu.c | 12 ++++++++++++ 2 files changed, 14 insertions(+) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 28e8ca0871e8..6ac25f68a6bc 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -77,6 +77,8 @@ extern int imx6q_revision(void); extern int mx53_display_revision(void); extern void imx_set_aips(void __iomem *); extern int mxc_device_init(void); +void imx_set_soc_revision(unsigned int rev); +unsigned int imx_get_soc_revision(void); enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index e70e3acbf9bd..51f6c51ca878 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -8,11 +8,23 @@ unsigned int __mxc_cpu_type; EXPORT_SYMBOL(__mxc_cpu_type); +static unsigned int imx_soc_revision; + void mxc_set_cpu_type(unsigned int type) { __mxc_cpu_type = type; } +void imx_set_soc_revision(unsigned int rev) +{ + imx_soc_revision = rev; +} + +unsigned int imx_get_soc_revision(void) +{ + return imx_soc_revision; +} + void imx_print_silicon_rev(const char *cpu, int srev) { if (srev == IMX_CHIP_REVISION_UNKNOWN) -- cgit v1.2.3 From 3f75978b3742157853618c5c6dd4a5f49aa950b1 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 13 Aug 2013 14:10:29 +0800 Subject: ARM: imx6q: use common soc revision helpers It calls imx_set_soc_revision() to set up soc revision in imx6q_init_revision(), and replaces all the occurrences of imx6q_revision() with common helper imx_get_soc_revision(). Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 5 +++-- arch/arm/mach-imx/common.h | 1 - arch/arm/mach-imx/mach-imx6q.c | 13 ++++--------- 3 files changed, 7 insertions(+), 12 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 913ad85ad621..c68156621cc8 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -300,7 +300,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) WARN_ON(!base); /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ - if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) { + if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { post_div_table[1].div = 1; post_div_table[2].div = 1; video_div_table[1].div = 1; @@ -574,7 +574,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); - if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { + if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || + cpu_is_imx6dl()) { clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); } diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 6ac25f68a6bc..cac12870efb3 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -73,7 +73,6 @@ extern void mxc_restart(enum reboot_mode, const char *); extern void mxc_arch_reset_init(void __iomem *); extern void mxc_arch_reset_init_dt(void); extern int mx53_revision(void); -extern int imx6q_revision(void); extern int mx53_display_revision(void); extern void imx_set_aips(void __iomem *); extern int mxc_device_init(void); diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 3be0fa0e9796..f260aad9850b 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -38,16 +38,10 @@ #include "cpuidle.h" #include "hardware.h" -static u32 chip_revision; - -int imx6q_revision(void) -{ - return chip_revision; -} - static void __init imx6q_init_revision(void) { u32 rev = imx_anatop_get_digprog(); + u32 chip_revision; switch (rev & 0xff) { case 0: @@ -64,6 +58,7 @@ static void __init imx6q_init_revision(void) } mxc_set_cpu_type(rev >> 16 & 0xff); + imx_set_soc_revision(chip_revision); } static void imx6q_restart(enum reboot_mode mode, const char *cmd) @@ -191,7 +186,7 @@ static void __init imx6q_1588_init(void) static void __init imx6q_init_machine(void) { imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", - imx6q_revision()); + imx_get_soc_revision()); imx6q_enet_phy_init(); @@ -270,7 +265,7 @@ static void __init imx6q_init_late(void) * WAIT mode is broken on TO 1.0 and 1.1, so there is no point * to run cpuidle on them. */ - if (imx6q_revision() > IMX_CHIP_REVISION_1_1) + if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) imx6q_cpuidle_init(); if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { -- cgit v1.2.3 From f1c6f314727c7595e249c7da3933ba2bc6219e58 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 13 Aug 2013 14:59:43 +0800 Subject: ARM: imx: add a common function to initialize revision from anatop The patch creates a common function imx_init_revision_from_anatop() by merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any SoC that encodes revision info in anatop can use it to initialize revision. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/anatop.c | 27 +++++++++++++++++++++------ arch/arm/mach-imx/common.h | 2 +- arch/arm/mach-imx/mach-imx6q.c | 25 +------------------------ 3 files changed, 23 insertions(+), 31 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index ad3b755abb78..b2d600f14937 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -16,6 +16,7 @@ #include #include #include "common.h" +#include "hardware.h" #define REG_SET 0x4 #define REG_CLR 0x8 @@ -76,21 +77,35 @@ static void imx_anatop_usb_chrg_detect_disable(void) BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); } -u32 imx_anatop_get_digprog(void) +void __init imx_init_revision_from_anatop(void) { struct device_node *np; void __iomem *anatop_base; - static u32 digprog; - - if (digprog) - return digprog; + unsigned int revision; + u32 digprog; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); WARN_ON(!anatop_base); digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG); + iounmap(anatop_base); + + switch (digprog & 0xff) { + case 0: + revision = IMX_CHIP_REVISION_1_0; + break; + case 1: + revision = IMX_CHIP_REVISION_1_1; + break; + case 2: + revision = IMX_CHIP_REVISION_1_2; + break; + default: + revision = IMX_CHIP_REVISION_UNKNOWN; + } - return digprog; + mxc_set_cpu_type(digprog >> 16 & 0xff); + imx_set_soc_revision(revision); } void __init imx_anatop_init(void) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index cac12870efb3..d0191152807d 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -78,6 +78,7 @@ extern void imx_set_aips(void __iomem *); extern int mxc_device_init(void); void imx_set_soc_revision(unsigned int rev); unsigned int imx_get_soc_revision(void); +void imx_init_revision_from_anatop(void); enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ @@ -134,7 +135,6 @@ extern void imx_gpc_restore_all(void); extern void imx_anatop_init(void); extern void imx_anatop_pre_suspend(void); extern void imx_anatop_post_resume(void); -extern u32 imx_anatop_get_digprog(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); extern void imx6q_set_chicken_bit(void); diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index f260aad9850b..1bdd0be429b9 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -38,29 +38,6 @@ #include "cpuidle.h" #include "hardware.h" -static void __init imx6q_init_revision(void) -{ - u32 rev = imx_anatop_get_digprog(); - u32 chip_revision; - - switch (rev & 0xff) { - case 0: - chip_revision = IMX_CHIP_REVISION_1_0; - break; - case 1: - chip_revision = IMX_CHIP_REVISION_1_1; - break; - case 2: - chip_revision = IMX_CHIP_REVISION_1_2; - break; - default: - chip_revision = IMX_CHIP_REVISION_UNKNOWN; - } - - mxc_set_cpu_type(rev >> 16 & 0xff); - imx_set_soc_revision(chip_revision); -} - static void imx6q_restart(enum reboot_mode mode, const char *cmd) { struct device_node *np; @@ -282,7 +259,7 @@ static void __init imx6q_map_io(void) static void __init imx6q_init_irq(void) { - imx6q_init_revision(); + imx_init_revision_from_anatop(); imx_init_l2cache(); imx_src_init(); imx_gpc_init(); -- cgit v1.2.3 From d8ce823fb34e6b50b1d9cb804c1067546eab9cee Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 13 Aug 2013 16:54:05 +0800 Subject: ARM: imx: use imx_init_revision_from_anatop() on imx6sl Add imx6sl support into imx_init_revision_from_anatop(), so that it can be used to initialize cpu type and revision on imx6sl. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 4 +++- arch/arm/mach-imx/anatop.c | 6 +++++- arch/arm/mach-imx/mach-imx6sl.c | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c46651e4d966..177d9e791a01 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -380,7 +380,9 @@ }; anatop: anatop@020c8000 { - compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus"; + compatible = "fsl,imx6sl-anatop", + "fsl,imx6q-anatop", + "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index b2d600f14937..4a40bbb46183 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -27,6 +27,7 @@ #define ANADIG_USB1_CHRG_DETECT 0x1b0 #define ANADIG_USB2_CHRG_DETECT 0x210 #define ANADIG_DIGPROG 0x260 +#define ANADIG_DIGPROG_IMX6SL 0x280 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 @@ -83,11 +84,14 @@ void __init imx_init_revision_from_anatop(void) void __iomem *anatop_base; unsigned int revision; u32 digprog; + u16 offset = ANADIG_DIGPROG; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); WARN_ON(!anatop_base); - digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG); + if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) + offset = ANADIG_DIGPROG_IMX6SL; + digprog = readl_relaxed(anatop_base + offset); iounmap(anatop_base); switch (digprog & 0xff) { diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 21cde21daf9b..4ce9ae58ed0c 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -45,6 +45,7 @@ static void __init imx6sl_init_machine(void) static void __init imx6sl_init_irq(void) { + imx_init_revision_from_anatop(); imx_init_l2cache(); imx_src_init(); imx_gpc_init(); -- cgit v1.2.3 From a28875462bd493fc1bb041c21f811b4a0577a497 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 13 Aug 2013 16:59:28 +0800 Subject: ARM: imx6: report soc info via soc device The patch enables soc bus infrastructure and adds a function imx_soc_device_init() to report soc info via soc device interface for imx6qdl and imx6sl. With the support, user space can get soc related info by looking at sysfs like below. $ cat /sys/devices/soc0/machine Freescale i.MX6 Quad SABRE Smart Device Board $ cat /sys/devices/soc0/family Freescale i.MX $ cat /sys/devices/soc0/soc_id i.MX6Q $ cat /sys/devices/soc0/revision 1.2 Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 1 + arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/cpu.c | 81 +++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mach-imx6q.c | 8 +++- arch/arm/mach-imx/mach-imx6sl.c | 8 +++- arch/arm/mach-imx/mxc.h | 1 + 6 files changed, 98 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 9f67338ac2ee..e0179158aec6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -11,6 +11,7 @@ config ARCH_MXC select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 select MULTI_IRQ_HANDLER + select SOC_BUS select SPARSE_IRQ select USE_OF help diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index d0191152807d..f9d01142a4f6 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -79,6 +79,7 @@ extern int mxc_device_init(void); void imx_set_soc_revision(unsigned int rev); unsigned int imx_get_soc_revision(void); void imx_init_revision_from_anatop(void); +struct device *imx_soc_device_init(void); enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 51f6c51ca878..fae2c9a78744 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -1,6 +1,9 @@ #include #include +#include +#include +#include #include "hardware.h" #include "common.h" @@ -56,3 +59,81 @@ void __init imx_set_aips(void __iomem *base) reg = __raw_readl(base + 0x50) & 0x00FFFFFF; __raw_writel(reg, base + 0x50); } + +struct device * __init imx_soc_device_init(void) +{ + struct soc_device_attribute *soc_dev_attr; + struct soc_device *soc_dev; + struct device_node *root; + const char *soc_id; + int ret; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return NULL; + + soc_dev_attr->family = "Freescale i.MX"; + + root = of_find_node_by_path("/"); + ret = of_property_read_string(root, "model", &soc_dev_attr->machine); + of_node_put(root); + if (ret) + goto free_soc; + + switch (__mxc_cpu_type) { + case MXC_CPU_MX1: + soc_id = "i.MX1"; + break; + case MXC_CPU_MX21: + soc_id = "i.MX21"; + break; + case MXC_CPU_MX25: + soc_id = "i.MX25"; + break; + case MXC_CPU_MX27: + soc_id = "i.MX27"; + break; + case MXC_CPU_MX31: + soc_id = "i.MX31"; + break; + case MXC_CPU_MX35: + soc_id = "i.MX35"; + break; + case MXC_CPU_MX51: + soc_id = "i.MX51"; + break; + case MXC_CPU_MX53: + soc_id = "i.MX53"; + break; + case MXC_CPU_IMX6SL: + soc_id = "i.MX6SL"; + break; + case MXC_CPU_IMX6DL: + soc_id = "i.MX6DL"; + break; + case MXC_CPU_IMX6Q: + soc_id = "i.MX6Q"; + break; + default: + soc_id = "Unknown"; + } + soc_dev_attr->soc_id = soc_id; + + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", + (imx_soc_revision >> 4) & 0xf, + imx_soc_revision & 0xf); + if (!soc_dev_attr->revision) + goto free_soc; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) + goto free_rev; + + return soc_device_to_device(soc_dev); + +free_rev: + kfree(soc_dev_attr->revision); +free_soc: + kfree(soc_dev_attr); + return NULL; +} diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 1bdd0be429b9..049e36edc143 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -162,12 +162,18 @@ static void __init imx6q_1588_init(void) static void __init imx6q_init_machine(void) { + struct device *parent; + imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", imx_get_soc_revision()); + parent = imx_soc_device_init(); + if (parent == NULL) + pr_warn("failed to initialize soc device\n"); + imx6q_enet_phy_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); imx_anatop_init(); imx6q_pm_init(); diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 4ce9ae58ed0c..f01aaabd3254 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -36,9 +36,15 @@ static void __init imx6sl_fec_init(void) static void __init imx6sl_init_machine(void) { + struct device *parent; + mxc_arch_reset_init_dt(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + parent = imx_soc_device_init(); + if (parent == NULL) + pr_warn("failed to initialize soc device\n"); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); imx6sl_fec_init(); } diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 8629e5be7ecd..99e03ea9bf79 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -34,6 +34,7 @@ #define MXC_CPU_MX35 35 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 +#define MXC_CPU_IMX6SL 0x60 #define MXC_CPU_IMX6DL 0x61 #define MXC_CPU_IMX6Q 0x63 -- cgit v1.2.3 From 7655fe53f4d39379d3f619e1ed49c79aba4d319b Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 25 Sep 2013 21:30:42 +0800 Subject: ARM: imx: remove stale mx53_display_revision() declaration The mx53_display_revision() declaration in common.h is stale and used nowhere, so remove it. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index f9d01142a4f6..d04ed7e8d8d3 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -73,7 +73,6 @@ extern void mxc_restart(enum reboot_mode, const char *); extern void mxc_arch_reset_init(void __iomem *); extern void mxc_arch_reset_init_dt(void); extern int mx53_revision(void); -extern int mx53_display_revision(void); extern void imx_set_aips(void __iomem *); extern int mxc_device_init(void); void imx_set_soc_revision(unsigned int rev); -- cgit v1.2.3 From bf22172158cd6dcc5be6dc286ff5c33794dd0ae8 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Mon, 16 Sep 2013 08:20:52 +0000 Subject: ARM: imx: Add LVDS general-purpose clocks to i.MX6Q The i.MX6 has two general-purpose LVDS clocks that can be driven from a variety of sources. This patch adds a mux and a gate for both of these clocks. Signed-off-by: Sean Cross Signed-off-by: Shawn Guo --- .../devicetree/bindings/clock/imx6q-clock.txt | 4 ++++ arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index e8b1baae9ae4..6aab72bf67ea 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -216,6 +216,10 @@ clocks and IDs. cko 201 vdoa 202 pll4_audio_div 203 + lvds1_sel 204 + lvds2_sel 205 + lvds1_gate 206 + lvds2_gate 207 Examples: diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index c68156621cc8..e8e5bad82b30 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -217,6 +217,11 @@ static const char *cko2_sels[] = { "uart_serial", "spdif", "asrc", "hsi_tx", }; static const char *cko_sels[] = { "cko1", "cko2", }; +static const char *lvds_sels[] = { + "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", + "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", + "pcie_ref", "sata_ref", +}; enum mx6q_clks { dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, @@ -251,7 +256,8 @@ enum mx6q_clks { ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, - spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max + spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, + lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max }; static struct clk *clk[clk_max]; @@ -342,6 +348,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); + clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); + clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); + + /* + * lvds1_gate and lvds2_gate are pseudo-gates. Both can be + * independently configured as clock inputs or outputs. We treat + * the "output_enable" bit as a gate, even though it's really just + * enabling clock output. + */ + clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); + clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); + /* name parent_name reg idx */ clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); -- cgit v1.2.3 From 74b8031307c5d33d36742c26dd0921991bd5a255 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Thu, 26 Sep 2013 10:45:35 +0800 Subject: ARM: imx6q: clock and Kconfig update for PCIe support Update imx6q clock initialization and Kconfig for PCIe support. Signed-off-by: Sean Cross Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 2 ++ arch/arm/mach-imx/clk-imx6q.c | 4 ++++ 2 files changed, 6 insertions(+) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index e0179158aec6..270f78667dc6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -802,6 +802,8 @@ config SOC_IMX6Q select HAVE_IMX_SRC select HAVE_SMP select MFD_SYSCON + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI select PINCTRL select PINCTRL_IMX6Q select PL310_ERRATA_588369 if CACHE_PL310 diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index e8e5bad82b30..07bc0d8b573f 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -623,6 +623,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if (ret) pr_warn("failed to set up CLKO: %d\n", ret); + /* All existing boards with PCIe use LVDS1 */ + if (IS_ENABLED(CONFIG_PCI_IMX6)) + clk_set_parent(clk[lvds1_sel], clk[sata_ref]); + /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); -- cgit v1.2.3 From 1ddd35be8b71855329c4c7e8910b00fd2bc0f6dc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 30 Sep 2013 14:04:51 +0200 Subject: ARM: imx: Include linux/err.h The IS_ERR() macro is defined in the linux/err.h header file, so include it explicitly. Signed-off-by: Thierry Reding Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index fae2c9a78744..ba3b498a67ec 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -1,4 +1,4 @@ - +#include #include #include #include -- cgit v1.2.3 From bfcc7bcef55dd9db82758f3ac755714a59db9529 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 1 Oct 2013 00:21:12 -0300 Subject: ARM: mach-imx: clk-imx51-imx53: Retrieve base address and irq from dt As mx53 is a dt-only SoC, we should retrieve the gpt base address and irq from the device tree, instead of using the old MX53_IO_ADDRESS method. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx51-imx53.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index ceaac9cd7b42..ce37af26ff8c 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -14,6 +14,9 @@ #include #include #include +#include +#include +#include #include "crm-regs-imx5.h" #include "clk.h" @@ -472,8 +475,9 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); static void __init mx53_clocks_init(struct device_node *np) { - int i; + int i, irq; unsigned long r; + void __iomem *base; clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); @@ -559,14 +563,17 @@ static void __init mx53_clocks_init(struct device_node *np) clk_set_rate(clk[esdhc_a_podf], 200000000); clk_set_rate(clk[esdhc_b_podf], 200000000); - /* System timer */ - mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT); - clk_prepare_enable(clk[iim_gate]); imx_print_silicon_rev("i.MX53", mx53_revision()); clk_disable_unprepare(clk[iim_gate]); r = clk_round_rate(clk[usboh3_per_gate], 54000000); clk_set_rate(clk[usboh3_per_gate], r); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); + base = of_iomap(np, 0); + WARN_ON(!base); + irq = irq_of_parse_and_map(np, 0); + mxc_timer_init(base, irq); } CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); -- cgit v1.2.3 From 823b2fe25a96715ceed9f689869e702c4dd3907a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 1 Oct 2013 00:21:13 -0300 Subject: ARM: mach-imx: mm-imx5: Retrieve tzic base address from dt As mx53 is a dt-only SoC, we should retrieve the tzic base address from the device tree, instead of using the old MX53_IO_ADDRESS method. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mm-imx5.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index eb3cce38c70d..2cafcf00000b 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -15,6 +15,7 @@ #include #include #include +#include #include @@ -100,7 +101,14 @@ void __init mx51_init_irq(void) void __init mx53_init_irq(void) { - tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); + struct device_node *np; + void __iomem *base; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic"); + base = of_iomap(np, 0); + WARN_ON(!base); + + tzic_init_irq(base); } static struct sdma_platform_data imx51_sdma_pdata __initdata = { -- cgit v1.2.3 From 6fc6c93eb6d07cb622c2ec2e956875c00ef47df3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 1 Oct 2013 00:21:14 -0300 Subject: ARM: mach-imx: mm-imx5: Retrieve iomuxc base address from dt As mx53 is a dt-only SoC, we should retrieve the iomuxc base address from the device tree, instead of using the old MX53_IO_ADDRESS method. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mm-imx5.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 2cafcf00000b..d1d52600f458 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -89,8 +89,15 @@ void __init imx51_init_early(void) void __init imx53_init_early(void) { + struct device_node *np; + void __iomem *base; + mxc_set_cpu_type(MXC_CPU_MX53); - mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc"); + base = of_iomap(np, 0); + WARN_ON(!base); + mxc_iomux_v3_init(base); imx_src_init(); } -- cgit v1.2.3 From 87a84b69824d7fd63b20f3bc98d75c0238b8e7d0 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 6 Oct 2013 16:47:46 +0800 Subject: ARM: imx: replace imx6q_restart() with mxc_restart() The imx6q_restart() works fine with normal reboot but will run into problem with emergency reboot like sysrq-b. In that case, of_iomap() gets called from interrupt context and hence triggers the BUG_ON in __get_vm_area_node(). Actually, since commit c1e31d1 (ARM: imx: create mxc_arch_reset_init_dt() for DT boot), imx6q/dl should try to use mxc_restart() by calling mxc_arch_reset_init_dt() beforehand, where things like of_iomap() can be done. The patch updates mxc_restart() a little bit to get it work for imx6q/dl and kill imx6q_restart() completely. Reported-by: Nathan Lynch Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 4 ++++ arch/arm/mach-imx/mach-imx6q.c | 35 +++-------------------------------- arch/arm/mach-imx/system.c | 5 +++++ 3 files changed, 12 insertions(+), 32 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index d04ed7e8d8d3..2413bfbc42f9 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -126,7 +126,11 @@ static inline void imx_smp_prepare(void) {} static inline void imx_scu_standby_enable(void) {} #endif extern void imx_src_init(void); +#ifdef CONFIG_HAVE_IMX_SRC extern void imx_src_prepare_restart(void); +#else +static inline void imx_src_prepare_restart(void) {} +#endif extern void imx_gpc_init(void); extern void imx_gpc_pre_suspend(void); extern void imx_gpc_post_resume(void); diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 049e36edc143..0f9f24116daa 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -38,36 +37,6 @@ #include "cpuidle.h" #include "hardware.h" -static void imx6q_restart(enum reboot_mode mode, const char *cmd) -{ - struct device_node *np; - void __iomem *wdog_base; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); - wdog_base = of_iomap(np, 0); - if (!wdog_base) - goto soft; - - imx_src_prepare_restart(); - - /* enable wdog */ - writew_relaxed(1 << 2, wdog_base); - /* write twice to ensure the request will not get ignored */ - writew_relaxed(1 << 2, wdog_base); - - /* wait for reset to assert ... */ - mdelay(500); - - pr_err("Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); - -soft: - /* we'll take a jump through zero as a poor second */ - soft_restart(0); -} - /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { @@ -167,6 +136,8 @@ static void __init imx6q_init_machine(void) imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", imx_get_soc_revision()); + mxc_arch_reset_init_dt(); + parent = imx_soc_device_init(); if (parent == NULL) pr_warn("failed to initialize soc device\n"); @@ -285,5 +256,5 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") .init_machine = imx6q_init_machine, .init_late = imx6q_init_late, .dt_compat = imx6q_dt_compat, - .restart = imx6q_restart, + .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 80c177c36c5f..e6edcd38b282 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -42,6 +42,9 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) { unsigned int wcr_enable; + if (cpu_is_imx6q() || cpu_is_imx6dl()) + imx_src_prepare_restart(); + if (wdog_clk) clk_enable(wdog_clk); @@ -52,6 +55,8 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) /* Assert SRS signal */ __raw_writew(wcr_enable, wdog_base); + /* write twice to ensure the request will not get ignored */ + __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ mdelay(500); -- cgit v1.2.3 From fcd75f921dfa21a745869090c512ce4c6f2f0477 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 9 Oct 2013 15:29:14 +0800 Subject: ARM: imx: do not return from imx_cpu_die() call When imx_cpu_die() is being called, the cpu should never return from the call but just in WFI and wait for hardware to take it down. So let's do cpu_do_idle() repeatly in the call. Doing this help improve the relibility of hotplug operation. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/hotplug.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index 3daf1ed90579..b35e99cc5e5b 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c @@ -52,7 +52,9 @@ void imx_cpu_die(unsigned int cpu) * the register being cleared to kill the cpu. */ imx_set_cpu_arg(cpu, ~0); - cpu_do_idle(); + + while (1) + cpu_do_idle(); } int imx_cpu_kill(unsigned int cpu) -- cgit v1.2.3 From 6050d181a4fd4abb745506a6e565d55f1f9df964 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 9 Oct 2013 15:54:31 +0800 Subject: ARM: imx: reset core along with enable/disable operation From hotplug stress test result, resetting core during enable/disable operation can improve cpu hotplug stability. So let's set SRC reset bit in imx_enable_cpu() for the core when its enable bit is accessed. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/src.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 10a6b1a8c5ac..4754373e7e7d 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -91,6 +91,7 @@ void imx_enable_cpu(int cpu, bool enable) spin_lock(&scr_lock); val = readl_relaxed(src_base + SRC_SCR); val = enable ? val | mask : val & ~mask; + val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); writel_relaxed(val, src_base + SRC_SCR); spin_unlock(&scr_lock); } -- cgit v1.2.3 From 803648db201f6c5f45e74a646f8f17bdeeb7b7e6 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 16 Oct 2013 21:05:35 +0800 Subject: ARM: imx: drop extern with function prototypes in common.h Since commit 70dc8a4 (checkpatch: warn when using extern with function prototypes in .h files), we will get checkpatch warning when updating common.h following the existing convention which has extern for function prototypes. Let's change the convention to not use extern with function prototypes in this header. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 170 ++++++++++++++++++++++----------------------- 1 file changed, 85 insertions(+), 85 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 2413bfbc42f9..ddcbd90b4edf 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -18,63 +18,63 @@ struct pt_regs; struct clk; enum mxc_cpu_pwr_mode; -extern void mx1_map_io(void); -extern void mx21_map_io(void); -extern void mx25_map_io(void); -extern void mx27_map_io(void); -extern void mx31_map_io(void); -extern void mx35_map_io(void); -extern void mx51_map_io(void); -extern void mx53_map_io(void); -extern void imx1_init_early(void); -extern void imx21_init_early(void); -extern void imx25_init_early(void); -extern void imx27_init_early(void); -extern void imx31_init_early(void); -extern void imx35_init_early(void); -extern void imx51_init_early(void); -extern void imx53_init_early(void); -extern void mxc_init_irq(void __iomem *); -extern void tzic_init_irq(void __iomem *); -extern void mx1_init_irq(void); -extern void mx21_init_irq(void); -extern void mx25_init_irq(void); -extern void mx27_init_irq(void); -extern void mx31_init_irq(void); -extern void mx35_init_irq(void); -extern void mx51_init_irq(void); -extern void mx53_init_irq(void); -extern void imx1_soc_init(void); -extern void imx21_soc_init(void); -extern void imx25_soc_init(void); -extern void imx27_soc_init(void); -extern void imx31_soc_init(void); -extern void imx35_soc_init(void); -extern void imx51_soc_init(void); -extern void imx51_init_late(void); -extern void imx53_init_late(void); -extern void epit_timer_init(void __iomem *base, int irq); -extern void mxc_timer_init(void __iomem *, int); -extern int mx1_clocks_init(unsigned long fref); -extern int mx21_clocks_init(unsigned long lref, unsigned long fref); -extern int mx25_clocks_init(void); -extern int mx27_clocks_init(unsigned long fref); -extern int mx31_clocks_init(unsigned long fref); -extern int mx35_clocks_init(void); -extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, +void mx1_map_io(void); +void mx21_map_io(void); +void mx25_map_io(void); +void mx27_map_io(void); +void mx31_map_io(void); +void mx35_map_io(void); +void mx51_map_io(void); +void mx53_map_io(void); +void imx1_init_early(void); +void imx21_init_early(void); +void imx25_init_early(void); +void imx27_init_early(void); +void imx31_init_early(void); +void imx35_init_early(void); +void imx51_init_early(void); +void imx53_init_early(void); +void mxc_init_irq(void __iomem *); +void tzic_init_irq(void __iomem *); +void mx1_init_irq(void); +void mx21_init_irq(void); +void mx25_init_irq(void); +void mx27_init_irq(void); +void mx31_init_irq(void); +void mx35_init_irq(void); +void mx51_init_irq(void); +void mx53_init_irq(void); +void imx1_soc_init(void); +void imx21_soc_init(void); +void imx25_soc_init(void); +void imx27_soc_init(void); +void imx31_soc_init(void); +void imx35_soc_init(void); +void imx51_soc_init(void); +void imx51_init_late(void); +void imx53_init_late(void); +void epit_timer_init(void __iomem *base, int irq); +void mxc_timer_init(void __iomem *, int); +int mx1_clocks_init(unsigned long fref); +int mx21_clocks_init(unsigned long lref, unsigned long fref); +int mx25_clocks_init(void); +int mx27_clocks_init(unsigned long fref); +int mx31_clocks_init(unsigned long fref); +int mx35_clocks_init(void); +int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); -extern int mx25_clocks_init_dt(void); -extern int mx27_clocks_init_dt(void); -extern int mx31_clocks_init_dt(void); -extern struct platform_device *mxc_register_gpio(char *name, int id, +int mx25_clocks_init_dt(void); +int mx27_clocks_init_dt(void); +int mx31_clocks_init_dt(void); +struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); -extern void mxc_set_cpu_type(unsigned int type); -extern void mxc_restart(enum reboot_mode, const char *); -extern void mxc_arch_reset_init(void __iomem *); -extern void mxc_arch_reset_init_dt(void); -extern int mx53_revision(void); -extern void imx_set_aips(void __iomem *); -extern int mxc_device_init(void); +void mxc_set_cpu_type(unsigned int type); +void mxc_restart(enum reboot_mode, const char *); +void mxc_arch_reset_init(void __iomem *); +void mxc_arch_reset_init_dt(void); +int mx53_revision(void); +void imx_set_aips(void __iomem *); +int mxc_device_init(void); void imx_set_soc_revision(unsigned int rev); unsigned int imx_get_soc_revision(void); void imx_init_revision_from_anatop(void); @@ -95,8 +95,8 @@ enum mx3_cpu_pwr_mode { MX3_SLEEP, }; -extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); -extern void imx_print_silicon_rev(const char *cpu, int srev); +void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); +void imx_print_silicon_rev(const char *cpu, int srev); void avic_handle_irq(struct pt_regs *); void tzic_handle_irq(struct pt_regs *); @@ -110,57 +110,57 @@ void tzic_handle_irq(struct pt_regs *); #define imx51_handle_irq tzic_handle_irq #define imx53_handle_irq tzic_handle_irq -extern void imx_enable_cpu(int cpu, bool enable); -extern void imx_set_cpu_jump(int cpu, void *jump_addr); -extern u32 imx_get_cpu_arg(int cpu); -extern void imx_set_cpu_arg(int cpu, u32 arg); -extern void v7_cpu_resume(void); +void imx_enable_cpu(int cpu, bool enable); +void imx_set_cpu_jump(int cpu, void *jump_addr); +u32 imx_get_cpu_arg(int cpu); +void imx_set_cpu_arg(int cpu, u32 arg); +void v7_cpu_resume(void); #ifdef CONFIG_SMP -extern void v7_secondary_startup(void); -extern void imx_scu_map_io(void); -extern void imx_smp_prepare(void); -extern void imx_scu_standby_enable(void); +void v7_secondary_startup(void); +void imx_scu_map_io(void); +void imx_smp_prepare(void); +void imx_scu_standby_enable(void); #else static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} static inline void imx_scu_standby_enable(void) {} #endif -extern void imx_src_init(void); +void imx_src_init(void); #ifdef CONFIG_HAVE_IMX_SRC -extern void imx_src_prepare_restart(void); +void imx_src_prepare_restart(void); #else static inline void imx_src_prepare_restart(void) {} #endif -extern void imx_gpc_init(void); -extern void imx_gpc_pre_suspend(void); -extern void imx_gpc_post_resume(void); -extern void imx_gpc_mask_all(void); -extern void imx_gpc_restore_all(void); -extern void imx_anatop_init(void); -extern void imx_anatop_pre_suspend(void); -extern void imx_anatop_post_resume(void); -extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -extern void imx6q_set_chicken_bit(void); - -extern void imx_cpu_die(unsigned int cpu); -extern int imx_cpu_kill(unsigned int cpu); +void imx_gpc_init(void); +void imx_gpc_pre_suspend(void); +void imx_gpc_post_resume(void); +void imx_gpc_mask_all(void); +void imx_gpc_restore_all(void); +void imx_anatop_init(void); +void imx_anatop_pre_suspend(void); +void imx_anatop_post_resume(void); +int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); +void imx6q_set_chicken_bit(void); + +void imx_cpu_die(unsigned int cpu); +int imx_cpu_kill(unsigned int cpu); #ifdef CONFIG_PM -extern void imx6q_pm_init(void); -extern void imx5_pm_init(void); +void imx6q_pm_init(void); +void imx5_pm_init(void); #else static inline void imx6q_pm_init(void) {} static inline void imx5_pm_init(void) {} #endif #ifdef CONFIG_NEON -extern int mx51_neon_fixup(void); +int mx51_neon_fixup(void); #else static inline int mx51_neon_fixup(void) { return 0; } #endif #ifdef CONFIG_CACHE_L2X0 -extern void imx_init_l2cache(void); +void imx_init_l2cache(void); #else static inline void imx_init_l2cache(void) {} #endif -- cgit v1.2.3 From 9e8147bb5ec5d1dda2141da70f96b98985a306cb Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 25 Sep 2013 23:09:36 +0800 Subject: ARM: imx6q: move low-power code out of clock driver The LPM (Low Power Mode) code that currently sits in imx6q clock driver will be reused by imx6sl. Let's move it into pm-imx6q.c, so that we can keep clock driver SoC specific and reuse pm-imx6q.c on imx6sl. In order to avoid adding another ioremap for CCM block, imx6q_pm_set_ccm_base() is created to let clock driver set up ccm_base for pm code. During the move, the unused CCGR macros get removed. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 156 +----------------------------------------- arch/arm/mach-imx/common.h | 2 + arch/arm/mach-imx/pm-imx6q.c | 152 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+), 154 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 07bc0d8b573f..d756d91fd741 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -25,155 +24,6 @@ #include "common.h" #include "hardware.h" -#define CCR 0x0 -#define BM_CCR_WB_COUNT (0x7 << 16) -#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) -#define BM_CCR_RBC_EN (0x1 << 27) - -#define CCGR0 0x68 -#define CCGR1 0x6c -#define CCGR2 0x70 -#define CCGR3 0x74 -#define CCGR4 0x78 -#define CCGR5 0x7c -#define CCGR6 0x80 -#define CCGR7 0x84 - -#define CLPCR 0x54 -#define BP_CLPCR_LPM 0 -#define BM_CLPCR_LPM (0x3 << 0) -#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) -#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define BM_CLPCR_SBYOS (0x1 << 6) -#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define BM_CLPCR_VSTBY (0x1 << 8) -#define BP_CLPCR_STBY_COUNT 9 -#define BM_CLPCR_STBY_COUNT (0x3 << 9) -#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) -#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) -#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) -#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) -#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) -#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) -#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) -#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) -#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) -#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) - -#define CGPR 0x64 -#define BM_CGPR_CHICKEN_BIT (0x1 << 17) - -static void __iomem *ccm_base; - -void imx6q_set_chicken_bit(void) -{ - u32 val = readl_relaxed(ccm_base + CGPR); - - val |= BM_CGPR_CHICKEN_BIT; - writel_relaxed(val, ccm_base + CGPR); -} - -static void imx6q_enable_rbc(bool enable) -{ - u32 val; - static bool last_rbc_mode; - - if (last_rbc_mode == enable) - return; - /* - * need to mask all interrupts in GPC before - * operating RBC configurations - */ - imx_gpc_mask_all(); - - /* configure RBC enable bit */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_EN; - val |= enable ? BM_CCR_RBC_EN : 0; - writel_relaxed(val, ccm_base + CCR); - - /* configure RBC count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_BYPASS_COUNT; - val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; - writel(val, ccm_base + CCR); - - /* - * need to delay at least 2 cycles of CKIL(32K) - * due to hardware design requirement, which is - * ~61us, here we use 65us for safe - */ - udelay(65); - - /* restore GPC interrupt mask settings */ - imx_gpc_restore_all(); - - last_rbc_mode = enable; -} - -static void imx6q_enable_wb(bool enable) -{ - u32 val; - static bool last_wb_mode; - - if (last_wb_mode == enable) - return; - - /* configure well bias enable bit */ - val = readl_relaxed(ccm_base + CLPCR); - val &= ~BM_CLPCR_WB_PER_AT_LPM; - val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; - writel_relaxed(val, ccm_base + CLPCR); - - /* configure well bias count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_WB_COUNT; - val |= enable ? BM_CCR_WB_COUNT : 0; - writel_relaxed(val, ccm_base + CCR); - - last_wb_mode = enable; -} - -int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) -{ - u32 val = readl_relaxed(ccm_base + CLPCR); - - val &= ~BM_CLPCR_LPM; - switch (mode) { - case WAIT_CLOCKED: - imx6q_enable_wb(false); - imx6q_enable_rbc(false); - break; - case WAIT_UNCLOCKED: - val |= 0x1 << BP_CLPCR_LPM; - val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; - break; - case STOP_POWER_ON: - val |= 0x2 << BP_CLPCR_LPM; - break; - case WAIT_UNCLOCKED_POWER_OFF: - val |= 0x1 << BP_CLPCR_LPM; - val &= ~BM_CLPCR_VSTBY; - val &= ~BM_CLPCR_SBYOS; - break; - case STOP_POWER_OFF: - val |= 0x2 << BP_CLPCR_LPM; - val |= 0x3 << BP_CLPCR_STBY_COUNT; - val |= BM_CLPCR_VSTBY; - val |= BM_CLPCR_SBYOS; - imx6q_enable_wb(true); - imx6q_enable_rbc(true); - break; - default: - return -EINVAL; - } - - writel_relaxed(val, ccm_base + CLPCR); - - return 0; -} - static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; @@ -384,7 +234,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) np = ccm_node; base = of_iomap(np, 0); WARN_ON(!base); - ccm_base = base; + + imx6q_pm_set_ccm_base(base); /* name reg shift width parent_names num_parents */ clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); @@ -627,9 +478,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if (IS_ENABLED(CONFIG_PCI_IMX6)) clk_set_parent(clk[lvds1_sel], clk[sata_ref]); - /* Set initial power mode */ - imx6q_set_lpm(WAIT_CLOCKED); - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); base = of_iomap(np, 0); WARN_ON(!base); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index ddcbd90b4edf..fde6661ef70d 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -147,9 +147,11 @@ int imx_cpu_kill(unsigned int cpu); #ifdef CONFIG_PM void imx6q_pm_init(void); +void imx6q_pm_set_ccm_base(void __iomem *base); void imx5_pm_init(void); #else static inline void imx6q_pm_init(void) {} +static inline void imx6q_pm_set_ccm_base(void __iomem *base) {} static inline void imx5_pm_init(void) {} #endif diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index 204942749e21..461a895a1388 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -10,9 +10,11 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include #include #include +#include #include #include #include @@ -22,6 +24,146 @@ #include "common.h" #include "hardware.h" +#define CCR 0x0 +#define BM_CCR_WB_COUNT (0x7 << 16) +#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) +#define BM_CCR_RBC_EN (0x1 << 27) + +#define CLPCR 0x54 +#define BP_CLPCR_LPM 0 +#define BM_CLPCR_LPM (0x3 << 0) +#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) +#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define BM_CLPCR_SBYOS (0x1 << 6) +#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define BM_CLPCR_VSTBY (0x1 << 8) +#define BP_CLPCR_STBY_COUNT 9 +#define BM_CLPCR_STBY_COUNT (0x3 << 9) +#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) +#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) +#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) +#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) +#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) +#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) +#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) +#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) +#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) +#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) + +#define CGPR 0x64 +#define BM_CGPR_CHICKEN_BIT (0x1 << 17) + +static void __iomem *ccm_base; + +void imx6q_set_chicken_bit(void) +{ + u32 val = readl_relaxed(ccm_base + CGPR); + + val |= BM_CGPR_CHICKEN_BIT; + writel_relaxed(val, ccm_base + CGPR); +} + +static void imx6q_enable_rbc(bool enable) +{ + u32 val; + static bool last_rbc_mode; + + if (last_rbc_mode == enable) + return; + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpc_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_EN; + val |= enable ? BM_CCR_RBC_EN : 0; + writel_relaxed(val, ccm_base + CCR); + + /* configure RBC count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_BYPASS_COUNT; + val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; + writel(val, ccm_base + CCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpc_restore_all(); + + last_rbc_mode = enable; +} + +static void imx6q_enable_wb(bool enable) +{ + u32 val; + static bool last_wb_mode; + + if (last_wb_mode == enable) + return; + + /* configure well bias enable bit */ + val = readl_relaxed(ccm_base + CLPCR); + val &= ~BM_CLPCR_WB_PER_AT_LPM; + val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; + writel_relaxed(val, ccm_base + CLPCR); + + /* configure well bias count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_WB_COUNT; + val |= enable ? BM_CCR_WB_COUNT : 0; + writel_relaxed(val, ccm_base + CCR); + + last_wb_mode = enable; +} + +int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) +{ + u32 val = readl_relaxed(ccm_base + CLPCR); + + val &= ~BM_CLPCR_LPM; + switch (mode) { + case WAIT_CLOCKED: + imx6q_enable_wb(false); + imx6q_enable_rbc(false); + break; + case WAIT_UNCLOCKED: + val |= 0x1 << BP_CLPCR_LPM; + val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; + break; + case STOP_POWER_ON: + val |= 0x2 << BP_CLPCR_LPM; + break; + case WAIT_UNCLOCKED_POWER_OFF: + val |= 0x1 << BP_CLPCR_LPM; + val &= ~BM_CLPCR_VSTBY; + val &= ~BM_CLPCR_SBYOS; + break; + case STOP_POWER_OFF: + val |= 0x2 << BP_CLPCR_LPM; + val |= 0x3 << BP_CLPCR_STBY_COUNT; + val |= BM_CLPCR_VSTBY; + val |= BM_CLPCR_SBYOS; + imx6q_enable_wb(true); + imx6q_enable_rbc(true); + break; + default: + return -EINVAL; + } + + writel_relaxed(val, ccm_base + CLPCR); + + return 0; +} + static int imx6q_suspend_finish(unsigned long val) { cpu_do_idle(); @@ -55,7 +197,17 @@ static const struct platform_suspend_ops imx6q_pm_ops = { .valid = suspend_valid_only_mem, }; +void __init imx6q_pm_set_ccm_base(void __iomem *base) +{ + ccm_base = base; +} + void __init imx6q_pm_init(void) { + WARN_ON(!ccm_base); + + /* Set initial power mode */ + imx6q_set_lpm(WAIT_CLOCKED); + suspend_set_ops(&imx6q_pm_ops); } -- cgit v1.2.3 From 1d674a73c59211cc33cb9c2954659033d8458fa9 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 9 Oct 2013 20:31:28 +0800 Subject: ARM: imx6q: call WB and RBC configuration from imx6q_pm_enter() The WB and RBC configuration calls are currently made from imx6q_set_lpm() for WAIT_CLOCKED and WAIT_UNCLOCKED mode with a simple state tracking. This becomes unnecessary since we can make the calls from imx6q_pm_enter() directly now for suspend. More importantly, the current call of imx6q_enable_wb() from imx6q_set_lpm() is buggy. The CLPCR register bits configured by imx6q_enable_wb() will get lost, because imx6q_set_lpm() caches the same register and write it back at the end of the function. That's why the imx6dl suspend/resume does not work currently - the wakeup from suspend triggers a reset on imx6dl. Moves the WB and RBC calls into imx6q_pm_enter() to save the state tracking and fixes above bug, so that suspend/resume can start working on imx6dl. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/pm-imx6q.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index 461a895a1388..fb7d90d36672 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -67,10 +67,7 @@ void imx6q_set_chicken_bit(void) static void imx6q_enable_rbc(bool enable) { u32 val; - static bool last_rbc_mode; - if (last_rbc_mode == enable) - return; /* * need to mask all interrupts in GPC before * operating RBC configurations @@ -98,17 +95,11 @@ static void imx6q_enable_rbc(bool enable) /* restore GPC interrupt mask settings */ imx_gpc_restore_all(); - - last_rbc_mode = enable; } static void imx6q_enable_wb(bool enable) { u32 val; - static bool last_wb_mode; - - if (last_wb_mode == enable) - return; /* configure well bias enable bit */ val = readl_relaxed(ccm_base + CLPCR); @@ -121,8 +112,6 @@ static void imx6q_enable_wb(bool enable) val &= ~BM_CCR_WB_COUNT; val |= enable ? BM_CCR_WB_COUNT : 0; writel_relaxed(val, ccm_base + CCR); - - last_wb_mode = enable; } int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) @@ -132,8 +121,6 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) val &= ~BM_CLPCR_LPM; switch (mode) { case WAIT_CLOCKED: - imx6q_enable_wb(false); - imx6q_enable_rbc(false); break; case WAIT_UNCLOCKED: val |= 0x1 << BP_CLPCR_LPM; @@ -152,8 +139,6 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; - imx6q_enable_wb(true); - imx6q_enable_rbc(true); break; default: return -EINVAL; @@ -175,6 +160,8 @@ static int imx6q_pm_enter(suspend_state_t state) switch (state) { case PM_SUSPEND_MEM: imx6q_set_lpm(STOP_POWER_OFF); + imx6q_enable_wb(true); + imx6q_enable_rbc(true); imx_gpc_pre_suspend(); imx_anatop_pre_suspend(); imx_set_cpu_jump(0, v7_cpu_resume); @@ -183,6 +170,8 @@ static int imx6q_pm_enter(suspend_state_t state) imx_smp_prepare(); imx_anatop_post_resume(); imx_gpc_post_resume(); + imx6q_enable_rbc(false); + imx6q_enable_wb(false); imx6q_set_lpm(WAIT_CLOCKED); break; default: -- cgit v1.2.3 From d48866fefdac239a4e02777e712aad60db9ee8a8 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 16 Oct 2013 19:52:00 +0800 Subject: ARM: imx: ensure dsm_request signal is not asserted when setting LPM There is a defect in imx6 LPM design. When SW tries to enter low power mode with following sequence, the chip will enter low power mode before A9 CPU execute WFI instruction: 1. Set CCM_CLPCR[1:0] to 2'b00; 2. ARM CPU enters WFI; 3. ARM CPU wakeup from an interrupt event, which is masked by GPC or not visible to GPC, such as interrupt from local timer; 4. Set CCM_CLPCR[1:0] to 2'b01 or 2'b10; 5. ARM CPU execute WFI. Before the last step, the chip will enter WAIT mode if CCM_CLPCR[1:0] is set to 2'b01, or enter STOP mode if CCM_CLPCR[1:0] is set to 2'b10. The patch implements a recommended workaround for this issue. 1. SW triggers irq #32(IOMUX) to be always pending manually by setting IOMUX_GPR1_GINT bit; 2. SW should then unmask it in GPC before setting CCM LPM; 3. SW should mask it right after CCM LPM is set (bit0-1 of CCM_CLPCR). Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 3 +++ arch/arm/mach-imx/gpc.c | 4 ++-- arch/arm/mach-imx/pm-imx6q.c | 26 ++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index fde6661ef70d..7cbe22d0c6e9 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -13,6 +13,7 @@ #include +struct irq_data; struct platform_device; struct pt_regs; struct clk; @@ -136,6 +137,8 @@ void imx_gpc_pre_suspend(void); void imx_gpc_post_resume(void); void imx_gpc_mask_all(void); void imx_gpc_restore_all(void); +void imx_gpc_irq_mask(struct irq_data *d); +void imx_gpc_irq_unmask(struct irq_data *d); void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 44a65e9ff1fc..586e0171a652 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -90,7 +90,7 @@ void imx_gpc_restore_all(void) writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); } -static void imx_gpc_irq_unmask(struct irq_data *d) +void imx_gpc_irq_unmask(struct irq_data *d) { void __iomem *reg; u32 val; @@ -105,7 +105,7 @@ static void imx_gpc_irq_unmask(struct irq_data *d) writel_relaxed(val, reg); } -static void imx_gpc_irq_mask(struct irq_data *d) +void imx_gpc_irq_mask(struct irq_data *d) { void __iomem *reg; u32 val; diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index fb7d90d36672..f303b56f087c 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -13,8 +13,12 @@ #include #include #include +#include +#include +#include #include #include +#include #include #include #include @@ -116,6 +120,7 @@ static void imx6q_enable_wb(bool enable) int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { + struct irq_desc *iomuxc_irq_desc; u32 val = readl_relaxed(ccm_base + CLPCR); val &= ~BM_CLPCR_LPM; @@ -144,7 +149,16 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) return -EINVAL; } + /* + * Unmask the always pending IOMUXC interrupt #32 as wakeup source to + * deassert dsm_request signal, so that we can ensure dsm_request + * is not asserted when we're going to write CLPCR register to set LPM. + * After setting up LPM bits, we need to mask this wakeup source. + */ + iomuxc_irq_desc = irq_to_desc(32); + imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data); writel_relaxed(val, ccm_base + CLPCR); + imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data); return 0; } @@ -193,8 +207,20 @@ void __init imx6q_pm_set_ccm_base(void __iomem *base) void __init imx6q_pm_init(void) { + struct regmap *gpr; + WARN_ON(!ccm_base); + /* + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, + IMX6Q_GPR1_GINT); + /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); -- cgit v1.2.3 From 9ba64fe3eb461b95bf11436a13db0d9c79465514 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 17 Oct 2013 10:07:09 +0800 Subject: ARM: imx: enable suspend for imx6sl The imx6sl low power mode implementation inherits imx6q/dl one, and pm-imx6q.c can just work for imx6sl with some minor updates. Let's enable imx6sl suspend support by reusing pm-imx6q.c and use cpu_is_imxXX() to handle the those minor differences between imx6sl and imx6q/dl. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Makefile | 2 ++ arch/arm/mach-imx/clk-imx6sl.c | 3 +++ arch/arm/mach-imx/mach-imx6sl.c | 3 +++ arch/arm/mach-imx/mxc.h | 5 +++++ arch/arm/mach-imx/pm-imx6q.c | 9 ++++++++- 5 files changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 5383c589ad71..bbe1f5bb799c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -102,6 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o ifeq ($(CONFIG_PM),y) obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o +# i.MX6SL reuses pm-imx6q.c +obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o endif # i.MX5 based machines diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index a5c3c5d21aee..c0c4ef55e35b 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -127,6 +127,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) base = of_iomap(np, 0); WARN_ON(!base); + /* Reuse imx6q pm code */ + imx6q_pm_set_ccm_base(base); + /* name reg shift width parent_names num_parents */ clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index f01aaabd3254..2f952e3fcf89 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -47,6 +47,9 @@ static void __init imx6sl_init_machine(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); imx6sl_fec_init(); + imx_anatop_init(); + /* Reuse imx6q pm code */ + imx6q_pm_init(); } static void __init imx6sl_init_irq(void) diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 99e03ea9bf79..b08ab3ad4a6d 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -153,6 +153,11 @@ extern unsigned int __mxc_cpu_type; #endif #ifndef __ASSEMBLY__ +static inline bool cpu_is_imx6sl(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6SL; +} + static inline bool cpu_is_imx6dl(void) { return __mxc_cpu_type == MXC_CPU_IMX6DL; diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index f303b56f087c..aecd9f8037e0 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -144,6 +144,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; + if (cpu_is_imx6sl()) { + val |= BM_CLPCR_BYPASS_PMIC_READY; + val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + } else { + val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } break; default: return -EINVAL; @@ -181,7 +187,8 @@ static int imx6q_pm_enter(suspend_state_t state) imx_set_cpu_jump(0, v7_cpu_resume); /* Zzz ... */ cpu_suspend(0, imx6q_suspend_finish); - imx_smp_prepare(); + if (cpu_is_imx6q() || cpu_is_imx6dl()) + imx_smp_prepare(); imx_anatop_post_resume(); imx_gpc_post_resume(); imx6q_enable_rbc(false); -- cgit v1.2.3 From 5d4879cda67b09f086807821cf594ee079d6dfbe Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 19 Sep 2013 16:03:50 -0500 Subject: PM / OPP: rename functions to dev_pm_opp* Since Operating Performance Points (OPP) functions are specific to device specific power management, be specific and rename opp_* accessors in OPP library with dev_pm_opp_* equivalent. Affected functions are: opp_get_voltage opp_get_freq opp_get_opp_count opp_find_freq_exact opp_find_freq_floor opp_find_freq_ceil opp_add opp_enable opp_disable opp_get_notifier opp_init_cpufreq_table opp_free_cpufreq_table Reported-by: Randy Dunlap Signed-off-by: Nishanth Menon Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki --- Documentation/power/opp.txt | 102 ++++++++++++++++---------------- arch/arm/mach-imx/mach-imx6q.c | 2 +- arch/arm/mach-omap2/board-omap3beagle.c | 8 +-- arch/arm/mach-omap2/opp.c | 4 +- arch/arm/mach-omap2/pm.c | 4 +- drivers/base/power/opp.c | 82 ++++++++++++------------- drivers/cpufreq/arm_big_little.c | 6 +- drivers/cpufreq/cpufreq-cpu0.c | 18 +++--- drivers/cpufreq/exynos5440-cpufreq.c | 13 ++-- drivers/cpufreq/imx6q-cpufreq.c | 20 +++---- drivers/cpufreq/omap-cpufreq.c | 8 +-- drivers/devfreq/devfreq.c | 14 ++--- drivers/devfreq/exynos/exynos4_bus.c | 21 +++---- drivers/devfreq/exynos/exynos5_bus.c | 18 +++--- include/linux/opp.h | 50 ++++++++-------- 15 files changed, 187 insertions(+), 183 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/Documentation/power/opp.txt b/Documentation/power/opp.txt index 425c51d56aef..185367b1848f 100644 --- a/Documentation/power/opp.txt +++ b/Documentation/power/opp.txt @@ -71,14 +71,14 @@ operations until that OPP could be re-enabled if possible. OPP library facilitates this concept in it's implementation. The following operational functions operate only on available opps: -opp_find_freq_{ceil, floor}, opp_get_voltage, opp_get_freq, opp_get_opp_count -and opp_init_cpufreq_table +opp_find_freq_{ceil, floor}, dev_pm_opp_get_voltage, dev_pm_opp_get_freq, dev_pm_opp_get_opp_count +and dev_pm_opp_init_cpufreq_table -opp_find_freq_exact is meant to be used to find the opp pointer which can then -be used for opp_enable/disable functions to make an opp available as required. +dev_pm_opp_find_freq_exact is meant to be used to find the opp pointer which can then +be used for dev_pm_opp_enable/disable functions to make an opp available as required. WARNING: Users of OPP library should refresh their availability count using -get_opp_count if opp_enable/disable functions are invoked for a device, the +get_opp_count if dev_pm_opp_enable/disable functions are invoked for a device, the exact mechanism to trigger these or the notification mechanism to other dependent subsystems such as cpufreq are left to the discretion of the SoC specific framework which uses the OPP library. Similar care needs to be taken @@ -96,24 +96,24 @@ using RCU read locks. The opp_find_freq_{exact,ceil,floor}, opp_get_{voltage, freq, opp_count} fall into this category. opp_{add,enable,disable} are updaters which use mutex and implement it's own -RCU locking mechanisms. opp_init_cpufreq_table acts as an updater and uses +RCU locking mechanisms. dev_pm_opp_init_cpufreq_table acts as an updater and uses mutex to implment RCU updater strategy. These functions should *NOT* be called under RCU locks and other contexts that prevent blocking functions in RCU or mutex operations from working. 2. Initial OPP List Registration ================================ -The SoC implementation calls opp_add function iteratively to add OPPs per +The SoC implementation calls dev_pm_opp_add function iteratively to add OPPs per device. It is expected that the SoC framework will register the OPP entries optimally- typical numbers range to be less than 5. The list generated by registering the OPPs is maintained by OPP library throughout the device operation. The SoC framework can subsequently control the availability of the -OPPs dynamically using the opp_enable / disable functions. +OPPs dynamically using the dev_pm_opp_enable / disable functions. -opp_add - Add a new OPP for a specific domain represented by the device pointer. +dev_pm_opp_add - Add a new OPP for a specific domain represented by the device pointer. The OPP is defined using the frequency and voltage. Once added, the OPP is assumed to be available and control of it's availability can be done - with the opp_enable/disable functions. OPP library internally stores + with the dev_pm_opp_enable/disable functions. OPP library internally stores and manages this information in the opp struct. This function may be used by SoC framework to define a optimal list as per the demands of SoC usage environment. @@ -124,7 +124,7 @@ opp_add - Add a new OPP for a specific domain represented by the device pointer. soc_pm_init() { /* Do things */ - r = opp_add(mpu_dev, 1000000, 900000); + r = dev_pm_opp_add(mpu_dev, 1000000, 900000); if (!r) { pr_err("%s: unable to register mpu opp(%d)\n", r); goto no_cpufreq; @@ -143,44 +143,44 @@ functions return the matching pointer representing the opp if a match is found, else returns error. These errors are expected to be handled by standard error checks such as IS_ERR() and appropriate actions taken by the caller. -opp_find_freq_exact - Search for an OPP based on an *exact* frequency and +dev_pm_opp_find_freq_exact - Search for an OPP based on an *exact* frequency and availability. This function is especially useful to enable an OPP which is not available by default. Example: In a case when SoC framework detects a situation where a higher frequency could be made available, it can use this function to - find the OPP prior to call the opp_enable to actually make it available. + find the OPP prior to call the dev_pm_opp_enable to actually make it available. rcu_read_lock(); - opp = opp_find_freq_exact(dev, 1000000000, false); + opp = dev_pm_opp_find_freq_exact(dev, 1000000000, false); rcu_read_unlock(); /* dont operate on the pointer.. just do a sanity check.. */ if (IS_ERR(opp)) { pr_err("frequency not disabled!\n"); /* trigger appropriate actions.. */ } else { - opp_enable(dev,1000000000); + dev_pm_opp_enable(dev,1000000000); } NOTE: This is the only search function that operates on OPPs which are not available. -opp_find_freq_floor - Search for an available OPP which is *at most* the +dev_pm_opp_find_freq_floor - Search for an available OPP which is *at most* the provided frequency. This function is useful while searching for a lesser match OR operating on OPP information in the order of decreasing frequency. Example: To find the highest opp for a device: freq = ULONG_MAX; rcu_read_lock(); - opp_find_freq_floor(dev, &freq); + dev_pm_opp_find_freq_floor(dev, &freq); rcu_read_unlock(); -opp_find_freq_ceil - Search for an available OPP which is *at least* the +dev_pm_opp_find_freq_ceil - Search for an available OPP which is *at least* the provided frequency. This function is useful while searching for a higher match OR operating on OPP information in the order of increasing frequency. Example 1: To find the lowest opp for a device: freq = 0; rcu_read_lock(); - opp_find_freq_ceil(dev, &freq); + dev_pm_opp_find_freq_ceil(dev, &freq); rcu_read_unlock(); Example 2: A simplified implementation of a SoC cpufreq_driver->target: soc_cpufreq_target(..) @@ -188,7 +188,7 @@ opp_find_freq_ceil - Search for an available OPP which is *at least* the /* Do stuff like policy checks etc. */ /* Find the best frequency match for the req */ rcu_read_lock(); - opp = opp_find_freq_ceil(dev, &freq); + opp = dev_pm_opp_find_freq_ceil(dev, &freq); rcu_read_unlock(); if (!IS_ERR(opp)) soc_switch_to_freq_voltage(freq); @@ -208,34 +208,34 @@ as thermal considerations (e.g. don't use OPPx until the temperature drops). WARNING: Do not use these functions in interrupt context. -opp_enable - Make a OPP available for operation. +dev_pm_opp_enable - Make a OPP available for operation. Example: Lets say that 1GHz OPP is to be made available only if the SoC temperature is lower than a certain threshold. The SoC framework implementation might choose to do something as follows: if (cur_temp < temp_low_thresh) { /* Enable 1GHz if it was disabled */ rcu_read_lock(); - opp = opp_find_freq_exact(dev, 1000000000, false); + opp = dev_pm_opp_find_freq_exact(dev, 1000000000, false); rcu_read_unlock(); /* just error check */ if (!IS_ERR(opp)) - ret = opp_enable(dev, 1000000000); + ret = dev_pm_opp_enable(dev, 1000000000); else goto try_something_else; } -opp_disable - Make an OPP to be not available for operation +dev_pm_opp_disable - Make an OPP to be not available for operation Example: Lets say that 1GHz OPP is to be disabled if the temperature exceeds a threshold value. The SoC framework implementation might choose to do something as follows: if (cur_temp > temp_high_thresh) { /* Disable 1GHz if it was enabled */ rcu_read_lock(); - opp = opp_find_freq_exact(dev, 1000000000, true); + opp = dev_pm_opp_find_freq_exact(dev, 1000000000, true); rcu_read_unlock(); /* just error check */ if (!IS_ERR(opp)) - ret = opp_disable(dev, 1000000000); + ret = dev_pm_opp_disable(dev, 1000000000); else goto try_something_else; } @@ -247,7 +247,7 @@ information from the OPP structure is necessary. Once an OPP pointer is retrieved using the search functions, the following functions can be used by SoC framework to retrieve the information represented inside the OPP layer. -opp_get_voltage - Retrieve the voltage represented by the opp pointer. +dev_pm_opp_get_voltage - Retrieve the voltage represented by the opp pointer. Example: At a cpufreq transition to a different frequency, SoC framework requires to set the voltage represented by the OPP using the regulator framework to the Power Management chip providing the @@ -256,15 +256,15 @@ opp_get_voltage - Retrieve the voltage represented by the opp pointer. { /* do things */ rcu_read_lock(); - opp = opp_find_freq_ceil(dev, &freq); - v = opp_get_voltage(opp); + opp = dev_pm_opp_find_freq_ceil(dev, &freq); + v = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); if (v) regulator_set_voltage(.., v); /* do other things */ } -opp_get_freq - Retrieve the freq represented by the opp pointer. +dev_pm_opp_get_freq - Retrieve the freq represented by the opp pointer. Example: Lets say the SoC framework uses a couple of helper functions we could pass opp pointers instead of doing additional parameters to handle quiet a bit of data parameters. @@ -273,8 +273,8 @@ opp_get_freq - Retrieve the freq represented by the opp pointer. /* do things.. */ max_freq = ULONG_MAX; rcu_read_lock(); - max_opp = opp_find_freq_floor(dev,&max_freq); - requested_opp = opp_find_freq_ceil(dev,&freq); + max_opp = dev_pm_opp_find_freq_floor(dev,&max_freq); + requested_opp = dev_pm_opp_find_freq_ceil(dev,&freq); if (!IS_ERR(max_opp) && !IS_ERR(requested_opp)) r = soc_test_validity(max_opp, requested_opp); rcu_read_unlock(); @@ -282,25 +282,25 @@ opp_get_freq - Retrieve the freq represented by the opp pointer. } soc_test_validity(..) { - if(opp_get_voltage(max_opp) < opp_get_voltage(requested_opp)) + if(dev_pm_opp_get_voltage(max_opp) < dev_pm_opp_get_voltage(requested_opp)) return -EINVAL; - if(opp_get_freq(max_opp) < opp_get_freq(requested_opp)) + if(dev_pm_opp_get_freq(max_opp) < dev_pm_opp_get_freq(requested_opp)) return -EINVAL; /* do things.. */ } -opp_get_opp_count - Retrieve the number of available opps for a device +dev_pm_opp_get_opp_count - Retrieve the number of available opps for a device Example: Lets say a co-processor in the SoC needs to know the available frequencies in a table, the main processor can notify as following: soc_notify_coproc_available_frequencies() { /* Do things */ rcu_read_lock(); - num_available = opp_get_opp_count(dev); + num_available = dev_pm_opp_get_opp_count(dev); speeds = kzalloc(sizeof(u32) * num_available, GFP_KERNEL); /* populate the table in increasing order */ freq = 0; - while (!IS_ERR(opp = opp_find_freq_ceil(dev, &freq))) { + while (!IS_ERR(opp = dev_pm_opp_find_freq_ceil(dev, &freq))) { speeds[i] = freq; freq++; i++; @@ -313,7 +313,7 @@ opp_get_opp_count - Retrieve the number of available opps for a device 6. Cpufreq Table Generation =========================== -opp_init_cpufreq_table - cpufreq framework typically is initialized with +dev_pm_opp_init_cpufreq_table - cpufreq framework typically is initialized with cpufreq_frequency_table_cpuinfo which is provided with the list of frequencies that are available for operation. This function provides a ready to use conversion routine to translate the OPP layer's internal @@ -326,7 +326,7 @@ opp_init_cpufreq_table - cpufreq framework typically is initialized with soc_pm_init() { /* Do things */ - r = opp_init_cpufreq_table(dev, &freq_table); + r = dev_pm_opp_init_cpufreq_table(dev, &freq_table); if (!r) cpufreq_frequency_table_cpuinfo(policy, freq_table); /* Do other things */ @@ -336,7 +336,7 @@ opp_init_cpufreq_table - cpufreq framework typically is initialized with addition to CONFIG_PM as power management feature is required to dynamically scale voltage and frequency in a system. -opp_free_cpufreq_table - Free up the table allocated by opp_init_cpufreq_table +dev_pm_opp_free_cpufreq_table - Free up the table allocated by dev_pm_opp_init_cpufreq_table 7. Data Structures ================== @@ -366,8 +366,8 @@ struct opp - The internal data structure of OPP library which is used to identifier for OPP in the interactions with OPP layer. WARNING: The struct opp pointer should not be parsed or modified by the - users. The defaults of for an instance is populated by opp_add, but the - availability of the OPP can be modified by opp_enable/disable functions. + users. The defaults of for an instance is populated by dev_pm_opp_add, but the + availability of the OPP can be modified by dev_pm_opp_enable/disable functions. struct device - This is used to identify a domain to the OPP layer. The nature of the device and it's implementation is left to the user of @@ -377,19 +377,19 @@ Overall, in a simplistic view, the data structure operations is represented as following: Initialization / modification: - +-----+ /- opp_enable -opp_add --> | opp | <------- - | +-----+ \- opp_disable + +-----+ /- dev_pm_opp_enable +dev_pm_opp_add --> | opp | <------- + | +-----+ \- dev_pm_opp_disable \-------> domain_info(device) Search functions: - /-- opp_find_freq_ceil ---\ +-----+ -domain_info<---- opp_find_freq_exact -----> | opp | - \-- opp_find_freq_floor ---/ +-----+ + /-- dev_pm_opp_find_freq_ceil ---\ +-----+ +domain_info<---- dev_pm_opp_find_freq_exact -----> | opp | + \-- dev_pm_opp_find_freq_floor ---/ +-----+ Retrieval functions: -+-----+ /- opp_get_voltage ++-----+ /- dev_pm_opp_get_voltage | opp | <--- -+-----+ \- opp_get_freq ++-----+ \- dev_pm_opp_get_freq -domain_info <- opp_get_opp_count +domain_info <- dev_pm_opp_get_opp_count diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 90372a21087f..d7ecc90e6bba 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -226,7 +226,7 @@ static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) val = readl_relaxed(base + OCOTP_CFG3); val >>= OCOTP_CFG3_SPEED_SHIFT; if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) - if (opp_disable(cpu_dev, 1200000000)) + if (dev_pm_opp_disable(cpu_dev, 1200000000)) pr_warn("failed to disable 1.2 GHz OPP\n"); put_node: diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index f26918467efc..33969e5a149f 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -522,11 +522,11 @@ static int __init beagle_opp_init(void) return -ENODEV; } /* Enable MPU 1GHz and lower opps */ - r = opp_enable(mpu_dev, 800000000); + r = dev_pm_opp_enable(mpu_dev, 800000000); /* TODO: MPU 1GHz needs SR and ABB */ /* Enable IVA 800MHz and lower opps */ - r |= opp_enable(iva_dev, 660000000); + r |= dev_pm_opp_enable(iva_dev, 660000000); /* TODO: DSP 800MHz needs SR and ABB */ if (r) { pr_err("%s: failed to enable higher opp %d\n", @@ -535,8 +535,8 @@ static int __init beagle_opp_init(void) * Cleanup - disable the higher freqs - we dont care * about the results */ - opp_disable(mpu_dev, 800000000); - opp_disable(iva_dev, 660000000); + dev_pm_opp_disable(mpu_dev, 800000000); + dev_pm_opp_disable(iva_dev, 660000000); } } return 0; diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index bd41d59a7cab..7b04637b13cb 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c @@ -81,14 +81,14 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, dev = &oh->od->pdev->dev; } - r = opp_add(dev, opp_def->freq, opp_def->u_volt); + r = dev_pm_opp_add(dev, opp_def->freq, opp_def->u_volt); if (r) { dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n", __func__, opp_def->freq, opp_def->hwmod_name, i, r); } else { if (!opp_def->default_available) - r = opp_disable(dev, opp_def->freq); + r = dev_pm_opp_disable(dev, opp_def->freq); if (r) dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n", __func__, opp_def->freq, diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index e742118fcfd2..937744c3679d 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -172,7 +172,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, clk_put(clk); rcu_read_lock(); - opp = opp_find_freq_ceil(dev, &freq); + opp = dev_pm_opp_find_freq_ceil(dev, &freq); if (IS_ERR(opp)) { rcu_read_unlock(); pr_err("%s: unable to find boot up OPP for vdd_%s\n", @@ -180,7 +180,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, goto exit; } - bootup_volt = opp_get_voltage(opp); + bootup_volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); if (!bootup_volt) { pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c index ef89897c6043..00c6a449cdeb 100644 --- a/drivers/base/power/opp.c +++ b/drivers/base/power/opp.c @@ -136,7 +136,7 @@ static struct device_opp *find_device_opp(struct device *dev) } /** - * opp_get_voltage() - Gets the voltage corresponding to an available opp + * dev_pm_opp_get_voltage() - Gets the voltage corresponding to an available opp * @opp: opp for which voltage has to be returned for * * Return voltage in micro volt corresponding to the opp, else @@ -150,7 +150,7 @@ static struct device_opp *find_device_opp(struct device *dev) * prior to unlocking with rcu_read_unlock() to maintain the integrity of the * pointer. */ -unsigned long opp_get_voltage(struct opp *opp) +unsigned long dev_pm_opp_get_voltage(struct opp *opp) { struct opp *tmp_opp; unsigned long v = 0; @@ -163,10 +163,10 @@ unsigned long opp_get_voltage(struct opp *opp) return v; } -EXPORT_SYMBOL_GPL(opp_get_voltage); +EXPORT_SYMBOL_GPL(dev_pm_opp_get_voltage); /** - * opp_get_freq() - Gets the frequency corresponding to an available opp + * dev_pm_opp_get_freq() - Gets the frequency corresponding to an available opp * @opp: opp for which frequency has to be returned for * * Return frequency in hertz corresponding to the opp, else @@ -180,7 +180,7 @@ EXPORT_SYMBOL_GPL(opp_get_voltage); * prior to unlocking with rcu_read_unlock() to maintain the integrity of the * pointer. */ -unsigned long opp_get_freq(struct opp *opp) +unsigned long dev_pm_opp_get_freq(struct opp *opp) { struct opp *tmp_opp; unsigned long f = 0; @@ -193,10 +193,10 @@ unsigned long opp_get_freq(struct opp *opp) return f; } -EXPORT_SYMBOL_GPL(opp_get_freq); +EXPORT_SYMBOL_GPL(dev_pm_opp_get_freq); /** - * opp_get_opp_count() - Get number of opps available in the opp list + * dev_pm_opp_get_opp_count() - Get number of opps available in the opp list * @dev: device for which we do this operation * * This function returns the number of available opps if there are any, @@ -206,7 +206,7 @@ EXPORT_SYMBOL_GPL(opp_get_freq); * internally references two RCU protected structures: device_opp and opp which * are safe as long as we are under a common RCU locked section. */ -int opp_get_opp_count(struct device *dev) +int dev_pm_opp_get_opp_count(struct device *dev) { struct device_opp *dev_opp; struct opp *temp_opp; @@ -226,10 +226,10 @@ int opp_get_opp_count(struct device *dev) return count; } -EXPORT_SYMBOL_GPL(opp_get_opp_count); +EXPORT_SYMBOL_GPL(dev_pm_opp_get_opp_count); /** - * opp_find_freq_exact() - search for an exact frequency + * dev_pm_opp_find_freq_exact() - search for an exact frequency * @dev: device for which we do this operation * @freq: frequency to search for * @available: true/false - match for available opp @@ -254,7 +254,7 @@ EXPORT_SYMBOL_GPL(opp_get_opp_count); * under the locked area. The pointer returned must be used prior to unlocking * with rcu_read_unlock() to maintain the integrity of the pointer. */ -struct opp *opp_find_freq_exact(struct device *dev, unsigned long freq, +struct opp *dev_pm_opp_find_freq_exact(struct device *dev, unsigned long freq, bool available) { struct device_opp *dev_opp; @@ -277,10 +277,10 @@ struct opp *opp_find_freq_exact(struct device *dev, unsigned long freq, return opp; } -EXPORT_SYMBOL_GPL(opp_find_freq_exact); +EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_exact); /** - * opp_find_freq_ceil() - Search for an rounded ceil freq + * dev_pm_opp_find_freq_ceil() - Search for an rounded ceil freq * @dev: device for which we do this operation * @freq: Start frequency * @@ -300,7 +300,7 @@ EXPORT_SYMBOL_GPL(opp_find_freq_exact); * under the locked area. The pointer returned must be used prior to unlocking * with rcu_read_unlock() to maintain the integrity of the pointer. */ -struct opp *opp_find_freq_ceil(struct device *dev, unsigned long *freq) +struct opp *dev_pm_opp_find_freq_ceil(struct device *dev, unsigned long *freq) { struct device_opp *dev_opp; struct opp *temp_opp, *opp = ERR_PTR(-ERANGE); @@ -324,10 +324,10 @@ struct opp *opp_find_freq_ceil(struct device *dev, unsigned long *freq) return opp; } -EXPORT_SYMBOL_GPL(opp_find_freq_ceil); +EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_ceil); /** - * opp_find_freq_floor() - Search for a rounded floor freq + * dev_pm_opp_find_freq_floor() - Search for a rounded floor freq * @dev: device for which we do this operation * @freq: Start frequency * @@ -347,7 +347,7 @@ EXPORT_SYMBOL_GPL(opp_find_freq_ceil); * under the locked area. The pointer returned must be used prior to unlocking * with rcu_read_unlock() to maintain the integrity of the pointer. */ -struct opp *opp_find_freq_floor(struct device *dev, unsigned long *freq) +struct opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq) { struct device_opp *dev_opp; struct opp *temp_opp, *opp = ERR_PTR(-ERANGE); @@ -375,17 +375,17 @@ struct opp *opp_find_freq_floor(struct device *dev, unsigned long *freq) return opp; } -EXPORT_SYMBOL_GPL(opp_find_freq_floor); +EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor); /** - * opp_add() - Add an OPP table from a table definitions + * dev_pm_opp_add() - Add an OPP table from a table definitions * @dev: device for which we do this operation * @freq: Frequency in Hz for this OPP * @u_volt: Voltage in uVolts for this OPP * * This function adds an opp definition to the opp list and returns status. * The opp is made available by default and it can be controlled using - * opp_enable/disable functions. + * dev_pm_opp_enable/disable functions. * * Locking: The internal device_opp and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks @@ -393,7 +393,7 @@ EXPORT_SYMBOL_GPL(opp_find_freq_floor); * that this function is *NOT* called under RCU protection or in contexts where * mutex cannot be locked. */ -int opp_add(struct device *dev, unsigned long freq, unsigned long u_volt) +int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long u_volt) { struct device_opp *dev_opp = NULL; struct opp *opp, *new_opp; @@ -460,7 +460,7 @@ int opp_add(struct device *dev, unsigned long freq, unsigned long u_volt) srcu_notifier_call_chain(&dev_opp->head, OPP_EVENT_ADD, new_opp); return 0; } -EXPORT_SYMBOL_GPL(opp_add); +EXPORT_SYMBOL_GPL(dev_pm_opp_add); /** * opp_set_availability() - helper to set the availability of an opp @@ -552,13 +552,13 @@ unlock: } /** - * opp_enable() - Enable a specific OPP + * dev_pm_opp_enable() - Enable a specific OPP * @dev: device for which we do this operation * @freq: OPP frequency to enable * * Enables a provided opp. If the operation is valid, this returns 0, else the * corresponding error value. It is meant to be used for users an OPP available - * after being temporarily made unavailable with opp_disable. + * after being temporarily made unavailable with dev_pm_opp_disable. * * Locking: The internal device_opp and opp structures are RCU protected. * Hence this function indirectly uses RCU and mutex locks to keep the @@ -566,21 +566,21 @@ unlock: * this function is *NOT* called under RCU protection or in contexts where * mutex locking or synchronize_rcu() blocking calls cannot be used. */ -int opp_enable(struct device *dev, unsigned long freq) +int dev_pm_opp_enable(struct device *dev, unsigned long freq) { return opp_set_availability(dev, freq, true); } -EXPORT_SYMBOL_GPL(opp_enable); +EXPORT_SYMBOL_GPL(dev_pm_opp_enable); /** - * opp_disable() - Disable a specific OPP + * dev_pm_opp_disable() - Disable a specific OPP * @dev: device for which we do this operation * @freq: OPP frequency to disable * * Disables a provided opp. If the operation is valid, this returns * 0, else the corresponding error value. It is meant to be a temporary * control by users to make this OPP not available until the circumstances are - * right to make it available again (with a call to opp_enable). + * right to make it available again (with a call to dev_pm_opp_enable). * * Locking: The internal device_opp and opp structures are RCU protected. * Hence this function indirectly uses RCU and mutex locks to keep the @@ -588,15 +588,15 @@ EXPORT_SYMBOL_GPL(opp_enable); * this function is *NOT* called under RCU protection or in contexts where * mutex locking or synchronize_rcu() blocking calls cannot be used. */ -int opp_disable(struct device *dev, unsigned long freq) +int dev_pm_opp_disable(struct device *dev, unsigned long freq) { return opp_set_availability(dev, freq, false); } -EXPORT_SYMBOL_GPL(opp_disable); +EXPORT_SYMBOL_GPL(dev_pm_opp_disable); #ifdef CONFIG_CPU_FREQ /** - * opp_init_cpufreq_table() - create a cpufreq table for a device + * dev_pm_opp_init_cpufreq_table() - create a cpufreq table for a device * @dev: device for which we do this operation * @table: Cpufreq table returned back to caller * @@ -619,7 +619,7 @@ EXPORT_SYMBOL_GPL(opp_disable); * Callers should ensure that this function is *NOT* called under RCU protection * or in contexts where mutex locking cannot be used. */ -int opp_init_cpufreq_table(struct device *dev, +int dev_pm_opp_init_cpufreq_table(struct device *dev, struct cpufreq_frequency_table **table) { struct device_opp *dev_opp; @@ -639,7 +639,7 @@ int opp_init_cpufreq_table(struct device *dev, } freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * - (opp_get_opp_count(dev) + 1), GFP_KERNEL); + (dev_pm_opp_get_opp_count(dev) + 1), GFP_KERNEL); if (!freq_table) { mutex_unlock(&dev_opp_list_lock); dev_warn(dev, "%s: Unable to allocate frequency table\n", @@ -663,16 +663,16 @@ int opp_init_cpufreq_table(struct device *dev, return 0; } -EXPORT_SYMBOL_GPL(opp_init_cpufreq_table); +EXPORT_SYMBOL_GPL(dev_pm_opp_init_cpufreq_table); /** - * opp_free_cpufreq_table() - free the cpufreq table + * dev_pm_opp_free_cpufreq_table() - free the cpufreq table * @dev: device for which we do this operation * @table: table to free * - * Free up the table allocated by opp_init_cpufreq_table + * Free up the table allocated by dev_pm_opp_init_cpufreq_table */ -void opp_free_cpufreq_table(struct device *dev, +void dev_pm_opp_free_cpufreq_table(struct device *dev, struct cpufreq_frequency_table **table) { if (!table) @@ -681,14 +681,14 @@ void opp_free_cpufreq_table(struct device *dev, kfree(*table); *table = NULL; } -EXPORT_SYMBOL_GPL(opp_free_cpufreq_table); +EXPORT_SYMBOL_GPL(dev_pm_opp_free_cpufreq_table); #endif /* CONFIG_CPU_FREQ */ /** - * opp_get_notifier() - find notifier_head of the device with opp + * dev_pm_opp_get_notifier() - find notifier_head of the device with opp * @dev: device pointer used to lookup device OPPs. */ -struct srcu_notifier_head *opp_get_notifier(struct device *dev) +struct srcu_notifier_head *dev_pm_opp_get_notifier(struct device *dev) { struct device_opp *dev_opp = find_device_opp(dev); @@ -732,7 +732,7 @@ int of_init_opp_table(struct device *dev) unsigned long freq = be32_to_cpup(val++) * 1000; unsigned long volt = be32_to_cpup(val++); - if (opp_add(dev, freq, volt)) { + if (dev_pm_opp_add(dev, freq, volt)) { dev_warn(dev, "%s: Failed to add OPP %ld\n", __func__, freq); continue; diff --git a/drivers/cpufreq/arm_big_little.c b/drivers/cpufreq/arm_big_little.c index 3549f0784af1..9e82a9d5df77 100644 --- a/drivers/cpufreq/arm_big_little.c +++ b/drivers/cpufreq/arm_big_little.c @@ -98,7 +98,7 @@ static void put_cluster_clk_and_freq_table(struct device *cpu_dev) if (!atomic_dec_return(&cluster_usage[cluster])) { clk_put(clk[cluster]); - opp_free_cpufreq_table(cpu_dev, &freq_table[cluster]); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table[cluster]); dev_dbg(cpu_dev, "%s: cluster: %d\n", __func__, cluster); } } @@ -119,7 +119,7 @@ static int get_cluster_clk_and_freq_table(struct device *cpu_dev) goto atomic_dec; } - ret = opp_init_cpufreq_table(cpu_dev, &freq_table[cluster]); + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table[cluster]); if (ret) { dev_err(cpu_dev, "%s: failed to init cpufreq table, cpu: %d, err: %d\n", __func__, cpu_dev->id, ret); @@ -138,7 +138,7 @@ static int get_cluster_clk_and_freq_table(struct device *cpu_dev) dev_err(cpu_dev, "%s: Failed to get clk for cpu: %d, cluster: %d\n", __func__, cpu_dev->id, cluster); ret = PTR_ERR(clk[cluster]); - opp_free_cpufreq_table(cpu_dev, &freq_table[cluster]); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table[cluster]); atomic_dec: atomic_dec(&cluster_usage[cluster]); diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c index c522a95c0e16..af951a9cea78 100644 --- a/drivers/cpufreq/cpufreq-cpu0.c +++ b/drivers/cpufreq/cpufreq-cpu0.c @@ -72,7 +72,7 @@ static int cpu0_set_target(struct cpufreq_policy *policy, if (!IS_ERR(cpu_reg)) { rcu_read_lock(); - opp = opp_find_freq_ceil(cpu_dev, &freq_Hz); + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); if (IS_ERR(opp)) { rcu_read_unlock(); pr_err("failed to find OPP for %ld\n", freq_Hz); @@ -80,7 +80,7 @@ static int cpu0_set_target(struct cpufreq_policy *policy, ret = PTR_ERR(opp); goto post_notify; } - volt = opp_get_voltage(opp); + volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); tol = volt * voltage_tolerance / 100; volt_old = regulator_get_voltage(cpu_reg); @@ -218,7 +218,7 @@ static int cpu0_cpufreq_probe(struct platform_device *pdev) goto out_put_node; } - ret = opp_init_cpufreq_table(cpu_dev, &freq_table); + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); if (ret) { pr_err("failed to init cpufreq table: %d\n", ret); goto out_put_node; @@ -242,12 +242,12 @@ static int cpu0_cpufreq_probe(struct platform_device *pdev) for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) ; rcu_read_lock(); - opp = opp_find_freq_exact(cpu_dev, + opp = dev_pm_opp_find_freq_exact(cpu_dev, freq_table[0].frequency * 1000, true); - min_uV = opp_get_voltage(opp); - opp = opp_find_freq_exact(cpu_dev, + min_uV = dev_pm_opp_get_voltage(opp); + opp = dev_pm_opp_find_freq_exact(cpu_dev, freq_table[i-1].frequency * 1000, true); - max_uV = opp_get_voltage(opp); + max_uV = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); if (ret > 0) @@ -264,7 +264,7 @@ static int cpu0_cpufreq_probe(struct platform_device *pdev) return 0; out_free_table: - opp_free_cpufreq_table(cpu_dev, &freq_table); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); out_put_node: of_node_put(np); return ret; @@ -273,7 +273,7 @@ out_put_node: static int cpu0_cpufreq_remove(struct platform_device *pdev) { cpufreq_unregister_driver(&cpu0_cpufreq_driver); - opp_free_cpufreq_table(cpu_dev, &freq_table); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); return 0; } diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c index be5380ecdcd4..444eca74d3c2 100644 --- a/drivers/cpufreq/exynos5440-cpufreq.c +++ b/drivers/cpufreq/exynos5440-cpufreq.c @@ -123,7 +123,7 @@ static int init_div_table(void) rcu_read_lock(); for (i = 0; freq_tbl[i].frequency != CPUFREQ_TABLE_END; i++) { - opp = opp_find_freq_exact(dvfs_info->dev, + opp = dev_pm_opp_find_freq_exact(dvfs_info->dev, freq_tbl[i].frequency * 1000, true); if (IS_ERR(opp)) { rcu_read_unlock(); @@ -142,7 +142,7 @@ static int init_div_table(void) << P0_7_CSCLKDEV_SHIFT; /* Calculate EMA */ - volt_id = opp_get_voltage(opp); + volt_id = dev_pm_opp_get_voltage(opp); volt_id = (MAX_VOLTAGE - volt_id) / VOLTAGE_STEP; if (volt_id < PMIC_HIGH_VOLT) { ema_div = (CPUEMA_HIGH << P0_7_CPUEMA_SHIFT) | @@ -399,13 +399,14 @@ static int exynos_cpufreq_probe(struct platform_device *pdev) goto err_put_node; } - ret = opp_init_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table); + ret = dev_pm_opp_init_cpufreq_table(dvfs_info->dev, + &dvfs_info->freq_table); if (ret) { dev_err(dvfs_info->dev, "failed to init cpufreq table: %d\n", ret); goto err_put_node; } - dvfs_info->freq_count = opp_get_opp_count(dvfs_info->dev); + dvfs_info->freq_count = dev_pm_opp_get_opp_count(dvfs_info->dev); exynos_sort_descend_freq_table(); if (of_property_read_u32(np, "clock-latency", &dvfs_info->latency)) @@ -454,7 +455,7 @@ static int exynos_cpufreq_probe(struct platform_device *pdev) return 0; err_free_table: - opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table); + dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table); err_put_node: of_node_put(np); dev_err(&pdev->dev, "%s: failed initialization\n", __func__); @@ -464,7 +465,7 @@ err_put_node: static int exynos_cpufreq_remove(struct platform_device *pdev) { cpufreq_unregister_driver(&exynos_driver); - opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table); + dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table); return 0; } diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index c3fd2a101ca0..b360549e7715 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -70,14 +70,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, return 0; rcu_read_lock(); - opp = opp_find_freq_ceil(cpu_dev, &freq_hz); + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); if (IS_ERR(opp)) { rcu_read_unlock(); dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); return PTR_ERR(opp); } - volt = opp_get_voltage(opp); + volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); volt_old = regulator_get_voltage(arm_reg); @@ -237,14 +237,14 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) } /* We expect an OPP table supplied by platform */ - num = opp_get_opp_count(cpu_dev); + num = dev_pm_opp_get_opp_count(cpu_dev); if (num < 0) { ret = num; dev_err(cpu_dev, "no OPP table is found: %d\n", ret); goto put_node; } - ret = opp_init_cpufreq_table(cpu_dev, &freq_table); + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); if (ret) { dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); goto put_node; @@ -259,12 +259,12 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) * same order. */ rcu_read_lock(); - opp = opp_find_freq_exact(cpu_dev, + opp = dev_pm_opp_find_freq_exact(cpu_dev, freq_table[0].frequency * 1000, true); - min_volt = opp_get_voltage(opp); - opp = opp_find_freq_exact(cpu_dev, + min_volt = dev_pm_opp_get_voltage(opp); + opp = dev_pm_opp_find_freq_exact(cpu_dev, freq_table[--num].frequency * 1000, true); - max_volt = opp_get_voltage(opp); + max_volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); if (ret > 0) @@ -292,7 +292,7 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) return 0; free_freq_table: - opp_free_cpufreq_table(cpu_dev, &freq_table); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); put_node: of_node_put(np); return ret; @@ -301,7 +301,7 @@ put_node: static int imx6q_cpufreq_remove(struct platform_device *pdev) { cpufreq_unregister_driver(&imx6q_cpufreq_driver); - opp_free_cpufreq_table(cpu_dev, &freq_table); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); return 0; } diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c index f31fcfcad514..c5e31d296607 100644 --- a/drivers/cpufreq/omap-cpufreq.c +++ b/drivers/cpufreq/omap-cpufreq.c @@ -105,14 +105,14 @@ static int omap_target(struct cpufreq_policy *policy, if (mpu_reg) { rcu_read_lock(); - opp = opp_find_freq_ceil(mpu_dev, &freq); + opp = dev_pm_opp_find_freq_ceil(mpu_dev, &freq); if (IS_ERR(opp)) { rcu_read_unlock(); dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n", __func__, freqs.new); return -EINVAL; } - volt = opp_get_voltage(opp); + volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); tol = volt * OPP_TOLERANCE / 100; volt_old = regulator_get_voltage(mpu_reg); @@ -162,7 +162,7 @@ done: static inline void freq_table_free(void) { if (atomic_dec_and_test(&freq_table_users)) - opp_free_cpufreq_table(mpu_dev, &freq_table); + dev_pm_opp_free_cpufreq_table(mpu_dev, &freq_table); } static int omap_cpu_init(struct cpufreq_policy *policy) @@ -181,7 +181,7 @@ static int omap_cpu_init(struct cpufreq_policy *policy) policy->cur = omap_getspeed(policy->cpu); if (!freq_table) - result = opp_init_cpufreq_table(mpu_dev, &freq_table); + result = dev_pm_opp_init_cpufreq_table(mpu_dev, &freq_table); if (result) { dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n", diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index c99c00d35d34..f798edcb910d 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -908,7 +908,7 @@ static ssize_t available_frequencies_show(struct device *d, rcu_read_lock(); do { - opp = opp_find_freq_ceil(dev, &freq); + opp = dev_pm_opp_find_freq_ceil(dev, &freq); if (IS_ERR(opp)) break; @@ -1036,18 +1036,18 @@ struct opp *devfreq_recommended_opp(struct device *dev, unsigned long *freq, if (flags & DEVFREQ_FLAG_LEAST_UPPER_BOUND) { /* The freq is an upper bound. opp should be lower */ - opp = opp_find_freq_floor(dev, freq); + opp = dev_pm_opp_find_freq_floor(dev, freq); /* If not available, use the closest opp */ if (opp == ERR_PTR(-ERANGE)) - opp = opp_find_freq_ceil(dev, freq); + opp = dev_pm_opp_find_freq_ceil(dev, freq); } else { /* The freq is an lower bound. opp should be higher */ - opp = opp_find_freq_ceil(dev, freq); + opp = dev_pm_opp_find_freq_ceil(dev, freq); /* If not available, use the closest opp */ if (opp == ERR_PTR(-ERANGE)) - opp = opp_find_freq_floor(dev, freq); + opp = dev_pm_opp_find_freq_floor(dev, freq); } return opp; @@ -1066,7 +1066,7 @@ int devfreq_register_opp_notifier(struct device *dev, struct devfreq *devfreq) int ret = 0; rcu_read_lock(); - nh = opp_get_notifier(dev); + nh = dev_pm_opp_get_notifier(dev); if (IS_ERR(nh)) ret = PTR_ERR(nh); rcu_read_unlock(); @@ -1092,7 +1092,7 @@ int devfreq_unregister_opp_notifier(struct device *dev, struct devfreq *devfreq) int ret = 0; rcu_read_lock(); - nh = opp_get_notifier(dev); + nh = dev_pm_opp_get_notifier(dev); if (IS_ERR(nh)) ret = PTR_ERR(nh); rcu_read_unlock(); diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c index c5f86d8caca3..33c0e05a5ff1 100644 --- a/drivers/devfreq/exynos/exynos4_bus.c +++ b/drivers/devfreq/exynos/exynos4_bus.c @@ -650,8 +650,8 @@ static int exynos4_bus_target(struct device *dev, unsigned long *_freq, rcu_read_unlock(); return PTR_ERR(opp); } - new_oppinfo.rate = opp_get_freq(opp); - new_oppinfo.volt = opp_get_voltage(opp); + new_oppinfo.rate = dev_pm_opp_get_freq(opp); + new_oppinfo.volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); freq = new_oppinfo.rate; @@ -873,7 +873,7 @@ static int exynos4210_init_tables(struct busfreq_data *data) exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i]; for (i = LV_0; i < EX4210_LV_NUM; i++) { - err = opp_add(data->dev, exynos4210_busclk_table[i].clk, + err = dev_pm_opp_add(data->dev, exynos4210_busclk_table[i].clk, exynos4210_busclk_table[i].volt); if (err) { dev_err(data->dev, "Cannot add opp entries.\n"); @@ -940,7 +940,7 @@ static int exynos4x12_init_tables(struct busfreq_data *data) } for (i = 0; i < EX4x12_LV_NUM; i++) { - ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk, + ret = dev_pm_opp_add(data->dev, exynos4x12_mifclk_table[i].clk, exynos4x12_mifclk_table[i].volt); if (ret) { dev_err(data->dev, "Fail to add opp entries.\n"); @@ -969,7 +969,7 @@ static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this, data->disabled = true; rcu_read_lock(); - opp = opp_find_freq_floor(data->dev, &maxfreq); + opp = dev_pm_opp_find_freq_floor(data->dev, &maxfreq); if (IS_ERR(opp)) { rcu_read_unlock(); dev_err(data->dev, "%s: unable to find a min freq\n", @@ -977,8 +977,8 @@ static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this, mutex_unlock(&data->lock); return PTR_ERR(opp); } - new_oppinfo.rate = opp_get_freq(opp); - new_oppinfo.volt = opp_get_voltage(opp); + new_oppinfo.rate = dev_pm_opp_get_freq(opp); + new_oppinfo.volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); err = exynos4_bus_setvolt(data, &new_oppinfo, @@ -1065,15 +1065,16 @@ static int exynos4_busfreq_probe(struct platform_device *pdev) } rcu_read_lock(); - opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq); + opp = dev_pm_opp_find_freq_floor(dev, + &exynos4_devfreq_profile.initial_freq); if (IS_ERR(opp)) { rcu_read_unlock(); dev_err(dev, "Invalid initial frequency %lu kHz.\n", exynos4_devfreq_profile.initial_freq); return PTR_ERR(opp); } - data->curr_oppinfo.rate = opp_get_freq(opp); - data->curr_oppinfo.volt = opp_get_voltage(opp); + data->curr_oppinfo.rate = dev_pm_opp_get_freq(opp); + data->curr_oppinfo.volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); platform_set_drvdata(pdev, data); diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c index 574b16b59be5..b0e45925505b 100644 --- a/drivers/devfreq/exynos/exynos5_bus.c +++ b/drivers/devfreq/exynos/exynos5_bus.c @@ -144,8 +144,8 @@ static int exynos5_busfreq_int_target(struct device *dev, unsigned long *_freq, return PTR_ERR(opp); } - freq = opp_get_freq(opp); - volt = opp_get_voltage(opp); + freq = dev_pm_opp_get_freq(opp); + volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); old_freq = data->curr_freq; @@ -246,7 +246,7 @@ static int exynos5250_init_int_tables(struct busfreq_data_int *data) int i, err = 0; for (i = LV_0; i < _LV_END; i++) { - err = opp_add(data->dev, exynos5_int_opp_table[i].clk, + err = dev_pm_opp_add(data->dev, exynos5_int_opp_table[i].clk, exynos5_int_opp_table[i].volt); if (err) { dev_err(data->dev, "Cannot add opp entries.\n"); @@ -276,14 +276,14 @@ static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this, data->disabled = true; rcu_read_lock(); - opp = opp_find_freq_floor(data->dev, &maxfreq); + opp = dev_pm_opp_find_freq_floor(data->dev, &maxfreq); if (IS_ERR(opp)) { rcu_read_unlock(); err = PTR_ERR(opp); goto unlock; } - freq = opp_get_freq(opp); - volt = opp_get_voltage(opp); + freq = dev_pm_opp_get_freq(opp); + volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); err = exynos5_int_setvolt(data, volt); @@ -368,7 +368,7 @@ static int exynos5_busfreq_int_probe(struct platform_device *pdev) } rcu_read_lock(); - opp = opp_find_freq_floor(dev, + opp = dev_pm_opp_find_freq_floor(dev, &exynos5_devfreq_int_profile.initial_freq); if (IS_ERR(opp)) { rcu_read_unlock(); @@ -377,8 +377,8 @@ static int exynos5_busfreq_int_probe(struct platform_device *pdev) err = PTR_ERR(opp); goto err_opp_add; } - initial_freq = opp_get_freq(opp); - initial_volt = opp_get_voltage(opp); + initial_freq = dev_pm_opp_get_freq(opp); + initial_volt = dev_pm_opp_get_voltage(opp); rcu_read_unlock(); data->curr_freq = initial_freq; diff --git a/include/linux/opp.h b/include/linux/opp.h index 3aca2b8def33..2066ae5880c6 100644 --- a/include/linux/opp.h +++ b/include/linux/opp.h @@ -27,77 +27,79 @@ enum opp_event { #if defined(CONFIG_PM_OPP) -unsigned long opp_get_voltage(struct opp *opp); +unsigned long dev_pm_opp_get_voltage(struct opp *opp); -unsigned long opp_get_freq(struct opp *opp); +unsigned long dev_pm_opp_get_freq(struct opp *opp); -int opp_get_opp_count(struct device *dev); +int dev_pm_opp_get_opp_count(struct device *dev); -struct opp *opp_find_freq_exact(struct device *dev, unsigned long freq, +struct opp *dev_pm_opp_find_freq_exact(struct device *dev, unsigned long freq, bool available); -struct opp *opp_find_freq_floor(struct device *dev, unsigned long *freq); +struct opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq); -struct opp *opp_find_freq_ceil(struct device *dev, unsigned long *freq); +struct opp *dev_pm_opp_find_freq_ceil(struct device *dev, unsigned long *freq); -int opp_add(struct device *dev, unsigned long freq, unsigned long u_volt); +int dev_pm_opp_add(struct device *dev, unsigned long freq, + unsigned long u_volt); -int opp_enable(struct device *dev, unsigned long freq); +int dev_pm_opp_enable(struct device *dev, unsigned long freq); -int opp_disable(struct device *dev, unsigned long freq); +int dev_pm_opp_disable(struct device *dev, unsigned long freq); -struct srcu_notifier_head *opp_get_notifier(struct device *dev); +struct srcu_notifier_head *dev_pm_opp_get_notifier(struct device *dev); #else -static inline unsigned long opp_get_voltage(struct opp *opp) +static inline unsigned long dev_pm_opp_get_voltage(struct opp *opp) { return 0; } -static inline unsigned long opp_get_freq(struct opp *opp) +static inline unsigned long dev_pm_opp_get_freq(struct opp *opp) { return 0; } -static inline int opp_get_opp_count(struct device *dev) +static inline int dev_pm_opp_get_opp_count(struct device *dev) { return 0; } -static inline struct opp *opp_find_freq_exact(struct device *dev, +static inline struct opp *dev_pm_opp_find_freq_exact(struct device *dev, unsigned long freq, bool available) { return ERR_PTR(-EINVAL); } -static inline struct opp *opp_find_freq_floor(struct device *dev, +static inline struct opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq) { return ERR_PTR(-EINVAL); } -static inline struct opp *opp_find_freq_ceil(struct device *dev, +static inline struct opp *dev_pm_opp_find_freq_ceil(struct device *dev, unsigned long *freq) { return ERR_PTR(-EINVAL); } -static inline int opp_add(struct device *dev, unsigned long freq, +static inline int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long u_volt) { return -EINVAL; } -static inline int opp_enable(struct device *dev, unsigned long freq) +static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq) { return 0; } -static inline int opp_disable(struct device *dev, unsigned long freq) +static inline int dev_pm_opp_disable(struct device *dev, unsigned long freq) { return 0; } -static inline struct srcu_notifier_head *opp_get_notifier(struct device *dev) +static inline struct srcu_notifier_head *dev_pm_opp_get_notifier( + struct device *dev) { return ERR_PTR(-EINVAL); } @@ -113,19 +115,19 @@ static inline int of_init_opp_table(struct device *dev) #endif #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_PM_OPP) -int opp_init_cpufreq_table(struct device *dev, +int dev_pm_opp_init_cpufreq_table(struct device *dev, struct cpufreq_frequency_table **table); -void opp_free_cpufreq_table(struct device *dev, +void dev_pm_opp_free_cpufreq_table(struct device *dev, struct cpufreq_frequency_table **table); #else -static inline int opp_init_cpufreq_table(struct device *dev, +static inline int dev_pm_opp_init_cpufreq_table(struct device *dev, struct cpufreq_frequency_table **table) { return -EINVAL; } static inline -void opp_free_cpufreq_table(struct device *dev, +void dev_pm_opp_free_cpufreq_table(struct device *dev, struct cpufreq_frequency_table **table) { } -- cgit v1.2.3 From e4db1c7439b31993a4886b273bb9235a8eea82bf Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 19 Sep 2013 16:03:52 -0500 Subject: PM / OPP: rename header to linux/pm_opp.h Since Operating Performance Points (OPP) functions are specific to device specific power management, be specific and rename opp.h to pm_opp.h Reported-by: Randy Dunlap Signed-off-by: Nishanth Menon Signed-off-by: Rafael J. Wysocki --- Documentation/power/opp.txt | 2 +- arch/arm/mach-imx/mach-imx6q.c | 2 +- arch/arm/mach-omap2/board-omap3beagle.c | 2 +- arch/arm/mach-omap2/omap-pm.h | 2 +- arch/arm/mach-omap2/opp.c | 2 +- arch/arm/mach-omap2/pm.c | 2 +- drivers/base/power/opp.c | 2 +- drivers/cpufreq/arm_big_little.c | 2 +- drivers/cpufreq/arm_big_little_dt.c | 2 +- drivers/cpufreq/cpufreq-cpu0.c | 2 +- drivers/cpufreq/exynos5440-cpufreq.c | 2 +- drivers/cpufreq/imx6q-cpufreq.c | 2 +- drivers/cpufreq/omap-cpufreq.c | 2 +- drivers/devfreq/devfreq.c | 2 +- drivers/devfreq/exynos/exynos4_bus.c | 2 +- drivers/devfreq/exynos/exynos5_bus.c | 4 +- include/linux/devfreq.h | 2 +- include/linux/opp.h | 139 -------------------------------- include/linux/pm_opp.h | 139 ++++++++++++++++++++++++++++++++ 19 files changed, 157 insertions(+), 157 deletions(-) delete mode 100644 include/linux/opp.h create mode 100644 include/linux/pm_opp.h (limited to 'arch/arm/mach-imx') diff --git a/Documentation/power/opp.txt b/Documentation/power/opp.txt index 7f67e3d2c530..b8a907dc0169 100644 --- a/Documentation/power/opp.txt +++ b/Documentation/power/opp.txt @@ -42,7 +42,7 @@ We can represent these as three OPPs as the following {Hz, uV} tuples: OPP library provides a set of helper functions to organize and query the OPP information. The library is located in drivers/base/power/opp.c and the header -is located in include/linux/opp.h. OPP library can be enabled by enabling +is located in include/linux/pm_opp.h. OPP library can be enabled by enabling CONFIG_PM_OPP from power management menuconfig menu. OPP library depends on CONFIG_PM as certain SoCs such as Texas Instrument's OMAP framework allows to optionally boot at a certain OPP without needing cpufreq. diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index d7ecc90e6bba..699aabe296e1 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 33969e5a149f..6432ab8d9207 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-omap2/omap-pm.h b/arch/arm/mach-omap2/omap-pm.h index 67faa7b8fe92..1d777e63e05c 100644 --- a/arch/arm/mach-omap2/omap-pm.h +++ b/arch/arm/mach-omap2/omap-pm.h @@ -17,7 +17,7 @@ #include #include #include -#include +#include /* * agent_id values for use with omap_pm_set_min_bus_tput(): diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index 7b04637b13cb..ec21e6eb03e1 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c @@ -17,7 +17,7 @@ * GNU General Public License for more details. */ #include -#include +#include #include #include "omap_device.h" diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 92901bd41490..2f569b3c3092 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c index 693e14a24914..fa4187418440 100644 --- a/drivers/base/power/opp.c +++ b/drivers/base/power/opp.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/cpufreq/arm_big_little.c b/drivers/cpufreq/arm_big_little.c index 9e82a9d5df77..e010fb722c6b 100644 --- a/drivers/cpufreq/arm_big_little.c +++ b/drivers/cpufreq/arm_big_little.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/cpufreq/arm_big_little_dt.c b/drivers/cpufreq/arm_big_little_dt.c index 480c0bd0468d..8d9d59108906 100644 --- a/drivers/cpufreq/arm_big_little_dt.c +++ b/drivers/cpufreq/arm_big_little_dt.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c index d73107894fee..242d4900de47 100644 --- a/drivers/cpufreq/cpufreq-cpu0.c +++ b/drivers/cpufreq/cpufreq-cpu0.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c index c8b3d3950f9e..d41e77769d1a 100644 --- a/drivers/cpufreq/exynos5440-cpufreq.c +++ b/drivers/cpufreq/exynos5440-cpufreq.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index 84e993dfb305..e4c914066601 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c index f057d423020c..20190f56594f 100644 --- a/drivers/cpufreq/omap-cpufreq.c +++ b/drivers/cpufreq/omap-cpufreq.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 03530a0a8042..2e23b12c350b 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c index 891becd46513..cede6f71cd63 100644 --- a/drivers/devfreq/exynos/exynos4_bus.c +++ b/drivers/devfreq/exynos/exynos4_bus.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c index d06232aa0738..52835f12ac98 100644 --- a/drivers/devfreq/exynos/exynos5_bus.c +++ b/drivers/devfreq/exynos/exynos5_bus.c @@ -15,10 +15,10 @@ #include #include #include -#include +#include #include #include -#include +#include #include #include #include diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h index c8c995325ca8..7a7cc74d7f27 100644 --- a/include/linux/devfreq.h +++ b/include/linux/devfreq.h @@ -15,7 +15,7 @@ #include #include -#include +#include #define DEVFREQ_NAME_LEN 16 diff --git a/include/linux/opp.h b/include/linux/opp.h deleted file mode 100644 index 5151b0059585..000000000000 --- a/include/linux/opp.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Generic OPP Interface - * - * Copyright (C) 2009-2010 Texas Instruments Incorporated. - * Nishanth Menon - * Romit Dasgupta - * Kevin Hilman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __LINUX_OPP_H__ -#define __LINUX_OPP_H__ - -#include -#include -#include - -struct dev_pm_opp; -struct device; - -enum dev_pm_opp_event { - OPP_EVENT_ADD, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE, -}; - -#if defined(CONFIG_PM_OPP) - -unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp); - -unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp); - -int dev_pm_opp_get_opp_count(struct device *dev); - -struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, - unsigned long freq, - bool available); - -struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, - unsigned long *freq); - -struct dev_pm_opp *dev_pm_opp_find_freq_ceil(struct device *dev, - unsigned long *freq); - -int dev_pm_opp_add(struct device *dev, unsigned long freq, - unsigned long u_volt); - -int dev_pm_opp_enable(struct device *dev, unsigned long freq); - -int dev_pm_opp_disable(struct device *dev, unsigned long freq); - -struct srcu_notifier_head *dev_pm_opp_get_notifier(struct device *dev); -#else -static inline unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp) -{ - return 0; -} - -static inline unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp) -{ - return 0; -} - -static inline int dev_pm_opp_get_opp_count(struct device *dev) -{ - return 0; -} - -static inline struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, - unsigned long freq, bool available) -{ - return ERR_PTR(-EINVAL); -} - -static inline struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, - unsigned long *freq) -{ - return ERR_PTR(-EINVAL); -} - -static inline struct dev_pm_opp *dev_pm_opp_find_freq_ceil(struct device *dev, - unsigned long *freq) -{ - return ERR_PTR(-EINVAL); -} - -static inline int dev_pm_opp_add(struct device *dev, unsigned long freq, - unsigned long u_volt) -{ - return -EINVAL; -} - -static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq) -{ - return 0; -} - -static inline int dev_pm_opp_disable(struct device *dev, unsigned long freq) -{ - return 0; -} - -static inline struct srcu_notifier_head *dev_pm_opp_get_notifier( - struct device *dev) -{ - return ERR_PTR(-EINVAL); -} -#endif /* CONFIG_PM_OPP */ - -#if defined(CONFIG_PM_OPP) && defined(CONFIG_OF) -int of_init_opp_table(struct device *dev); -#else -static inline int of_init_opp_table(struct device *dev) -{ - return -EINVAL; -} -#endif - -#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_PM_OPP) -int dev_pm_opp_init_cpufreq_table(struct device *dev, - struct cpufreq_frequency_table **table); -void dev_pm_opp_free_cpufreq_table(struct device *dev, - struct cpufreq_frequency_table **table); -#else -static inline int dev_pm_opp_init_cpufreq_table(struct device *dev, - struct cpufreq_frequency_table **table) -{ - return -EINVAL; -} - -static inline -void dev_pm_opp_free_cpufreq_table(struct device *dev, - struct cpufreq_frequency_table **table) -{ -} -#endif /* CONFIG_CPU_FREQ */ - -#endif /* __LINUX_OPP_H__ */ diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h new file mode 100644 index 000000000000..5151b0059585 --- /dev/null +++ b/include/linux/pm_opp.h @@ -0,0 +1,139 @@ +/* + * Generic OPP Interface + * + * Copyright (C) 2009-2010 Texas Instruments Incorporated. + * Nishanth Menon + * Romit Dasgupta + * Kevin Hilman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_OPP_H__ +#define __LINUX_OPP_H__ + +#include +#include +#include + +struct dev_pm_opp; +struct device; + +enum dev_pm_opp_event { + OPP_EVENT_ADD, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE, +}; + +#if defined(CONFIG_PM_OPP) + +unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp); + +unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp); + +int dev_pm_opp_get_opp_count(struct device *dev); + +struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, + unsigned long freq, + bool available); + +struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, + unsigned long *freq); + +struct dev_pm_opp *dev_pm_opp_find_freq_ceil(struct device *dev, + unsigned long *freq); + +int dev_pm_opp_add(struct device *dev, unsigned long freq, + unsigned long u_volt); + +int dev_pm_opp_enable(struct device *dev, unsigned long freq); + +int dev_pm_opp_disable(struct device *dev, unsigned long freq); + +struct srcu_notifier_head *dev_pm_opp_get_notifier(struct device *dev); +#else +static inline unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp) +{ + return 0; +} + +static inline unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp) +{ + return 0; +} + +static inline int dev_pm_opp_get_opp_count(struct device *dev) +{ + return 0; +} + +static inline struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, + unsigned long freq, bool available) +{ + return ERR_PTR(-EINVAL); +} + +static inline struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, + unsigned long *freq) +{ + return ERR_PTR(-EINVAL); +} + +static inline struct dev_pm_opp *dev_pm_opp_find_freq_ceil(struct device *dev, + unsigned long *freq) +{ + return ERR_PTR(-EINVAL); +} + +static inline int dev_pm_opp_add(struct device *dev, unsigned long freq, + unsigned long u_volt) +{ + return -EINVAL; +} + +static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq) +{ + return 0; +} + +static inline int dev_pm_opp_disable(struct device *dev, unsigned long freq) +{ + return 0; +} + +static inline struct srcu_notifier_head *dev_pm_opp_get_notifier( + struct device *dev) +{ + return ERR_PTR(-EINVAL); +} +#endif /* CONFIG_PM_OPP */ + +#if defined(CONFIG_PM_OPP) && defined(CONFIG_OF) +int of_init_opp_table(struct device *dev); +#else +static inline int of_init_opp_table(struct device *dev) +{ + return -EINVAL; +} +#endif + +#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_PM_OPP) +int dev_pm_opp_init_cpufreq_table(struct device *dev, + struct cpufreq_frequency_table **table); +void dev_pm_opp_free_cpufreq_table(struct device *dev, + struct cpufreq_frequency_table **table); +#else +static inline int dev_pm_opp_init_cpufreq_table(struct device *dev, + struct cpufreq_frequency_table **table) +{ + return -EINVAL; +} + +static inline +void dev_pm_opp_free_cpufreq_table(struct device *dev, + struct cpufreq_frequency_table **table) +{ +} +#endif /* CONFIG_CPU_FREQ */ + +#endif /* __LINUX_OPP_H__ */ -- cgit v1.2.3 From 9b3d423707c3b1f6633be1be7e959623e10c596b Mon Sep 17 00:00:00 2001 From: Jiada Wang Date: Wed, 30 Oct 2013 04:25:51 -0700 Subject: ARM: i.MX6q: fix the wrong parent of can_root clock instead of pll3_usb_otg the parent of can_root clock should be pll3_60m. Signed-off-by: Jiada Wang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index d756d91fd741..edd522e8c4af 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -298,7 +298,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); - clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); + clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); -- cgit v1.2.3 From b6e23bb63f28f0a8ffa7cf9824fa48000c08f9b2 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 28 Oct 2013 16:37:12 +0800 Subject: ARM: imx: remove imx_src_prepare_restart() call There is ~10% possibility that the following emergency restart command fails to reboot imx6q. $ echo b > /proc/sysrq-trigger The IMX restart routine mxc_restart() assumes that it will always run on primary core, and will call imx_src_prepare_restart() to disable secondary cores in order to get them come to online in the following boot. However, the assumption is only true for normal kernel_restart() case where migrate_to_reboot_cpu() will be called to migrate to primary core, but not necessarily true for emergency_restart() case. So when emergency_restart() calls into mxc_restart() on any secondary core, system will hang immediately once imx_src_prepare_restart() is called to disabled secondary cores. Since emergency_restart() is defined as a function that is safe to call in interrupt context, we cannot just call migrate_to_reboot_cpu() to fix the issue. Fortunately, we just found that the issue can be fixed at imx6q platform level. We used to call imx_src_prepare_restart() to disable all secondary cores before resetting hardware. Otherwise, the secondary will fail come to online in the reboot. However, we recently found that after commit 6050d18 (ARM: imx: reset core along with enable/disable operation) comes to play, we do not need to reset the secondary cores any more. That said, mxc_restart() now can run on any core to reboot the system, as long as we remove the imx_src_prepare_restart() call from mxc_restart(). So let's simply remove imx_src_prepare_restart() call to fix the above emergency restart failure. Reported-by: Jiada Wang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 5 ----- arch/arm/mach-imx/src.c | 15 --------------- arch/arm/mach-imx/system.c | 3 --- 3 files changed, 23 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 7cbe22d0c6e9..24a7899e36a8 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -127,11 +127,6 @@ static inline void imx_smp_prepare(void) {} static inline void imx_scu_standby_enable(void) {} #endif void imx_src_init(void); -#ifdef CONFIG_HAVE_IMX_SRC -void imx_src_prepare_restart(void); -#else -static inline void imx_src_prepare_restart(void) {} -#endif void imx_gpc_init(void); void imx_gpc_pre_suspend(void); void imx_gpc_post_resume(void); diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 4754373e7e7d..45f7f4e0a447 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -115,21 +115,6 @@ void imx_set_cpu_arg(int cpu, u32 arg) writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); } -void imx_src_prepare_restart(void) -{ - u32 val; - - /* clear enable bits of secondary cores */ - spin_lock(&scr_lock); - val = readl_relaxed(src_base + SRC_SCR); - val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); - writel_relaxed(val, src_base + SRC_SCR); - spin_unlock(&scr_lock); - - /* clear persistent entry register of primary core */ - writel_relaxed(0, src_base + SRC_GPR1); -} - void __init imx_src_init(void) { struct device_node *np; diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index e6edcd38b282..826b72ba08d9 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -42,9 +42,6 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) { unsigned int wcr_enable; - if (cpu_is_imx6q() || cpu_is_imx6dl()) - imx_src_prepare_restart(); - if (wdog_clk) clk_enable(wdog_clk); -- cgit v1.2.3 From 2c11b57a8a8d83ffa91aebb12c90488c8802e6f3 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 31 Oct 2013 10:35:40 +0800 Subject: ARM: imx: improve mxc_restart() on the SRC bit writes The current comment in the code does not make it clear why the double writes on SRC bit is needed. Let's quote the errata to get it clear. Also, to ensure there are at least 2 writes happen in the same one 32kHz period, we actually need 3 writes. Let's add the third one. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/system.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 826b72ba08d9..5e3027d3692f 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -52,7 +52,14 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) /* Assert SRS signal */ __raw_writew(wcr_enable, wdog_base); - /* write twice to ensure the request will not get ignored */ + /* + * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be + * written twice), we add another two writes to ensure there must be at + * least two writes happen in the same one 32kHz clock period. We save + * the target check here, since the writes shouldn't be a huge burden + * for other platforms. + */ + __raw_writew(wcr_enable, wdog_base); __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ -- cgit v1.2.3 From 5d48217210a0ae4a08953b7e3db95ed5a992673d Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 31 Oct 2013 16:37:12 +0800 Subject: ARM: imx: v7_cpu_resume() is needed by imx6sl build Building a kernel with the following options, CONFIG_SMP=n CONFIG_PM=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6Q=n we will see the build error below. arch/arm/mach-imx/built-in.o: In function `imx6q_pm_enter': platform-spi_imx.c:(.text+0x2648): undefined reference to `v7_cpu_resume' make[1]: *** [vmlinux] Error 1 This is because that v7_cpu_resume() implemented in headsmp.S is also needed by imx6sl build. Let's build headsmp.S for CONFIG_SOC_IMX6SL as well. Reported-by: Russell King Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index bbe1f5bb799c..1789e2b31903 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -102,8 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o ifeq ($(CONFIG_PM),y) obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o -# i.MX6SL reuses pm-imx6q.c -obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o +# i.MX6SL reuses i.MX6Q code +obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o endif # i.MX5 based machines -- cgit v1.2.3 From ec9de6cd95a1ee326269699777301d5e1d5ddb75 Mon Sep 17 00:00:00 2001 From: Lothar Waßmann Date: Thu, 31 Oct 2013 12:55:48 +0100 Subject: ARM: imx6q: add missing sentinel to divider table The clk_enet_ref_table[] is missing a final empty entry as end of list marker. Also make the existing markers more obvious. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index edd522e8c4af..04cfd0fcb0e5 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -122,13 +122,14 @@ static struct clk_div_table clk_enet_ref_table[] = { { .val = 1, .div = 10, }, { .val = 2, .div = 5, }, { .val = 3, .div = 4, }, + { /* sentinel */ } }; static struct clk_div_table post_div_table[] = { { .val = 2, .div = 1, }, { .val = 1, .div = 2, }, { .val = 0, .div = 4, }, - { } + { /* sentinel */ } }; static struct clk_div_table video_div_table[] = { @@ -136,7 +137,7 @@ static struct clk_div_table video_div_table[] = { { .val = 1, .div = 2, }, { .val = 2, .div = 1, }, { .val = 3, .div = 4, }, - { } + { /* sentinel */ } }; static void __init imx6q_clocks_init(struct device_node *ccm_node) -- cgit v1.2.3 From 322503a15740bd9383bb4ed452e5dd5a40598170 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 30 Oct 2013 15:12:55 +0800 Subject: ARM: imx: add sleep for pllv3 relock The pllv3 relock time varies in the range of 50us ~ 500us, depending on the specific PLL type, e.g. 50us for ARM PLL and 450us for Audio/Video PLL. Let's add a usleep_range() call instead of doing busy wait during relock. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-pllv3.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index f6640b6a7b31..c9ca19184420 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -66,6 +67,7 @@ static int clk_pllv3_prepare(struct clk_hw *hw) break; if (time_after(jiffies, timeout)) break; + usleep_range(50, 500); } while (1); if (readl_relaxed(pll->base) & BM_PLL_LOCK) -- cgit v1.2.3 From bc3b84da8a55752d8c54005e558d59ac10fe9953 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 30 Oct 2013 15:56:22 +0800 Subject: ARM: imx: pllv3 needs relock in .set_rate() call The pllv3 nees relock not only when powering up but also when rate changes. The patch creates a helper function clk_pllv3_wait_lock() and moves the relock code from clk_pllv3_prepare() into there, so that both .prepare() and .set_rate() hooks of pllv3 can call into the helper for relocking. Since relock is only needed when PLL is powered up while clk_set_rate() could be called before clk is prepared, we need to add a check in clk_pllv3_wait_lock() to skip the relock if PLL is not powered. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-pllv3.c | 43 +++++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 18 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index c9ca19184420..df1736232961 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -46,21 +46,15 @@ struct clk_pllv3 { #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) -static int clk_pllv3_prepare(struct clk_hw *hw) +static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) { - struct clk_pllv3 *pll = to_clk_pllv3(hw); - unsigned long timeout; - u32 val; + unsigned long timeout = jiffies + msecs_to_jiffies(10); + u32 val = readl_relaxed(pll->base) & BM_PLL_POWER; - val = readl_relaxed(pll->base); - val &= ~BM_PLL_BYPASS; - if (pll->powerup_set) - val |= BM_PLL_POWER; - else - val &= ~BM_PLL_POWER; - writel_relaxed(val, pll->base); + /* No need to wait for lock when pll is not powered up */ + if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) + return 0; - timeout = jiffies + msecs_to_jiffies(10); /* Wait for PLL to lock */ do { if (readl_relaxed(pll->base) & BM_PLL_LOCK) @@ -70,10 +64,23 @@ static int clk_pllv3_prepare(struct clk_hw *hw) usleep_range(50, 500); } while (1); - if (readl_relaxed(pll->base) & BM_PLL_LOCK) - return 0; + return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; +} + +static int clk_pllv3_prepare(struct clk_hw *hw) +{ + struct clk_pllv3 *pll = to_clk_pllv3(hw); + u32 val; + + val = readl_relaxed(pll->base); + val &= ~BM_PLL_BYPASS; + if (pll->powerup_set) + val |= BM_PLL_POWER; else - return -ETIMEDOUT; + val &= ~BM_PLL_POWER; + writel_relaxed(val, pll->base); + + return clk_pllv3_wait_lock(pll); } static void clk_pllv3_unprepare(struct clk_hw *hw) @@ -148,7 +155,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, val |= div; writel_relaxed(val, pll->base); - return 0; + return clk_pllv3_wait_lock(pll); } static const struct clk_ops clk_pllv3_ops = { @@ -204,7 +211,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, val |= div; writel_relaxed(val, pll->base); - return 0; + return clk_pllv3_wait_lock(pll); } static const struct clk_ops clk_pllv3_sys_ops = { @@ -278,7 +285,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); - return 0; + return clk_pllv3_wait_lock(pll); } static const struct clk_ops clk_pllv3_av_ops = { -- cgit v1.2.3 From 43c9b9e8a4c64b1dd3026ab233703a4321ac6d7c Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 31 Oct 2013 09:46:17 +0800 Subject: ARM: imx: set up pllv3 POWER and BYPASS sequentially Currently, POWER and BYPASS bits are set up in a single write to pllv3 register. This causes problem occasionally from the IPU/HDMI testing. Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS sequentially. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-pllv3.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index df1736232961..61364050fccd 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -71,16 +71,24 @@ static int clk_pllv3_prepare(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; + int ret; val = readl_relaxed(pll->base); - val &= ~BM_PLL_BYPASS; if (pll->powerup_set) val |= BM_PLL_POWER; else val &= ~BM_PLL_POWER; writel_relaxed(val, pll->base); - return clk_pllv3_wait_lock(pll); + ret = clk_pllv3_wait_lock(pll); + if (ret) + return ret; + + val = readl_relaxed(pll->base); + val &= ~BM_PLL_BYPASS; + writel_relaxed(val, pll->base); + + return 0; } static void clk_pllv3_unprepare(struct clk_hw *hw) -- cgit v1.2.3