From 7268e0dd3eabee7368c09696dd2bd03a002cc896 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jan 2024 18:48:06 +0100 Subject: arm: dts: marvell: clearfog: add pro variant compatible in legacy dts Armada 388 Clearfog ("armada-388-clearfog.dts)" is a legacy filename for the Armada 388 Clearfog Pro ("armada-388-clearfog-pro.dts"). The "Pro" suffix was only used when the smaller version, the "Base" got released. The two names refer to exactly the same hardware, therefore they should share the same compatible strings. Copy "solidrun,clearfog-pro-a1" compatible from the -pro dts and add it to this legacy file. Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-388-clearfog.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts index 3290ccad2374..09bf2e6d4ed0 100644 --- a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts @@ -10,8 +10,9 @@ / { model = "SolidRun Clearfog A1"; - compatible = "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; + compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1", + "marvell,armada388", "marvell,armada385", + "marvell,armada380"; soc { internal-regs { -- cgit v1.2.3 From 668445d1c7ca4c0e056fda85935d2c291b46ac10 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jan 2024 18:48:07 +0100 Subject: arm: dts: marvell: clearfog-gtr: add board-specific compatible strings Most arm board have a board-specific compatible string that allows e.g. userspace to match specific firmware variants or apply specific policies. Add board-specific properties to both variants of the Clearfog GTR: - solidrun,clearfog-gtr-l8 - solidrun,clearfog-gtr-s4 Introduction of a common parent (e.g. "solidrun,clearfog-gtr") is omitted for brevity. Since announcement of the two products no additional variants were added it is assumed that there will always be just two. Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 2 ++ arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 1707d1b01545..7075b57820d4 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -4,6 +4,8 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", + "marvell,armada380"; }; &mdio { diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts index a7678a784c18..5f83d981449a 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts @@ -4,6 +4,8 @@ / { model = "SolidRun Clearfog GTR S4"; + compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385", + "marvell,armada380"; }; &sfp0 { -- cgit v1.2.3 From d265e1fecf4fdbf2aa46d278bc370890d8e7c707 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jan 2024 18:48:08 +0100 Subject: arm: dts: marvell: clearfog-gtr: sort pinctrl nodes alphabetically Cosmetic change to increase future patches readability when adding new pinctrl nodes. Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-385-clearfog-gtr.dtsi | 40 +++++++++++----------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi index d1452a04e904..8eabb60765b0 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -141,18 +141,13 @@ }; pinctrl@18000 { - cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { - marvell,pins = "mpp22"; + cf_gtr_fan_pwm: cf-gtr-fan-pwm { + marvell,pins = "mpp23"; marvell,function = "gpio"; }; - cf_gtr_fan_pwm: cf-gtr-fan-pwm { - marvell,pins = "mpp23"; + cf_gtr_front_button_pins: cf-gtr-front-button-pins { + marvell,pins = "mpp53"; marvell,function = "gpio"; }; @@ -162,13 +157,6 @@ marvell,function = "i2c1"; }; - cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; - cf_gtr_isolation_pins: cf-gtr-isolation-pins { marvell,pins = "mpp47"; marvell,function = "gpio"; @@ -179,18 +167,30 @@ marvell,function = "gpio"; }; + cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1"; }; - cf_gtr_front_button_pins: cf-gtr-front-button-pins { - marvell,pins = "mpp53"; + cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { + marvell,pins = "mpp18"; marvell,function = "gpio"; }; - cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { - marvell,pins = "mpp36"; + cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { + marvell,pins = "mpp22"; marvell,function = "gpio"; }; }; -- cgit v1.2.3 From 0d390855f61b03db829783311a175b272d0ebc17 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jan 2024 18:48:09 +0100 Subject: arm: dts: marvell: clearfog-gtr: add missing pinctrl for all used gpios Various control signals such as sfp module-absence, pci-e reset or led gpios were missing pinctrl nodes, leaving any u-boot choices in place. Since U-Boot is shared between multiple board variants, i.e. a388 clearfog pro / base, clearfog gtr l8 / s4, it is better to explicitly configure functions. Add explicit pinctrl entries for all gpios currently in use. Additionally the loss-of-signal gpio specified is invalid, in fact los only has a pull-up on the board but no gpio connection to the cpu. Remove this stray reference. Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-385-clearfog-gtr.dtsi | 42 ++++++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi index 8eabb60765b0..39ac97edb463 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -162,6 +162,22 @@ marvell,function = "gpio"; }; + cf_gtr_led_pins: led-pins { + marvell,pins = "mpp42", "mpp52"; + marvell,function = "gpio"; + }; + + cf_gtr_lte_disable_pins: lte-disable-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cf_gtr_pci_pins: pci-pins { + // pci reset + marvell,pins = "mpp33", "mpp35", "mpp44"; + marvell,function = "gpio"; + }; + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { marvell,pins = "mpp48"; marvell,function = "gpio"; @@ -179,6 +195,12 @@ marvell,function = "sd0"; }; + cf_gtr_sfp0_pins: sfp0-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp25", "mpp46"; + marvell,function = "gpio"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1"; @@ -193,6 +215,11 @@ marvell,pins = "mpp22"; marvell,function = "gpio"; }; + + cf_gtr_wifi_disable_pins: wifi-disable-pins { + marvell,pins = "mpp30", "mpp31"; + marvell,function = "gpio"; + }; }; sdhci@d8000 { @@ -221,21 +248,26 @@ }; pcie { + pinctrl-0 = <&cf_gtr_pci_pins>; + pinctrl-names = "default"; status = "okay"; /* * The PCIe units are accessible through * the mini-PCIe connectors on the board. */ + /* CON3 - serdes 0 */ pcie@1,0 { reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON4 - serdes 2 */ pcie@2,0 { reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON2 - serdes 4 */ pcie@3,0 { reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; @@ -243,10 +275,12 @@ }; }; + /* CON5 */ sfp0: sfp { compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp0_pins>; + pinctrl-names = "default"; i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; @@ -273,6 +307,8 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&cf_gtr_led_pins>; + pinctrl-names = "default"; led1 { function = LED_FUNCTION_CPU; @@ -408,7 +444,7 @@ }; &gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; wifi-disable { @@ -420,7 +456,7 @@ }; &gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; lte-disable { -- cgit v1.2.3 From 429cc56b8de40a51c2c08850ca717ef3e1c2bf3d Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 27 Feb 2024 17:23:11 +0100 Subject: arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector Clearfog GTR L8 has an extra SFP connector on the managed switch port 9. Add descriptions for both entities along with pinctrl. Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 20 +++++++++++++++++++- .../boot/dts/marvell/armada-385-clearfog-gtr.dtsi | 8 +++++++- 2 files changed, 26 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 7075b57820d4..1d6cfb975f48 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -6,6 +6,16 @@ model = "SolidRun Clearfog GTR L8"; compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", "marvell,armada380"; + + /* CON25 */ + sfp1: sfp-1 { + compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp1_pins>; + pinctrl-names = "default"; + i2c-bus = <&i2c0>; + mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; }; &mdio { @@ -68,11 +78,19 @@ phy-handle = <&switch0phy7>; }; + ethernet-port@9 { + reg = <9>; + label = "lan-sfp"; + phy-mode = "sgmii"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + ethernet-port@10 { reg = <10>; phy-mode = "2500base-x"; - ethernet = <ð1>; + fixed-link { speed = <2500>; full-duplex; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi index 39ac97edb463..f3a3cb6ac311 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -201,6 +201,12 @@ marvell,function = "gpio"; }; + cf_gtr_sfp1_pins: sfp1-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp24", "mpp54"; + marvell,function = "gpio"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1"; @@ -276,7 +282,7 @@ }; /* CON5 */ - sfp0: sfp { + sfp0: sfp-0 { compatible = "sff,sfp"; pinctrl-0 = <&cf_gtr_sfp0_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 2f9086ef0a20b4751e7c5b40a46becd44c336106 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jan 2024 18:48:11 +0100 Subject: arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure Clearfog GTR has an official enclosure with labels for all interfaces. The "lan" ports on the 8-port switch in device-tree were numbered in reverse wrt. enclosure. Update all device-tree labels to match. Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 1d6cfb975f48..cb85f8e31dfc 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -32,49 +32,49 @@ ethernet-port@1 { reg = <1>; - label = "lan8"; + label = "lan1"; phy-handle = <&switch0phy0>; }; ethernet-port@2 { reg = <2>; - label = "lan7"; + label = "lan2"; phy-handle = <&switch0phy1>; }; ethernet-port@3 { reg = <3>; - label = "lan6"; + label = "lan3"; phy-handle = <&switch0phy2>; }; ethernet-port@4 { reg = <4>; - label = "lan5"; + label = "lan4"; phy-handle = <&switch0phy3>; }; ethernet-port@5 { reg = <5>; - label = "lan4"; + label = "lan5"; phy-handle = <&switch0phy4>; }; ethernet-port@6 { reg = <6>; - label = "lan3"; + label = "lan6"; phy-handle = <&switch0phy5>; }; ethernet-port@7 { reg = <7>; - label = "lan2"; + label = "lan7"; phy-handle = <&switch0phy6>; }; ethernet-port@8 { reg = <8>; - label = "lan1"; + label = "lan8"; phy-handle = <&switch0phy7>; }; -- cgit v1.2.3