From 238dd317f74250983aefbde6dc0a1f345a717993 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 29 Aug 2010 17:08:44 +0200 Subject: MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost completely identical to AR7 except on a few points: - a second bank of gpios is available - vlynq0 on titan is vlynq1 on ar7 - different PHY addresses for cpmac0 This SoC can be found on commercial products like the Linksys WRTP54G Original patch by Xin with improvments by Florian. Signed-off-by: Xin Zhen Signed-off-by: Florian Fainelli Patchwork: http://patchwork.linux-mips.org/patch/1563/ Signed-off-by: Ralf Baechle --- --- arch/mips/include/asm/mach-ar7/ar7.h | 45 +++++++++++++++++++++++++++++++++-- arch/mips/include/asm/mach-ar7/gpio.h | 3 ++- 2 files changed, 45 insertions(+), 3 deletions(-) (limited to 'arch/mips/include/asm') diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h index ddb413e81d06..7919d76186bf 100644 --- a/arch/mips/include/asm/mach-ar7/ar7.h +++ b/arch/mips/include/asm/mach-ar7/ar7.h @@ -39,6 +39,7 @@ #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) +#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C) #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) @@ -50,6 +51,14 @@ #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) +/* Titan registers */ +#define TITAN_REGS_ESWITCH_BASE (0x08640000) +#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE) +#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800) +#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000) +#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00) +#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300) + #define AR7_RESET_PERIPHERAL 0x0 #define AR7_RESET_SOFTWARE 0x4 #define AR7_RESET_STATUS 0x8 @@ -59,15 +68,30 @@ #define AR7_RESET_BIT_MDIO 22 #define AR7_RESET_BIT_EPHY 26 +#define TITAN_RESET_BIT_EPHY1 28 + /* GPIO control registers */ #define AR7_GPIO_INPUT 0x0 #define AR7_GPIO_OUTPUT 0x4 #define AR7_GPIO_DIR 0x8 #define AR7_GPIO_ENABLE 0xc +#define TITAN_GPIO_INPUT_0 0x0 +#define TITAN_GPIO_INPUT_1 0x4 +#define TITAN_GPIO_OUTPUT_0 0x8 +#define TITAN_GPIO_OUTPUT_1 0xc +#define TITAN_GPIO_DIR_0 0x10 +#define TITAN_GPIO_DIR_1 0x14 +#define TITAN_GPIO_ENBL_0 0x18 +#define TITAN_GPIO_ENBL_1 0x1c #define AR7_CHIP_7100 0x18 #define AR7_CHIP_7200 0x2b #define AR7_CHIP_7300 0x05 +#define AR7_CHIP_TITAN 0x07 +#define TITAN_CHIP_1050 0x0f +#define TITAN_CHIP_1055 0x0e +#define TITAN_CHIP_1056 0x0d +#define TITAN_CHIP_1060 0x07 /* Interrupts */ #define AR7_IRQ_UART0 15 @@ -95,14 +119,29 @@ struct plat_dsl_data { extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; +static inline int ar7_is_titan(void) +{ + return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == + AR7_CHIP_TITAN; +} + static inline u16 ar7_chip_id(void) { - return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff; + return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *) + KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff); +} + +static inline u16 titan_chip_id(void) +{ + unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + + TITAN_GPIO_INPUT_1)); + return ((val >> 12) & 0x0f); } static inline u8 ar7_chip_rev(void) { - return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; + return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : + 0x14))) >> 16) & 0xff; } struct clk { @@ -163,4 +202,6 @@ static inline void ar7_device_off(u32 bit) int __init ar7_gpio_init(void); +int __init ar7_gpio_init(void); + #endif /* __AR7_H__ */ diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h index abc317c0372e..c177cd1eed25 100644 --- a/arch/mips/include/asm/mach-ar7/gpio.h +++ b/arch/mips/include/asm/mach-ar7/gpio.h @@ -22,7 +22,8 @@ #include #define AR7_GPIO_MAX 32 -#define NR_BUILTIN_GPIO AR7_GPIO_MAX +#define TITAN_GPIO_MAX 51 +#define NR_BUILTIN_GPIO TITAN_GPIO_MAX #define gpio_to_irq(gpio) -1 -- cgit v1.2.3