From 4eb0c00b6221f28b8988df37c9cb1bc5a2b91b39 Mon Sep 17 00:00:00 2001 From: David S. Miller Date: Thu, 5 Nov 2009 20:24:33 -0800 Subject: sparc64: Add a comment about why we only use certain memory barriers these days. Based upon feedback from Mathieu Desnoyers. Signed-off-by: David S. Miller --- arch/sparc/include/asm/system_64.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/sparc') diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h index 25e848f0cad7..d47a98e66972 100644 --- a/arch/sparc/include/asm/system_64.h +++ b/arch/sparc/include/asm/system_64.h @@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ : : : "memory"); \ } while (0) +/* The kernel always executes in TSO memory model these days, + * and furthermore most sparc64 chips implement more stringent + * memory ordering than required by the specifications. + */ #define mb() membar_safe("#StoreLoad") #define rmb() __asm__ __volatile__("":::"memory") #define wmb() __asm__ __volatile__("":::"memory") -- cgit v1.2.3