From 8c1ee96a2febee5a1dfb0e9d96c8f28a98f0a16b Mon Sep 17 00:00:00 2001 From: Shunli Wang Date: Fri, 4 Nov 2016 15:43:06 +0800 Subject: reset: mediatek: Add MT2701 reset driver In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by: Shunli Wang Signed-off-by: James Liao Signed-off-by: Erin Lo Tested-by: John Crispin Acked-by: Philipp Zabel Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt2701.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers/clk/mediatek/clk-mt2701.c') diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 6d2f82fa4339..6f26e6a37a6b 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -787,8 +787,12 @@ static int mtk_infrasys_init(struct platform_device *pdev) infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); + if (r) + return r; - return r; + mtk_register_reset_controller(node, 2, 0x30); + + return 0; } static const struct mtk_gate_regs peri0_cg_regs = { @@ -906,8 +910,12 @@ static int mtk_pericfg_init(struct platform_device *pdev) &mt2701_clk_lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + return r; - return r; + mtk_register_reset_controller(node, 2, 0x0); + + return 0; } #define MT8590_PLL_FMAX (2000 * MHZ) -- cgit v1.2.3