From df964016490b2cf630b1b926a1d5c610833aaa84 Mon Sep 17 00:00:00 2001 From: Abhishek Sahu Date: Wed, 13 Dec 2017 19:55:33 +0530 Subject: clk: qcom: add parent map for regmap mux Currently the driver assumes the register configuration value is identical to its index in the parent map. This patch adds the parent map field in regmap mux clock node which contains the mapping of parent index with actual register configuration value. If regmap node contains this parent map then the configuration value will be taken from this parent map instead of simply writing the index value. Signed-off-by: Abhishek Sahu Signed-off-by: Stephen Boyd --- drivers/clk/qcom/clk-rcg.h | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers/clk/qcom/clk-rcg.h') diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index a2495457e564..2a7489a84e69 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -25,16 +25,6 @@ struct freq_tbl { u16 n; }; -/** - * struct parent_map - map table for PLL source select configuration values - * @src: source PLL - * @cfg: configuration value - */ -struct parent_map { - u8 src; - u8 cfg; -}; - /** * struct mn - M/N:D counter * @mnctr_en_bit: bit to enable mn counter -- cgit v1.2.3