From c0c81245dac7caaef4db627fb7043495d1afe662 Mon Sep 17 00:00:00 2001 From: Yunhao Tian Date: Wed, 21 Jul 2021 20:48:16 +0800 Subject: clk: rockchip: make rk3308 ddrphy4x clock critical Currently, no driver support for DDR memory controller (DMC) is present, as a result, no driver is explicitly consuming the ddrphy clock. This means that VPLL1 (parent of ddr clock) will be shutdown if we enable and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX). If VPLL1 is disabled, the whole system will freeze, because the DDR controller will lose its clock. So, it's necessary to prevent VPLL1 from shutting down, by marking the ddrphy4x CLK_IS_CRITICAL. This bug was discovered when I was porting rockchip_i2s_tdm driver to mainline kernel from Rockchip 4.4 kernel. I guess that other Rockchip SoCs without DMC driver may need the same patch. If this applies to other devices, please let us know. Signed-off-by: Yunhao Tian Link: https://lore.kernel.org/r/BYAPR20MB24886765F888A9705CBEB70789E39@BYAPR20MB2488.namprd20.prod.outlook.com [adapted subject, changed to add the clock to the critical list] Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-rk3308.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/rockchip') diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c index 2c3bd0c749f2..db3396c3e6e9 100644 --- a/drivers/clk/rockchip/clk-rk3308.c +++ b/drivers/clk/rockchip/clk-rk3308.c @@ -911,6 +911,7 @@ static const char *const rk3308_critical_clocks[] __initconst = { "hclk_audio", "pclk_audio", "sclk_ddrc", + "clk_ddrphy4x", }; static void __init rk3308_clk_init(struct device_node *np) -- cgit v1.2.3