From c369596f895be88d09f4165b223fa31c64aaefd4 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 29 Dec 2016 14:36:50 +0100 Subject: clk: samsung: Add CPU clk configuration data for Exynos4412 Prime Add cpu clock configuration data for Exynos4412 Prime SoC (it supports additional PLL rates & CPU frequencies). Based on Hardkernel's kernel for ODROID-X2/U2/U3 boards. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/clk/samsung') diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index faab9b31baf5..e40b77583c47 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1298,6 +1298,8 @@ static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = }; static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { + PLL_35XX_RATE(1704000000, 213, 3, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), PLL_35XX_RATE(1500000000, 250, 4, 0), PLL_35XX_RATE(1400000000, 175, 3, 0), PLL_35XX_RATE(1300000000, 325, 6, 0), @@ -1421,6 +1423,8 @@ static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = { (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { + { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), }, + { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), }, -- cgit v1.2.3