From f0acaf9d6912240cf1a27f0f75d04cf149086da9 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 29 Aug 2022 16:18:09 +0300 Subject: drm/i915: move and group max_bw and bw_obj under display.bw Move display bandwidth related members under drm_i915_private display sub-struct. v2: Rebase Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/c8b9e2fdc5c226ffb71759a20e561c832a774ba5.1661779055.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'drivers/gpu/drm/i915/i915_drv.h') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 51afb5e744d7..2c63cdb64511 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -44,7 +44,6 @@ #include "display/intel_dsb.h" #include "display/intel_fbc.h" #include "display/intel_frontbuffer.h" -#include "display/intel_global_state.h" #include "display/intel_opregion.h" #include "gem/i915_gem_context_types.h" @@ -204,14 +203,8 @@ i915_fence_timeout(const struct drm_i915_private *i915) return i915_fence_context_timeout(i915, U64_MAX); } -/* Amount of SAGV/QGV points, BSpec precisely defines this */ -#define I915_NUM_QGV_POINTS 8 - #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) -/* Amount of PSF GV points, BSpec precisely defines this */ -#define I915_NUM_PSF_GV_POINTS 3 - struct intel_vbt_data { /* bdb version */ u16 version; @@ -470,18 +463,6 @@ struct drm_i915_private { u8 num_psf_gv_points; } dram_info; - struct intel_bw_info { - /* for each QGV point */ - unsigned int deratedbw[I915_NUM_QGV_POINTS]; - /* for each PSF GV point */ - unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; - u8 num_qgv_points; - u8 num_psf_gv_points; - u8 num_planes; - } max_bw[6]; - - struct intel_global_obj bw_obj; - struct intel_runtime_pm runtime_pm; struct i915_perf perf; -- cgit v1.2.3