From b8f3ebe630a4f1b4ff9340103d3b565ad5d78d43 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Wed, 23 Mar 2016 19:08:20 +0800 Subject: irqchip: Add Layerscape SCFG MSI controller support Some kind of Freescale Layerscape SoC provides a MSI implementation which uses two SCFG registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it. Signed-off-by: Minghuan Lian Tested-by: Alexander Stein Acked-by: Marc Zyngier Signed-off-by: Marc Zyngier --- drivers/irqchip/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/irqchip/Makefile') diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e354b00c173d..8cedf9060565 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -66,3 +66,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o +obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o -- cgit v1.2.3