From 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Mon Sep 17 00:00:00 2001
From: Linus Torvalds
Date: Sat, 16 Apr 2005 15:20:36 -0700
Subject: Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
---
drivers/net/wan/Kconfig | 607 ++++
drivers/net/wan/Makefile | 86 +
drivers/net/wan/c101.c | 446 +++
drivers/net/wan/cosa.c | 2100 +++++++++++++
drivers/net/wan/cosa.h | 117 +
drivers/net/wan/cycx_drv.c | 586 ++++
drivers/net/wan/cycx_main.c | 351 +++
drivers/net/wan/cycx_x25.c | 1609 ++++++++++
drivers/net/wan/dlci.c | 566 ++++
drivers/net/wan/dscc4.c | 2074 +++++++++++++
drivers/net/wan/farsync.c | 2712 +++++++++++++++++
drivers/net/wan/farsync.h | 357 +++
drivers/net/wan/hd64570.h | 241 ++
drivers/net/wan/hd64572.h | 527 ++++
drivers/net/wan/hd6457x.c | 853 ++++++
drivers/net/wan/hdlc_cisco.c | 330 +++
drivers/net/wan/hdlc_fr.c | 1237 ++++++++
drivers/net/wan/hdlc_generic.c | 343 +++
drivers/net/wan/hdlc_ppp.c | 115 +
drivers/net/wan/hdlc_raw.c | 90 +
drivers/net/wan/hdlc_raw_eth.c | 107 +
drivers/net/wan/hdlc_x25.c | 219 ++
drivers/net/wan/hostess_sv11.c | 420 +++
drivers/net/wan/lapbether.c | 465 +++
drivers/net/wan/lmc/Makefile | 17 +
drivers/net/wan/lmc/lmc.h | 33 +
drivers/net/wan/lmc/lmc_debug.c | 85 +
drivers/net/wan/lmc/lmc_debug.h | 52 +
drivers/net/wan/lmc/lmc_ioctl.h | 257 ++
drivers/net/wan/lmc/lmc_main.c | 2201 ++++++++++++++
drivers/net/wan/lmc/lmc_media.c | 1246 ++++++++
drivers/net/wan/lmc/lmc_media.h | 65 +
drivers/net/wan/lmc/lmc_prot.h | 15 +
drivers/net/wan/lmc/lmc_proto.c | 249 ++
drivers/net/wan/lmc/lmc_proto.h | 16 +
drivers/net/wan/lmc/lmc_var.h | 570 ++++
drivers/net/wan/n2.c | 562 ++++
drivers/net/wan/pc300-falc-lh.h | 1238 ++++++++
drivers/net/wan/pc300.h | 497 ++++
drivers/net/wan/pc300_drv.c | 3692 +++++++++++++++++++++++
drivers/net/wan/pc300_tty.c | 1095 +++++++
drivers/net/wan/pci200syn.c | 488 ++++
drivers/net/wan/sbni.c | 1735 +++++++++++
drivers/net/wan/sbni.h | 141 +
drivers/net/wan/sdla.c | 1676 +++++++++++
drivers/net/wan/sdla_chdlc.c | 4433 ++++++++++++++++++++++++++++
drivers/net/wan/sdla_fr.c | 5068 ++++++++++++++++++++++++++++++++
drivers/net/wan/sdla_ft1.c | 344 +++
drivers/net/wan/sdla_ppp.c | 3429 ++++++++++++++++++++++
drivers/net/wan/sdla_x25.c | 5496 +++++++++++++++++++++++++++++++++++
drivers/net/wan/sdladrv.c | 2318 +++++++++++++++
drivers/net/wan/sdlamain.c | 1341 +++++++++
drivers/net/wan/sealevel.c | 469 +++
drivers/net/wan/syncppp.c | 1488 ++++++++++
drivers/net/wan/wanpipe_multppp.c | 2357 +++++++++++++++
drivers/net/wan/wanxl.c | 839 ++++++
drivers/net/wan/wanxl.h | 152 +
drivers/net/wan/wanxlfw.S | 895 ++++++
drivers/net/wan/wanxlfw.inc_shipped | 158 +
drivers/net/wan/x25_asy.c | 844 ++++++
drivers/net/wan/x25_asy.h | 50 +
drivers/net/wan/z85230.c | 1851 ++++++++++++
drivers/net/wan/z85230.h | 449 +++
63 files changed, 64469 insertions(+)
create mode 100644 drivers/net/wan/Kconfig
create mode 100644 drivers/net/wan/Makefile
create mode 100644 drivers/net/wan/c101.c
create mode 100644 drivers/net/wan/cosa.c
create mode 100644 drivers/net/wan/cosa.h
create mode 100644 drivers/net/wan/cycx_drv.c
create mode 100644 drivers/net/wan/cycx_main.c
create mode 100644 drivers/net/wan/cycx_x25.c
create mode 100644 drivers/net/wan/dlci.c
create mode 100644 drivers/net/wan/dscc4.c
create mode 100644 drivers/net/wan/farsync.c
create mode 100644 drivers/net/wan/farsync.h
create mode 100644 drivers/net/wan/hd64570.h
create mode 100644 drivers/net/wan/hd64572.h
create mode 100644 drivers/net/wan/hd6457x.c
create mode 100644 drivers/net/wan/hdlc_cisco.c
create mode 100644 drivers/net/wan/hdlc_fr.c
create mode 100644 drivers/net/wan/hdlc_generic.c
create mode 100644 drivers/net/wan/hdlc_ppp.c
create mode 100644 drivers/net/wan/hdlc_raw.c
create mode 100644 drivers/net/wan/hdlc_raw_eth.c
create mode 100644 drivers/net/wan/hdlc_x25.c
create mode 100644 drivers/net/wan/hostess_sv11.c
create mode 100644 drivers/net/wan/lapbether.c
create mode 100644 drivers/net/wan/lmc/Makefile
create mode 100644 drivers/net/wan/lmc/lmc.h
create mode 100644 drivers/net/wan/lmc/lmc_debug.c
create mode 100644 drivers/net/wan/lmc/lmc_debug.h
create mode 100644 drivers/net/wan/lmc/lmc_ioctl.h
create mode 100644 drivers/net/wan/lmc/lmc_main.c
create mode 100644 drivers/net/wan/lmc/lmc_media.c
create mode 100644 drivers/net/wan/lmc/lmc_media.h
create mode 100644 drivers/net/wan/lmc/lmc_prot.h
create mode 100644 drivers/net/wan/lmc/lmc_proto.c
create mode 100644 drivers/net/wan/lmc/lmc_proto.h
create mode 100644 drivers/net/wan/lmc/lmc_var.h
create mode 100644 drivers/net/wan/n2.c
create mode 100644 drivers/net/wan/pc300-falc-lh.h
create mode 100644 drivers/net/wan/pc300.h
create mode 100644 drivers/net/wan/pc300_drv.c
create mode 100644 drivers/net/wan/pc300_tty.c
create mode 100644 drivers/net/wan/pci200syn.c
create mode 100644 drivers/net/wan/sbni.c
create mode 100644 drivers/net/wan/sbni.h
create mode 100644 drivers/net/wan/sdla.c
create mode 100644 drivers/net/wan/sdla_chdlc.c
create mode 100644 drivers/net/wan/sdla_fr.c
create mode 100644 drivers/net/wan/sdla_ft1.c
create mode 100644 drivers/net/wan/sdla_ppp.c
create mode 100644 drivers/net/wan/sdla_x25.c
create mode 100644 drivers/net/wan/sdladrv.c
create mode 100644 drivers/net/wan/sdlamain.c
create mode 100644 drivers/net/wan/sealevel.c
create mode 100644 drivers/net/wan/syncppp.c
create mode 100644 drivers/net/wan/wanpipe_multppp.c
create mode 100644 drivers/net/wan/wanxl.c
create mode 100644 drivers/net/wan/wanxl.h
create mode 100644 drivers/net/wan/wanxlfw.S
create mode 100644 drivers/net/wan/wanxlfw.inc_shipped
create mode 100644 drivers/net/wan/x25_asy.c
create mode 100644 drivers/net/wan/x25_asy.h
create mode 100644 drivers/net/wan/z85230.c
create mode 100644 drivers/net/wan/z85230.h
(limited to 'drivers/net/wan')
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
new file mode 100644
index 000000000000..35791934a602
--- /dev/null
+++ b/drivers/net/wan/Kconfig
@@ -0,0 +1,607 @@
+#
+# wan devices configuration
+#
+
+menu "Wan interfaces"
+ depends on NETDEVICES
+
+config WAN
+ bool "Wan interfaces support"
+ ---help---
+ Wide Area Networks (WANs), such as X.25, Frame Relay and leased
+ lines, are used to interconnect Local Area Networks (LANs) over vast
+ distances with data transfer rates significantly higher than those
+ achievable with commonly used asynchronous modem connections.
+
+ Usually, a quite expensive external device called a `WAN router' is
+ needed to connect to a WAN. As an alternative, a relatively
+ inexpensive WAN interface card can allow your Linux box to directly
+ connect to a WAN.
+
+ If you have one of those cards and wish to use it under Linux,
+ say Y here and also to the WAN driver for your card.
+
+ If unsure, say N.
+
+# There is no way to detect a comtrol sv11 - force it modular for now.
+config HOSTESS_SV11
+ tristate "Comtrol Hostess SV-11 support"
+ depends on WAN && ISA && m
+ help
+ Driver for Comtrol Hostess SV-11 network card which
+ operates on low speed synchronous serial links at up to
+ 256Kbps, supporting PPP and Cisco HDLC.
+
+ The driver will be compiled as a module: the
+ module will be called hostess_sv11.
+
+# The COSA/SRP driver has not been tested as non-modular yet.
+config COSA
+ tristate "COSA/SRP sync serial boards support"
+ depends on WAN && ISA && m
+ ---help---
+ Driver for COSA and SRP synchronous serial boards.
+
+ These boards allow to connect synchronous serial devices (for example
+ base-band modems, or any other device with the X.21, V.24, V.35 or
+ V.36 interface) to your Linux box. The cards can work as the
+ character device, synchronous PPP network device, or the Cisco HDLC
+ network device.
+
+ You will need user-space utilities COSA or SRP boards for downloading
+ the firmware to the cards and to set them up. Look at the
+ for more information. You can also
+ read the comment at the top of the for
+ details about the cards and the driver itself.
+
+ The driver will be compiled as a module: the
+ module will be called cosa.
+
+config DSCC4
+ tristate "Etinc PCISYNC serial board support"
+ depends on WAN && PCI && m
+ help
+ Driver for Etinc PCISYNC boards based on the Infineon (ex. Siemens)
+ DSCC4 chipset.
+
+ This is supposed to work with the four port card. Take a look at
+ for further information about the
+ driver.
+
+ To compile this driver as a module, choose M here: the
+ module will be called dscc4.
+
+config DSCC4_PCISYNC
+ bool "Etinc PCISYNC features"
+ depends on DSCC4
+ help
+ Due to Etinc's design choice for its PCISYNC cards, some operations
+ are only allowed on specific ports of the DSCC4. This option is the
+ only way for the driver to know that it shouldn't return a success
+ code for these operations.
+
+ Please say Y if your card is an Etinc's PCISYNC.
+
+config DSCC4_PCI_RST
+ bool "Hard reset support"
+ depends on DSCC4
+ help
+ Various DSCC4 bugs forbid any reliable software reset of the ASIC.
+ As a replacement, some vendors provide a way to assert the PCI #RST
+ pin of DSCC4 through the GPIO port of the card. If you choose Y,
+ the driver will make use of this feature before module removal
+ (i.e. rmmod). The feature is known to be available on Commtech's
+ cards. Contact your manufacturer for details.
+
+ Say Y if your card supports this feature.
+
+#
+# Lan Media's board. Currently 1000, 1200, 5200, 5245
+#
+config LANMEDIA
+ tristate "LanMedia Corp. SSI/V.35, T1/E1, HSSI, T3 boards"
+ depends on WAN && PCI
+ ---help---
+ Driver for the following Lan Media family of serial boards:
+
+ - LMC 1000 board allows you to connect synchronous serial devices
+ (for example base-band modems, or any other device with the X.21,
+ V.24, V.35 or V.36 interface) to your Linux box.
+
+ - LMC 1200 with on board DSU board allows you to connect your Linux
+ box directly to a T1 or E1 circuit.
+
+ - LMC 5200 board provides a HSSI interface capable of running up to
+ 52 Mbits per second.
+
+ - LMC 5245 board connects directly to a T3 circuit saving the
+ additional external hardware.
+
+ To change setting such as syncPPP vs Cisco HDLC or clock source you
+ will need lmcctl. It is available at
+ (broken link).
+
+ To compile this driver as a module, choose M here: the
+ module will be called lmc.
+
+# There is no way to detect a Sealevel board. Force it modular
+config SEALEVEL_4021
+ tristate "Sealevel Systems 4021 support"
+ depends on WAN && ISA && m
+ help
+ This is a driver for the Sealevel Systems ACB 56 serial I/O adapter.
+
+ The driver will be compiled as a module: the
+ module will be called sealevel.
+
+config SYNCLINK_SYNCPPP
+ tristate "SyncLink HDLC/SYNCPPP support"
+ depends on WAN
+ help
+ Enables HDLC/SYNCPPP support for the SyncLink WAN driver.
+
+ Normally the SyncLink WAN driver works with the main PPP driver
+ and pppd program.
+ HDLC/SYNCPPP support allows use of the Cisco HDLC/PPP driver
+ . The SyncLink WAN driver (in
+ character devices) must also be enabled.
+
+# Generic HDLC
+config HDLC
+ tristate "Generic HDLC layer"
+ depends on WAN
+ help
+ Say Y to this option if your Linux box contains a WAN (Wide Area
+ Network) card supported by this driver and you are planning to
+ connect the box to a WAN.
+
+ You will need supporting software from
+ .
+ Generic HDLC driver currently supports raw HDLC, Cisco HDLC, Frame
+ Relay, synchronous Point-to-Point Protocol (PPP) and X.25.
+
+ To compile this driver as a module, choose M here: the
+ module will be called hdlc.
+
+ If unsure, say N.
+
+config HDLC_RAW
+ bool "Raw HDLC support"
+ depends on HDLC
+ help
+ Generic HDLC driver supporting raw HDLC over WAN connections.
+
+ If unsure, say N.
+
+config HDLC_RAW_ETH
+ bool "Raw HDLC Ethernet device support"
+ depends on HDLC
+ help
+ Generic HDLC driver supporting raw HDLC Ethernet device emulation
+ over WAN connections.
+
+ You will need it for Ethernet over HDLC bridges.
+
+ If unsure, say N.
+
+config HDLC_CISCO
+ bool "Cisco HDLC support"
+ depends on HDLC
+ help
+ Generic HDLC driver supporting Cisco HDLC over WAN connections.
+
+ If unsure, say N.
+
+config HDLC_FR
+ bool "Frame Relay support"
+ depends on HDLC
+ help
+ Generic HDLC driver supporting Frame Relay over WAN connections.
+
+ If unsure, say N.
+
+config HDLC_PPP
+ bool "Synchronous Point-to-Point Protocol (PPP) support"
+ depends on HDLC
+ help
+ Generic HDLC driver supporting PPP over WAN connections.
+
+ If unsure, say N.
+
+config HDLC_X25
+ bool "X.25 protocol support"
+ depends on HDLC && (LAPB=m && HDLC=m || LAPB=y)
+ help
+ Generic HDLC driver supporting X.25 over WAN connections.
+
+ If unsure, say N.
+
+comment "X.25/LAPB support is disabled"
+ depends on WAN && HDLC && (LAPB!=m || HDLC!=m) && LAPB!=y
+
+config PCI200SYN
+ tristate "Goramo PCI200SYN support"
+ depends on HDLC && PCI
+ help
+ Driver for PCI200SYN cards by Goramo sp. j.
+
+ If you have such a card, say Y here and see
+ .
+
+ To compile this as a module, choose M here: the
+ module will be called pci200syn.
+
+ If unsure, say N.
+
+config WANXL
+ tristate "SBE Inc. wanXL support"
+ depends on HDLC && PCI
+ help
+ Driver for wanXL PCI cards by SBE Inc.
+
+ If you have such a card, say Y here and see
+ .
+
+ To compile this as a module, choose M here: the
+ module will be called wanxl.
+
+ If unsure, say N.
+
+config WANXL_BUILD_FIRMWARE
+ bool "rebuild wanXL firmware"
+ depends on WANXL && !PREVENT_FIRMWARE_BUILD
+ help
+ Allows you to rebuild firmware run by the QUICC processor.
+ It requires as68k, ld68k and hexdump programs.
+
+ You should never need this option, say N.
+
+config PC300
+ tristate "Cyclades-PC300 support (RS-232/V.35, X.21, T1/E1 boards)"
+ depends on HDLC && PCI
+ ---help---
+ Driver for the Cyclades-PC300 synchronous communication boards.
+
+ These boards provide synchronous serial interfaces to your
+ Linux box (interfaces currently available are RS-232/V.35, X.21 and
+ T1/E1). If you wish to support Multilink PPP, please select the
+ option later and read the file README.mlppp provided by PC300
+ package.
+
+ To compile this as a module, choose M here: the module
+ will be called pc300.
+
+ If unsure, say N.
+
+config PC300_MLPPP
+ bool "Cyclades-PC300 MLPPP support"
+ depends on PC300 && PPP_MULTILINK && PPP_SYNC_TTY && HDLC_PPP
+ help
+ Multilink PPP over the PC300 synchronous communication boards.
+
+comment "Cyclades-PC300 MLPPP support is disabled."
+ depends on WAN && HDLC && PC300 && (PPP=n || !PPP_MULTILINK || PPP_SYNC_TTY=n || !HDLC_PPP)
+
+comment "Refer to the file README.mlppp, provided by PC300 package."
+ depends on WAN && HDLC && PC300 && (PPP=n || !PPP_MULTILINK || PPP_SYNC_TTY=n || !HDLC_PPP)
+
+config N2
+ tristate "SDL RISCom/N2 support"
+ depends on HDLC && ISA
+ help
+ Driver for RISCom/N2 single or dual channel ISA cards by
+ SDL Communications Inc.
+
+ If you have such a card, say Y here and see
+ .
+
+ Note that N2csu and N2dds cards are not supported by this driver.
+
+ To compile this driver as a module, choose M here: the module
+ will be called n2.
+
+ If unsure, say N.
+
+config C101
+ tristate "Moxa C101 support"
+ depends on HDLC && ISA
+ help
+ Driver for C101 SuperSync ISA cards by Moxa Technologies Co., Ltd.
+
+ If you have such a card, say Y here and see
+ .
+
+ To compile this driver as a module, choose M here: the
+ module will be called c101.
+
+ If unsure, say N.
+
+config FARSYNC
+ tristate "FarSync T-Series support"
+ depends on HDLC && PCI
+ ---help---
+ Support for the FarSync T-Series X.21 (and V.35/V.24) cards by
+ FarSite Communications Ltd.
+
+ Synchronous communication is supported on all ports at speeds up to
+ 8Mb/s (128K on V.24) using synchronous PPP, Cisco HDLC, raw HDLC,
+ Frame Relay or X.25/LAPB.
+
+ If you want the module to be automatically loaded when the interface
+ is referenced then you should add "alias hdlcX farsync" to
+ /etc/modprobe.conf for each interface, where X is 0, 1, 2, ..., or
+ simply use "alias hdlc* farsync" to indicate all of them.
+
+ To compile this driver as a module, choose M here: the
+ module will be called farsync.
+
+config DLCI
+ tristate "Frame Relay DLCI support"
+ depends on WAN
+ ---help---
+ Support for the Frame Relay protocol.
+
+ Frame Relay is a fast low-cost way to connect to a remote Internet
+ access provider or to form a private wide area network. The one
+ physical line from your box to the local "switch" (i.e. the entry
+ point to the Frame Relay network, usually at the phone company) can
+ carry several logical point-to-point connections to other computers
+ connected to the Frame Relay network. For a general explanation of
+ the protocol, check out .
+
+ To use frame relay, you need supporting hardware (called FRAD) and
+ certain programs from the net-tools package as explained in
+ .
+
+ To compile this driver as a module, choose M here: the
+ module will be called dlci.
+
+config DLCI_COUNT
+ int "Max open DLCI"
+ depends on DLCI
+ default "24"
+ help
+ Maximal number of logical point-to-point frame relay connections
+ (the identifiers of which are called DCLIs) that the driver can
+ handle.
+
+ The default is probably fine.
+
+config DLCI_MAX
+ int "Max DLCI per device"
+ depends on DLCI
+ default "8"
+ help
+ How many logical point-to-point frame relay connections (the
+ identifiers of which are called DCLIs) should be handled by each
+ of your hardware frame relay access devices.
+
+ Go with the default.
+
+config SDLA
+ tristate "SDLA (Sangoma S502/S508) support"
+ depends on DLCI && ISA
+ help
+ Driver for the Sangoma S502A, S502E, and S508 Frame Relay Access
+ Devices.
+
+ These are multi-protocol cards, but only Frame Relay is supported
+ by the driver at this time. Please read
+ .
+
+ To compile this driver as a module, choose M here: the
+ module will be called sdla.
+
+# Wan router core.
+config WAN_ROUTER_DRIVERS
+ bool "WAN router drivers"
+ depends on WAN && WAN_ROUTER
+ ---help---
+ Connect LAN to WAN via Linux box.
+
+ Select driver your card and remember to say Y to "Wan Router."
+ You will need the wan-tools package which is available from
+ . For more information read:
+ .
+
+ Note that the answer to this question won't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about WAN router drivers.
+
+ If unsure, say N.
+
+config VENDOR_SANGOMA
+ tristate "Sangoma WANPIPE(tm) multiprotocol cards"
+ depends on WAN_ROUTER_DRIVERS && WAN_ROUTER && (PCI || ISA) && BROKEN
+ ---help---
+ Driver for S514-PCI/ISA Synchronous Data Link Adapters (SDLA).
+
+ WANPIPE from Sangoma Technologies Inc.
+ is a family of intelligent multiprotocol WAN adapters with data
+ transfer rates up to 4Mbps. Cards support:
+
+ - X.25, Frame Relay, PPP, Cisco HDLC protocols.
+
+ - API for protocols like HDLC (LAPB), HDLC Streaming, X.25,
+ Frame Relay and BiSync.
+
+ - Ethernet Bridging over Frame Relay protocol.
+
+ - MULTILINK PPP
+
+ - Async PPP (Modem Dialup)
+
+ The next questions will ask you about the protocols you want
+ the driver to support.
+
+ If you have one or more of these cards, say M to this option;
+ and read .
+
+ To compile this driver as a module, choose M here: the
+ module will be called wanpipe.
+
+config WANPIPE_CHDLC
+ bool "WANPIPE Cisco HDLC support"
+ depends on VENDOR_SANGOMA
+ ---help---
+ Connect a WANPIPE card to a leased line using the Cisco HDLC.
+
+ - Supports Dual Port Cisco HDLC on the S514-PCI/S508-ISA cards
+ which allows user to build applications using the HDLC streaming API.
+
+ - CHDLC Streaming MULTILINK PPP that can bind multiple WANPIPE T1
+ cards into a single logical channel.
+
+ Say Y and the Cisco HDLC support, HDLC streaming API and
+ MULTILINK PPP will be included in the driver.
+
+config WANPIPE_FR
+ bool "WANPIPE Frame Relay support"
+ depends on VENDOR_SANGOMA
+ help
+ Connect a WANPIPE card to a Frame Relay network, or use Frame Felay
+ API to develop custom applications.
+
+ Contains the Ethernet Bridging over Frame Relay feature, where
+ a WANPIPE frame relay link can be directly connected to the Linux
+ kernel bridge. The Frame Relay option is supported on S514-PCI
+ and S508-ISA cards.
+
+ Say Y and the Frame Relay support will be included in the driver.
+
+config WANPIPE_X25
+ bool "WANPIPE X.25 support"
+ depends on VENDOR_SANGOMA
+ help
+ Connect a WANPIPE card to an X.25 network.
+
+ Includes the X.25 API support for custom applications over the
+ X.25 protocol. The X.25 option is supported on S514-PCI and
+ S508-ISA cards.
+
+ Say Y and the X.25 support will be included in the driver.
+
+config WANPIPE_PPP
+ bool "WANPIPE PPP support"
+ depends on VENDOR_SANGOMA
+ help
+ Connect a WANPIPE card to a leased line using Point-to-Point
+ Protocol (PPP).
+
+ The PPP option is supported on S514-PCI/S508-ISA cards.
+
+ Say Y and the PPP support will be included in the driver.
+
+config WANPIPE_MULTPPP
+ bool "WANPIPE Multi-Port PPP support"
+ depends on VENDOR_SANGOMA
+ help
+ Connect a WANPIPE card to a leased line using Point-to-Point
+ Protocol (PPP).
+
+ Uses in-kernel SyncPPP protocol over the Sangoma HDLC Streaming
+ adapter. In this case each Sangoma adapter port can support an
+ independent PPP connection. For example, a single Quad-Port PCI
+ adapter can support up to four independent PPP links. The PPP
+ option is supported on S514-PCI/S508-ISA cards.
+
+ Say Y and the Multi-Port PPP support will be included in the driver.
+
+config CYCLADES_SYNC
+ tristate "Cyclom 2X(tm) cards (EXPERIMENTAL)"
+ depends on WAN_ROUTER_DRIVERS && (PCI || ISA)
+ ---help---
+ Cyclom 2X from Cyclades Corporation is an
+ intelligent multiprotocol WAN adapter with data transfer rates up to
+ 512 Kbps. These cards support the X.25 and SNA related protocols.
+
+ While no documentation is available at this time please grab the
+ wanconfig tarball in
+ (with minor changes
+ to make it compile with the current wanrouter include files; efforts
+ are being made to use the original package available at
+ ).
+
+ Feel free to contact me or the cycsyn-devel mailing list at
+ and for
+ additional details, I hope to have documentation available as soon as
+ possible. (Cyclades Brazil is writing the Documentation).
+
+ The next questions will ask you about the protocols you want the
+ driver to support (for now only X.25 is supported).
+
+ If you have one or more of these cards, say Y to this option.
+
+ To compile this driver as a module, choose M here: the
+ module will be called cyclomx.
+
+config CYCLOMX_X25
+ bool "Cyclom 2X X.25 support (EXPERIMENTAL)"
+ depends on CYCLADES_SYNC
+ help
+ Connect a Cyclom 2X card to an X.25 network.
+
+ Enabling X.25 support will enlarge your kernel by about 11 kB.
+
+# X.25 network drivers
+config LAPBETHER
+ tristate "LAPB over Ethernet driver (EXPERIMENTAL)"
+ depends on WAN && LAPB && X25
+ ---help---
+ Driver for a pseudo device (typically called /dev/lapb0) which allows
+ you to open an LAPB point-to-point connection to some other computer
+ on your Ethernet network.
+
+ In order to do this, you need to say Y or M to the driver for your
+ Ethernet card as well as to "LAPB Data Link Driver".
+
+ To compile this driver as a module, choose M here: the
+ module will be called lapbether.
+
+ If unsure, say N.
+
+config X25_ASY
+ tristate "X.25 async driver (EXPERIMENTAL)"
+ depends on WAN && LAPB && X25
+ ---help---
+ Send and receive X.25 frames over regular asynchronous serial
+ lines such as telephone lines equipped with ordinary modems.
+
+ Experts should note that this driver doesn't currently comply with
+ the asynchronous HDLS framing protocols in CCITT recommendation X.25.
+
+ To compile this driver as a module, choose M here: the
+ module will be called x25_asy.
+
+ If unsure, say N.
+
+config SBNI
+ tristate "Granch SBNI12 Leased Line adapter support"
+ depends on WAN && X86
+ ---help---
+ Driver for ISA SBNI12-xx cards which are low cost alternatives to
+ leased line modems.
+
+ You can find more information and last versions of drivers and
+ utilities at . If you have any question you
+ can send email to .
+
+ To compile this driver as a module, choose M here: the
+ module will be called sbni.
+
+ If unsure, say N.
+
+config SBNI_MULTILINE
+ bool "Multiple line feature support"
+ depends on SBNI
+ help
+ Schedule traffic for some parallel lines, via SBNI12 adapters.
+
+ If you have two computers connected with two parallel lines it's
+ possible to increase transfer rate nearly twice. You should have
+ a program named 'sbniconfig' to configure adapters.
+
+ If unsure, say N.
+
+endmenu
+
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
new file mode 100644
index 000000000000..ce6c56b903e7
--- /dev/null
+++ b/drivers/net/wan/Makefile
@@ -0,0 +1,86 @@
+#
+# Makefile for the Linux network (wan) device drivers.
+#
+# 3 Aug 2000, Christoph Hellwig
+# Rewritten to use lists instead of if-statements.
+#
+
+wanpipe-y := sdlamain.o sdla_ft1.o
+wanpipe-$(CONFIG_WANPIPE_X25) += sdla_x25.o
+wanpipe-$(CONFIG_WANPIPE_FR) += sdla_fr.o
+wanpipe-$(CONFIG_WANPIPE_CHDLC) += sdla_chdlc.o
+wanpipe-$(CONFIG_WANPIPE_PPP) += sdla_ppp.o
+wanpipe-$(CONFIG_WANPIPE_MULTPPP) += wanpipe_multppp.o
+wanpipe-objs := $(wanpipe-y)
+
+cyclomx-y := cycx_main.o
+cyclomx-$(CONFIG_CYCLOMX_X25) += cycx_x25.o
+cyclomx-objs := $(cyclomx-y)
+
+hdlc-y := hdlc_generic.o
+hdlc-$(CONFIG_HDLC_RAW) += hdlc_raw.o
+hdlc-$(CONFIG_HDLC_RAW_ETH) += hdlc_raw_eth.o
+hdlc-$(CONFIG_HDLC_CISCO) += hdlc_cisco.o
+hdlc-$(CONFIG_HDLC_FR) += hdlc_fr.o
+hdlc-$(CONFIG_HDLC_PPP) += hdlc_ppp.o
+hdlc-$(CONFIG_HDLC_X25) += hdlc_x25.o
+hdlc-objs := $(hdlc-y)
+
+pc300-y := pc300_drv.o
+pc300-$(CONFIG_PC300_MLPPP) += pc300_tty.o
+pc300-objs := $(pc300-y)
+
+obj-$(CONFIG_HOSTESS_SV11) += z85230.o syncppp.o hostess_sv11.o
+obj-$(CONFIG_SEALEVEL_4021) += z85230.o syncppp.o sealevel.o
+obj-$(CONFIG_COSA) += syncppp.o cosa.o
+obj-$(CONFIG_FARSYNC) += syncppp.o farsync.o
+obj-$(CONFIG_DSCC4) += dscc4.o
+obj-$(CONFIG_LANMEDIA) += syncppp.o
+obj-$(CONFIG_SYNCLINK_SYNCPPP) += syncppp.o
+obj-$(CONFIG_X25_ASY) += x25_asy.o
+
+obj-$(CONFIG_LANMEDIA) += lmc/
+
+obj-$(CONFIG_DLCI) += dlci.o
+obj-$(CONFIG_SDLA) += sdla.o
+ifeq ($(CONFIG_WANPIPE_MULTPPP),y)
+ obj-$(CONFIG_VENDOR_SANGOMA) += sdladrv.o wanpipe.o syncppp.o
+else
+ obj-$(CONFIG_VENDOR_SANGOMA) += sdladrv.o wanpipe.o
+endif
+obj-$(CONFIG_CYCLADES_SYNC) += cycx_drv.o cyclomx.o
+obj-$(CONFIG_LAPBETHER) += lapbether.o
+obj-$(CONFIG_SBNI) += sbni.o
+obj-$(CONFIG_PC300) += pc300.o
+obj-$(CONFIG_HDLC) += hdlc.o
+ifeq ($(CONFIG_HDLC_PPP),y)
+ obj-$(CONFIG_HDLC) += syncppp.o
+endif
+obj-$(CONFIG_N2) += n2.o
+obj-$(CONFIG_C101) += c101.o
+obj-$(CONFIG_WANXL) += wanxl.o
+obj-$(CONFIG_PCI200SYN) += pci200syn.o
+
+clean-files := wanxlfw.inc
+$(obj)/wanxl.o: $(obj)/wanxlfw.inc
+
+ifeq ($(CONFIG_WANXL_BUILD_FIRMWARE),y)
+ifeq ($(ARCH),m68k)
+ AS68K = $(AS)
+ LD68K = $(LD)
+else
+ AS68K = as68k
+ LD68K = ld68k
+endif
+
+quiet_cmd_build_wanxlfw = BLD FW $@
+ cmd_build_wanxlfw = \
+ $(CPP) -Wp,-MD,$(depfile) -I$(srctree)/include $< | $(AS68K) -m68360 -o $(obj)/wanxlfw.o; \
+ $(LD68K) --oformat binary -Ttext 0x1000 $(obj)/wanxlfw.o -o $(obj)/wanxlfw.bin; \
+ hexdump -ve '"\n" 16/1 "0x%02X,"' $(obj)/wanxlfw.bin | sed 's/0x ,//g;1s/^/static u8 firmware[]={/;$$s/,$$/\n};\n/' >$(obj)/wanxlfw.inc; \
+ rm -f $(obj)/wanxlfw.bin $(obj)/wanxlfw.o
+
+$(obj)/wanxlfw.inc: $(src)/wanxlfw.S
+ $(call if_changed_dep,build_wanxlfw)
+targets += wanxlfw.inc
+endif
diff --git a/drivers/net/wan/c101.c b/drivers/net/wan/c101.c
new file mode 100644
index 000000000000..43d854ace233
--- /dev/null
+++ b/drivers/net/wan/c101.c
@@ -0,0 +1,446 @@
+/*
+ * Moxa C101 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2000-2003 Krzysztof Halasa
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * For information see http://hq.pm.waw.pl/hdlc/
+ *
+ * Sources of information:
+ * Hitachi HD64570 SCA User's Manual
+ * Moxa C101 User's Manual
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "hd64570.h"
+
+
+static const char* version = "Moxa C101 driver version: 1.15";
+static const char* devname = "C101";
+
+#undef DEBUG_PKT
+#define DEBUG_RINGS
+
+#define C101_PAGE 0x1D00
+#define C101_DTR 0x1E00
+#define C101_SCA 0x1F00
+#define C101_WINDOW_SIZE 0x2000
+#define C101_MAPPED_RAM_SIZE 0x4000
+
+#define RAM_SIZE (256 * 1024)
+#define TX_RING_BUFFERS 10
+#define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) / \
+ (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
+
+#define CLOCK_BASE 9830400 /* 9.8304 MHz */
+#define PAGE0_ALWAYS_MAPPED
+
+static char *hw; /* pointer to hw=xxx command line string */
+
+
+typedef struct card_s {
+ struct net_device *dev;
+ spinlock_t lock; /* TX lock */
+ u8 __iomem *win0base; /* ISA window base address */
+ u32 phy_winbase; /* ISA physical base address */
+ sync_serial_settings settings;
+ int rxpart; /* partial frame received, next frame invalid*/
+ unsigned short encoding;
+ unsigned short parity;
+ u16 rx_ring_buffers; /* number of buffers in a ring */
+ u16 tx_ring_buffers;
+ u16 buff_offset; /* offset of first buffer of first channel */
+ u16 rxin; /* rx ring buffer 'in' pointer */
+ u16 txin; /* tx ring buffer 'in' and 'last' pointers */
+ u16 txlast;
+ u8 rxs, txs, tmc; /* SCA registers */
+ u8 irq; /* IRQ (3-15) */
+ u8 page;
+
+ struct card_s *next_card;
+}card_t;
+
+typedef card_t port_t;
+
+static card_t *first_card;
+static card_t **new_card = &first_card;
+
+
+#define sca_in(reg, card) readb((card)->win0base + C101_SCA + (reg))
+#define sca_out(value, reg, card) writeb(value, (card)->win0base + C101_SCA + (reg))
+#define sca_inw(reg, card) readw((card)->win0base + C101_SCA + (reg))
+
+/* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
+#define sca_outw(value, reg, card) do { \
+ writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
+ writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg+1));\
+} while(0)
+
+#define port_to_card(port) (port)
+#define log_node(port) (0)
+#define phy_node(port) (0)
+#define winsize(card) (C101_WINDOW_SIZE)
+#define win0base(card) ((card)->win0base)
+#define winbase(card) ((card)->win0base + 0x2000)
+#define get_port(card, port) (card)
+static void sca_msci_intr(port_t *port);
+
+
+static inline u8 sca_get_page(card_t *card)
+{
+ return card->page;
+}
+
+static inline void openwin(card_t *card, u8 page)
+{
+ card->page = page;
+ writeb(page, card->win0base + C101_PAGE);
+}
+
+
+#include "hd6457x.c"
+
+
+static void sca_msci_intr(port_t *port)
+{
+ struct net_device *dev = port_to_dev(port);
+ card_t* card = port_to_card(port);
+ u8 stat = sca_in(MSCI1_OFFSET + ST1, card); /* read MSCI ST1 status */
+
+ /* Reset MSCI TX underrun status bit */
+ sca_out(stat & ST1_UDRN, MSCI0_OFFSET + ST1, card);
+
+ if (stat & ST1_UDRN) {
+ struct net_device_stats *stats = hdlc_stats(dev);
+ stats->tx_errors++; /* TX Underrun error detected */
+ stats->tx_fifo_errors++;
+ }
+
+ /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
+ sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, card);
+
+ if (stat & ST1_CDCD)
+ hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, card) & ST3_DCD),
+ dev);
+}
+
+
+static void c101_set_iface(port_t *port)
+{
+ u8 rxs = port->rxs & CLK_BRG_MASK;
+ u8 txs = port->txs & CLK_BRG_MASK;
+
+ switch(port->settings.clock_type) {
+ case CLOCK_INT:
+ rxs |= CLK_BRG_RX; /* TX clock */
+ txs |= CLK_RXCLK_TX; /* BRG output */
+ break;
+
+ case CLOCK_TXINT:
+ rxs |= CLK_LINE_RX; /* RXC input */
+ txs |= CLK_BRG_TX; /* BRG output */
+ break;
+
+ case CLOCK_TXFROMRX:
+ rxs |= CLK_LINE_RX; /* RXC input */
+ txs |= CLK_RXCLK_TX; /* RX clock */
+ break;
+
+ default: /* EXTernal clock */
+ rxs |= CLK_LINE_RX; /* RXC input */
+ txs |= CLK_LINE_TX; /* TXC input */
+ }
+
+ port->rxs = rxs;
+ port->txs = txs;
+ sca_out(rxs, MSCI1_OFFSET + RXS, port);
+ sca_out(txs, MSCI1_OFFSET + TXS, port);
+ sca_set_port(port);
+}
+
+
+static int c101_open(struct net_device *dev)
+{
+ port_t *port = dev_to_port(dev);
+ int result;
+
+ result = hdlc_open(dev);
+ if (result)
+ return result;
+
+ writeb(1, port->win0base + C101_DTR);
+ sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
+ sca_open(dev);
+ /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
+ sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
+ sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
+
+ hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD), dev);
+ printk(KERN_DEBUG "0x%X\n", sca_in(MSCI1_OFFSET + ST3, port));
+
+ /* enable MSCI1 CDCD interrupt */
+ sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
+ sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
+ sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
+ c101_set_iface(port);
+ return 0;
+}
+
+
+static int c101_close(struct net_device *dev)
+{
+ port_t *port = dev_to_port(dev);
+
+ sca_close(dev);
+ writeb(0, port->win0base + C101_DTR);
+ sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
+ hdlc_close(dev);
+ return 0;
+}
+
+
+static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ const size_t size = sizeof(sync_serial_settings);
+ sync_serial_settings new_line;
+ sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
+ port_t *port = dev_to_port(dev);
+
+#ifdef DEBUG_RINGS
+ if (cmd == SIOCDEVPRIVATE) {
+ sca_dump_rings(dev);
+ printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
+ sca_in(MSCI1_OFFSET + ST0, port),
+ sca_in(MSCI1_OFFSET + ST1, port),
+ sca_in(MSCI1_OFFSET + ST2, port),
+ sca_in(MSCI1_OFFSET + ST3, port));
+ return 0;
+ }
+#endif
+ if (cmd != SIOCWANDEV)
+ return hdlc_ioctl(dev, ifr, cmd);
+
+ switch(ifr->ifr_settings.type) {
+ case IF_GET_IFACE:
+ ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
+ if (ifr->ifr_settings.size < size) {
+ ifr->ifr_settings.size = size; /* data size wanted */
+ return -ENOBUFS;
+ }
+ if (copy_to_user(line, &port->settings, size))
+ return -EFAULT;
+ return 0;
+
+ case IF_IFACE_SYNC_SERIAL:
+ if(!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ if (copy_from_user(&new_line, line, size))
+ return -EFAULT;
+
+ if (new_line.clock_type != CLOCK_EXT &&
+ new_line.clock_type != CLOCK_TXFROMRX &&
+ new_line.clock_type != CLOCK_INT &&
+ new_line.clock_type != CLOCK_TXINT)
+ return -EINVAL; /* No such clock setting */
+
+ if (new_line.loopback != 0 && new_line.loopback != 1)
+ return -EINVAL;
+
+ memcpy(&port->settings, &new_line, size); /* Update settings */
+ c101_set_iface(port);
+ return 0;
+
+ default:
+ return hdlc_ioctl(dev, ifr, cmd);
+ }
+}
+
+
+
+static void c101_destroy_card(card_t *card)
+{
+ readb(card->win0base + C101_PAGE); /* Resets SCA? */
+
+ if (card->irq)
+ free_irq(card->irq, card);
+
+ if (card->win0base) {
+ iounmap(card->win0base);
+ release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
+ }
+
+ free_netdev(card->dev);
+
+ kfree(card);
+}
+
+
+
+static int __init c101_run(unsigned long irq, unsigned long winbase)
+{
+ struct net_device *dev;
+ hdlc_device *hdlc;
+ card_t *card;
+ int result;
+
+ if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
+ printk(KERN_ERR "c101: invalid IRQ value\n");
+ return -ENODEV;
+ }
+
+ if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
+ printk(KERN_ERR "c101: invalid RAM value\n");
+ return -ENODEV;
+ }
+
+ card = kmalloc(sizeof(card_t), GFP_KERNEL);
+ if (card == NULL) {
+ printk(KERN_ERR "c101: unable to allocate memory\n");
+ return -ENOBUFS;
+ }
+ memset(card, 0, sizeof(card_t));
+
+ card->dev = alloc_hdlcdev(card);
+ if (!card->dev) {
+ printk(KERN_ERR "c101: unable to allocate memory\n");
+ kfree(card);
+ return -ENOBUFS;
+ }
+
+ if (request_irq(irq, sca_intr, 0, devname, card)) {
+ printk(KERN_ERR "c101: could not allocate IRQ\n");
+ c101_destroy_card(card);
+ return(-EBUSY);
+ }
+ card->irq = irq;
+
+ if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
+ printk(KERN_ERR "c101: could not request RAM window\n");
+ c101_destroy_card(card);
+ return(-EBUSY);
+ }
+ card->phy_winbase = winbase;
+ card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
+ if (!card->win0base) {
+ printk(KERN_ERR "c101: could not map I/O address\n");
+ c101_destroy_card(card);
+ return -EBUSY;
+ }
+
+ card->tx_ring_buffers = TX_RING_BUFFERS;
+ card->rx_ring_buffers = RX_RING_BUFFERS;
+ card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
+
+ readb(card->win0base + C101_PAGE); /* Resets SCA? */
+ udelay(100);
+ writeb(0, card->win0base + C101_PAGE);
+ writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
+
+ sca_init(card, 0);
+
+ dev = port_to_dev(card);
+ hdlc = dev_to_hdlc(dev);
+
+ spin_lock_init(&card->lock);
+ SET_MODULE_OWNER(dev);
+ dev->irq = irq;
+ dev->mem_start = winbase;
+ dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
+ dev->tx_queue_len = 50;
+ dev->do_ioctl = c101_ioctl;
+ dev->open = c101_open;
+ dev->stop = c101_close;
+ hdlc->attach = sca_attach;
+ hdlc->xmit = sca_xmit;
+ card->settings.clock_type = CLOCK_EXT;
+
+ result = register_hdlc_device(dev);
+ if (result) {
+ printk(KERN_WARNING "c101: unable to register hdlc device\n");
+ c101_destroy_card(card);
+ return result;
+ }
+
+ sca_init_sync_port(card); /* Set up C101 memory */
+ hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, card) & ST3_DCD), dev);
+
+ printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
+ " using %u TX + %u RX packets rings\n",
+ dev->name, card->irq,
+ card->tx_ring_buffers, card->rx_ring_buffers);
+
+ *new_card = card;
+ new_card = &card->next_card;
+ return 0;
+}
+
+
+
+static int __init c101_init(void)
+{
+ if (hw == NULL) {
+#ifdef MODULE
+ printk(KERN_INFO "c101: no card initialized\n");
+#endif
+ return -ENOSYS; /* no parameters specified, abort */
+ }
+
+ printk(KERN_INFO "%s\n", version);
+
+ do {
+ unsigned long irq, ram;
+
+ irq = simple_strtoul(hw, &hw, 0);
+
+ if (*hw++ != ',')
+ break;
+ ram = simple_strtoul(hw, &hw, 0);
+
+ if (*hw == ':' || *hw == '\x0')
+ c101_run(irq, ram);
+
+ if (*hw == '\x0')
+ return first_card ? 0 : -ENOSYS;
+ }while(*hw++ == ':');
+
+ printk(KERN_ERR "c101: invalid hardware parameters\n");
+ return first_card ? 0 : -ENOSYS;
+}
+
+
+static void __exit c101_cleanup(void)
+{
+ card_t *card = first_card;
+
+ while (card) {
+ card_t *ptr = card;
+ card = card->next_card;
+ unregister_hdlc_device(port_to_dev(ptr));
+ c101_destroy_card(ptr);
+ }
+}
+
+
+module_init(c101_init);
+module_exit(c101_cleanup);
+
+MODULE_AUTHOR("Krzysztof Halasa ");
+MODULE_DESCRIPTION("Moxa C101 serial port driver");
+MODULE_LICENSE("GPL v2");
+module_param(hw, charp, 0444); /* hw=irq,ram:irq,... */
diff --git a/drivers/net/wan/cosa.c b/drivers/net/wan/cosa.c
new file mode 100644
index 000000000000..921a573372e9
--- /dev/null
+++ b/drivers/net/wan/cosa.c
@@ -0,0 +1,2100 @@
+/* $Id: cosa.c,v 1.31 2000/03/08 17:47:16 kas Exp $ */
+
+/*
+ * Copyright (C) 1995-1997 Jan "Yenya" Kasprzak
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * The driver for the SRP and COSA synchronous serial cards.
+ *
+ * HARDWARE INFO
+ *
+ * Both cards are developed at the Institute of Computer Science,
+ * Masaryk University (http://www.ics.muni.cz/). The hardware is
+ * developed by Jiri Novotny . More information
+ * and the photo of both cards is available at
+ * http://www.pavoucek.cz/cosa.html. The card documentation, firmwares
+ * and other goods can be downloaded from ftp://ftp.ics.muni.cz/pub/cosa/.
+ * For Linux-specific utilities, see below in the "Software info" section.
+ * If you want to order the card, contact Jiri Novotny.
+ *
+ * The SRP (serial port?, the Czech word "srp" means "sickle") card
+ * is a 2-port intelligent (with its own 8-bit CPU) synchronous serial card
+ * with V.24 interfaces up to 80kb/s each.
+ *
+ * The COSA (communication serial adapter?, the Czech word "kosa" means
+ * "scythe") is a next-generation sync/async board with two interfaces
+ * - currently any of V.24, X.21, V.35 and V.36 can be selected.
+ * It has a 16-bit SAB80166 CPU and can do up to 10 Mb/s per channel.
+ * The 8-channels version is in development.
+ *
+ * Both types have downloadable firmware and communicate via ISA DMA.
+ * COSA can be also a bus-mastering device.
+ *
+ * SOFTWARE INFO
+ *
+ * The homepage of the Linux driver is at http://www.fi.muni.cz/~kas/cosa/.
+ * The CVS tree of Linux driver can be viewed there, as well as the
+ * firmware binaries and user-space utilities for downloading the firmware
+ * into the card and setting up the card.
+ *
+ * The Linux driver (unlike the present *BSD drivers :-) can work even
+ * for the COSA and SRP in one computer and allows each channel to work
+ * in one of the three modes (character device, Cisco HDLC, Sync PPP).
+ *
+ * AUTHOR
+ *
+ * The Linux driver was written by Jan "Yenya" Kasprzak .
+ *
+ * You can mail me bugfixes and even success reports. I am especially
+ * interested in the SMP and/or muliti-channel success/failure reports
+ * (I wonder if I did the locking properly :-).
+ *
+ * THE AUTHOR USED THE FOLLOWING SOURCES WHEN PROGRAMMING THE DRIVER
+ *
+ * The COSA/SRP NetBSD driver by Zdenek Salvet and Ivos Cernohlavek
+ * The skeleton.c by Donald Becker
+ * The SDL Riscom/N2 driver by Mike Natale
+ * The Comtrol Hostess SV11 driver by Alan Cox
+ * The Sync PPP/Cisco HDLC layer (syncppp.c) ported to Linux by Alan Cox
+ */
+/*
+ * 5/25/1999 : Marcelo Tosatti
+ * fixed a deadlock in cosa_sppp_open
+ */
+
+/* ---------- Headers, macros, data structures ---------- */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#undef COSA_SLOW_IO /* for testing purposes only */
+#undef REALLY_SLOW_IO
+
+#include
+#include
+#include
+
+#include
+#include "cosa.h"
+
+/* Maximum length of the identification string. */
+#define COSA_MAX_ID_STRING 128
+
+/* Maximum length of the channel name */
+#define COSA_MAX_NAME (sizeof("cosaXXXcXXX")+1)
+
+/* Per-channel data structure */
+
+struct channel_data {
+ void *if_ptr; /* General purpose pointer (used by SPPP) */
+ int usage; /* Usage count; >0 for chrdev, -1 for netdev */
+ int num; /* Number of the channel */
+ struct cosa_data *cosa; /* Pointer to the per-card structure */
+ int txsize; /* Size of transmitted data */
+ char *txbuf; /* Transmit buffer */
+ char name[COSA_MAX_NAME]; /* channel name */
+
+ /* The HW layer interface */
+ /* routine called from the RX interrupt */
+ char *(*setup_rx)(struct channel_data *channel, int size);
+ /* routine called when the RX is done (from the EOT interrupt) */
+ int (*rx_done)(struct channel_data *channel);
+ /* routine called when the TX is done (from the EOT interrupt) */
+ int (*tx_done)(struct channel_data *channel, int size);
+
+ /* Character device parts */
+ struct semaphore rsem, wsem;
+ char *rxdata;
+ int rxsize;
+ wait_queue_head_t txwaitq, rxwaitq;
+ int tx_status, rx_status;
+
+ /* SPPP/HDLC device parts */
+ struct ppp_device pppdev;
+ struct sk_buff *rx_skb, *tx_skb;
+ struct net_device_stats stats;
+};
+
+/* cosa->firmware_status bits */
+#define COSA_FW_RESET (1<<0) /* Is the ROM monitor active? */
+#define COSA_FW_DOWNLOAD (1<<1) /* Is the microcode downloaded? */
+#define COSA_FW_START (1<<2) /* Is the microcode running? */
+
+struct cosa_data {
+ int num; /* Card number */
+ char name[COSA_MAX_NAME]; /* Card name - e.g "cosa0" */
+ unsigned int datareg, statusreg; /* I/O ports */
+ unsigned short irq, dma; /* IRQ and DMA number */
+ unsigned short startaddr; /* Firmware start address */
+ unsigned short busmaster; /* Use busmastering? */
+ int nchannels; /* # of channels on this card */
+ int driver_status; /* For communicating with firmware */
+ int firmware_status; /* Downloaded, reseted, etc. */
+ long int rxbitmap, txbitmap; /* Bitmap of channels who are willing to send/receive data */
+ long int rxtx; /* RX or TX in progress? */
+ int enabled;
+ int usage; /* usage count */
+ int txchan, txsize, rxsize;
+ struct channel_data *rxchan;
+ char *bouncebuf;
+ char *txbuf, *rxbuf;
+ struct channel_data *chan;
+ spinlock_t lock; /* For exclusive operations on this structure */
+ char id_string[COSA_MAX_ID_STRING]; /* ROM monitor ID string */
+ char *type; /* card type */
+};
+
+/*
+ * Define this if you want all the possible ports to be autoprobed.
+ * It is here but it probably is not a good idea to use this.
+ */
+/* #define COSA_ISA_AUTOPROBE 1 */
+
+/*
+ * Character device major number. 117 was allocated for us.
+ * The value of 0 means to allocate a first free one.
+ */
+static int cosa_major = 117;
+
+/*
+ * Encoding of the minor numbers:
+ * The lowest CARD_MINOR_BITS bits means the channel on the single card,
+ * the highest bits means the card number.
+ */
+#define CARD_MINOR_BITS 4 /* How many bits in minor number are reserved
+ * for the single card */
+/*
+ * The following depends on CARD_MINOR_BITS. Unfortunately, the "MODULE_STRING"
+ * macro doesn't like anything other than the raw number as an argument :-(
+ */
+#define MAX_CARDS 16
+/* #define MAX_CARDS (1 << (8-CARD_MINOR_BITS)) */
+
+#define DRIVER_RX_READY 0x0001
+#define DRIVER_TX_READY 0x0002
+#define DRIVER_TXMAP_SHIFT 2
+#define DRIVER_TXMAP_MASK 0x0c /* FIXME: 0xfc for 8-channel version */
+
+/*
+ * for cosa->rxtx - indicates whether either transmit or receive is
+ * in progress. These values are mean number of the bit.
+ */
+#define TXBIT 0
+#define RXBIT 1
+#define IRQBIT 2
+
+#define COSA_MTU 2000 /* FIXME: I don't know this exactly */
+
+#undef DEBUG_DATA //1 /* Dump the data read or written to the channel */
+#undef DEBUG_IRQS //1 /* Print the message when the IRQ is received */
+#undef DEBUG_IO //1 /* Dump the I/O traffic */
+
+#define TX_TIMEOUT (5*HZ)
+
+/* Maybe the following should be allocated dynamically */
+static struct cosa_data cosa_cards[MAX_CARDS];
+static int nr_cards;
+
+#ifdef COSA_ISA_AUTOPROBE
+static int io[MAX_CARDS+1] = { 0x220, 0x228, 0x210, 0x218, 0, };
+/* NOTE: DMA is not autoprobed!!! */
+static int dma[MAX_CARDS+1] = { 1, 7, 1, 7, 1, 7, 1, 7, 0, };
+#else
+static int io[MAX_CARDS+1];
+static int dma[MAX_CARDS+1];
+#endif
+/* IRQ can be safely autoprobed */
+static int irq[MAX_CARDS+1] = { -1, -1, -1, -1, -1, -1, 0, };
+
+/* for class stuff*/
+static struct class_simple *cosa_class;
+
+#ifdef MODULE
+module_param_array(io, int, NULL, 0);
+MODULE_PARM_DESC(io, "The I/O bases of the COSA or SRP cards");
+module_param_array(irq, int, NULL, 0);
+MODULE_PARM_DESC(irq, "The IRQ lines of the COSA or SRP cards");
+module_param_array(dma, int, NULL, 0);
+MODULE_PARM_DESC(dma, "The DMA channels of the COSA or SRP cards");
+
+MODULE_AUTHOR("Jan \"Yenya\" Kasprzak, ");
+MODULE_DESCRIPTION("Modular driver for the COSA or SRP synchronous card");
+MODULE_LICENSE("GPL");
+#endif
+
+/* I use this mainly for testing purposes */
+#ifdef COSA_SLOW_IO
+#define cosa_outb outb_p
+#define cosa_outw outw_p
+#define cosa_inb inb_p
+#define cosa_inw inw_p
+#else
+#define cosa_outb outb
+#define cosa_outw outw
+#define cosa_inb inb
+#define cosa_inw inw
+#endif
+
+#define is_8bit(cosa) (!(cosa->datareg & 0x08))
+
+#define cosa_getstatus(cosa) (cosa_inb(cosa->statusreg))
+#define cosa_putstatus(cosa, stat) (cosa_outb(stat, cosa->statusreg))
+#define cosa_getdata16(cosa) (cosa_inw(cosa->datareg))
+#define cosa_getdata8(cosa) (cosa_inb(cosa->datareg))
+#define cosa_putdata16(cosa, dt) (cosa_outw(dt, cosa->datareg))
+#define cosa_putdata8(cosa, dt) (cosa_outb(dt, cosa->datareg))
+
+/* Initialization stuff */
+static int cosa_probe(int ioaddr, int irq, int dma);
+
+/* HW interface */
+static void cosa_enable_rx(struct channel_data *chan);
+static void cosa_disable_rx(struct channel_data *chan);
+static int cosa_start_tx(struct channel_data *channel, char *buf, int size);
+static void cosa_kick(struct cosa_data *cosa);
+static int cosa_dma_able(struct channel_data *chan, char *buf, int data);
+
+/* SPPP/HDLC stuff */
+static void sppp_channel_init(struct channel_data *chan);
+static void sppp_channel_delete(struct channel_data *chan);
+static int cosa_sppp_open(struct net_device *d);
+static int cosa_sppp_close(struct net_device *d);
+static void cosa_sppp_timeout(struct net_device *d);
+static int cosa_sppp_tx(struct sk_buff *skb, struct net_device *d);
+static char *sppp_setup_rx(struct channel_data *channel, int size);
+static int sppp_rx_done(struct channel_data *channel);
+static int sppp_tx_done(struct channel_data *channel, int size);
+static int cosa_sppp_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
+static struct net_device_stats *cosa_net_stats(struct net_device *dev);
+
+/* Character device */
+static void chardev_channel_init(struct channel_data *chan);
+static char *chrdev_setup_rx(struct channel_data *channel, int size);
+static int chrdev_rx_done(struct channel_data *channel);
+static int chrdev_tx_done(struct channel_data *channel, int size);
+static ssize_t cosa_read(struct file *file,
+ char __user *buf, size_t count, loff_t *ppos);
+static ssize_t cosa_write(struct file *file,
+ const char __user *buf, size_t count, loff_t *ppos);
+static unsigned int cosa_poll(struct file *file, poll_table *poll);
+static int cosa_open(struct inode *inode, struct file *file);
+static int cosa_release(struct inode *inode, struct file *file);
+static int cosa_chardev_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg);
+#ifdef COSA_FASYNC_WORKING
+static int cosa_fasync(struct inode *inode, struct file *file, int on);
+#endif
+
+static struct file_operations cosa_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .read = cosa_read,
+ .write = cosa_write,
+ .poll = cosa_poll,
+ .ioctl = cosa_chardev_ioctl,
+ .open = cosa_open,
+ .release = cosa_release,
+#ifdef COSA_FASYNC_WORKING
+ .fasync = cosa_fasync,
+#endif
+};
+
+/* Ioctls */
+static int cosa_start(struct cosa_data *cosa, int address);
+static int cosa_reset(struct cosa_data *cosa);
+static int cosa_download(struct cosa_data *cosa, void __user *a);
+static int cosa_readmem(struct cosa_data *cosa, void __user *a);
+
+/* COSA/SRP ROM monitor */
+static int download(struct cosa_data *cosa, const char __user *data, int addr, int len);
+static int startmicrocode(struct cosa_data *cosa, int address);
+static int readmem(struct cosa_data *cosa, char __user *data, int addr, int len);
+static int cosa_reset_and_read_id(struct cosa_data *cosa, char *id);
+
+/* Auxilliary functions */
+static int get_wait_data(struct cosa_data *cosa);
+static int put_wait_data(struct cosa_data *cosa, int data);
+static int puthexnumber(struct cosa_data *cosa, int number);
+static void put_driver_status(struct cosa_data *cosa);
+static void put_driver_status_nolock(struct cosa_data *cosa);
+
+/* Interrupt handling */
+static irqreturn_t cosa_interrupt(int irq, void *cosa, struct pt_regs *regs);
+
+/* I/O ops debugging */
+#ifdef DEBUG_IO
+static void debug_data_in(struct cosa_data *cosa, int data);
+static void debug_data_out(struct cosa_data *cosa, int data);
+static void debug_data_cmd(struct cosa_data *cosa, int data);
+static void debug_status_in(struct cosa_data *cosa, int status);
+static void debug_status_out(struct cosa_data *cosa, int status);
+#endif
+
+
+/* ---------- Initialization stuff ---------- */
+
+static int __init cosa_init(void)
+{
+ int i, err = 0;
+
+ printk(KERN_INFO "cosa v1.08 (c) 1997-2000 Jan Kasprzak \n");
+#ifdef CONFIG_SMP
+ printk(KERN_INFO "cosa: SMP found. Please mail any success/failure reports to the author.\n");
+#endif
+ if (cosa_major > 0) {
+ if (register_chrdev(cosa_major, "cosa", &cosa_fops)) {
+ printk(KERN_WARNING "cosa: unable to get major %d\n",
+ cosa_major);
+ err = -EIO;
+ goto out;
+ }
+ } else {
+ if (!(cosa_major=register_chrdev(0, "cosa", &cosa_fops))) {
+ printk(KERN_WARNING "cosa: unable to register chardev\n");
+ err = -EIO;
+ goto out;
+ }
+ }
+ for (i=0; inchannels; i++) {
+ /* Chardev driver has no alloc'd per-channel data */
+ sppp_channel_delete(cosa->chan+i);
+ }
+ /* Clean up the per-card data */
+ kfree(cosa->chan);
+ kfree(cosa->bouncebuf);
+ free_irq(cosa->irq, cosa);
+ free_dma(cosa->dma);
+ release_region(cosa->datareg,is_8bit(cosa)?2:4);
+ }
+ unregister_chrdev(cosa_major, "cosa");
+}
+module_exit(cosa_exit);
+
+/*
+ * This function should register all the net devices needed for the
+ * single channel.
+ */
+static __inline__ void channel_init(struct channel_data *chan)
+{
+ sprintf(chan->name, "cosa%dc%d", chan->cosa->num, chan->num);
+
+ /* Initialize the chardev data structures */
+ chardev_channel_init(chan);
+
+ /* Register the sppp interface */
+ sppp_channel_init(chan);
+}
+
+static int cosa_probe(int base, int irq, int dma)
+{
+ struct cosa_data *cosa = cosa_cards+nr_cards;
+ int i, err = 0;
+
+ memset(cosa, 0, sizeof(struct cosa_data));
+
+ /* Checking validity of parameters: */
+ /* IRQ should be 2-7 or 10-15; negative IRQ means autoprobe */
+ if ((irq >= 0 && irq < 2) || irq > 15 || (irq < 10 && irq > 7)) {
+ printk (KERN_INFO "cosa_probe: invalid IRQ %d\n", irq);
+ return -1;
+ }
+ /* I/O address should be between 0x100 and 0x3ff and should be
+ * multiple of 8. */
+ if (base < 0x100 || base > 0x3ff || base & 0x7) {
+ printk (KERN_INFO "cosa_probe: invalid I/O address 0x%x\n",
+ base);
+ return -1;
+ }
+ /* DMA should be 0,1 or 3-7 */
+ if (dma < 0 || dma == 4 || dma > 7) {
+ printk (KERN_INFO "cosa_probe: invalid DMA %d\n", dma);
+ return -1;
+ }
+ /* and finally, on 16-bit COSA DMA should be 4-7 and
+ * I/O base should not be multiple of 0x10 */
+ if (((base & 0x8) && dma < 4) || (!(base & 0x8) && dma > 3)) {
+ printk (KERN_INFO "cosa_probe: 8/16 bit base and DMA mismatch"
+ " (base=0x%x, dma=%d)\n", base, dma);
+ return -1;
+ }
+
+ cosa->dma = dma;
+ cosa->datareg = base;
+ cosa->statusreg = is_8bit(cosa)?base+1:base+2;
+ spin_lock_init(&cosa->lock);
+
+ if (!request_region(base, is_8bit(cosa)?2:4,"cosa"))
+ return -1;
+
+ if (cosa_reset_and_read_id(cosa, cosa->id_string) < 0) {
+ printk(KERN_DEBUG "cosa: probe at 0x%x failed.\n", base);
+ err = -1;
+ goto err_out;
+ }
+
+ /* Test the validity of identification string */
+ if (!strncmp(cosa->id_string, "SRP", 3))
+ cosa->type = "srp";
+ else if (!strncmp(cosa->id_string, "COSA", 4))
+ cosa->type = is_8bit(cosa)? "cosa8": "cosa16";
+ else {
+/* Print a warning only if we are not autoprobing */
+#ifndef COSA_ISA_AUTOPROBE
+ printk(KERN_INFO "cosa: valid signature not found at 0x%x.\n",
+ base);
+#endif
+ err = -1;
+ goto err_out;
+ }
+ /* Update the name of the region now we know the type of card */
+ release_region(base, is_8bit(cosa)?2:4);
+ if (!request_region(base, is_8bit(cosa)?2:4, cosa->type)) {
+ printk(KERN_DEBUG "cosa: changing name at 0x%x failed.\n", base);
+ return -1;
+ }
+
+ /* Now do IRQ autoprobe */
+ if (irq < 0) {
+ unsigned long irqs;
+/* printk(KERN_INFO "IRQ autoprobe\n"); */
+ irqs = probe_irq_on();
+ /*
+ * Enable interrupt on tx buffer empty (it sure is)
+ * really sure ?
+ * FIXME: When this code is not used as module, we should
+ * probably call udelay() instead of the interruptible sleep.
+ */
+ set_current_state(TASK_INTERRUPTIBLE);
+ cosa_putstatus(cosa, SR_TX_INT_ENA);
+ schedule_timeout(30);
+ irq = probe_irq_off(irqs);
+ /* Disable all IRQs from the card */
+ cosa_putstatus(cosa, 0);
+ /* Empty the received data register */
+ cosa_getdata8(cosa);
+
+ if (irq < 0) {
+ printk (KERN_INFO "cosa IRQ autoprobe: multiple interrupts obtained (%d, board at 0x%x)\n",
+ irq, cosa->datareg);
+ err = -1;
+ goto err_out;
+ }
+ if (irq == 0) {
+ printk (KERN_INFO "cosa IRQ autoprobe: no interrupt obtained (board at 0x%x)\n",
+ cosa->datareg);
+ /* return -1; */
+ }
+ }
+
+ cosa->irq = irq;
+ cosa->num = nr_cards;
+ cosa->usage = 0;
+ cosa->nchannels = 2; /* FIXME: how to determine this? */
+
+ if (request_irq(cosa->irq, cosa_interrupt, 0, cosa->type, cosa)) {
+ err = -1;
+ goto err_out;
+ }
+ if (request_dma(cosa->dma, cosa->type)) {
+ err = -1;
+ goto err_out1;
+ }
+
+ cosa->bouncebuf = kmalloc(COSA_MTU, GFP_KERNEL|GFP_DMA);
+ if (!cosa->bouncebuf) {
+ err = -ENOMEM;
+ goto err_out2;
+ }
+ sprintf(cosa->name, "cosa%d", cosa->num);
+
+ /* Initialize the per-channel data */
+ cosa->chan = kmalloc(sizeof(struct channel_data)*cosa->nchannels,
+ GFP_KERNEL);
+ if (!cosa->chan) {
+ err = -ENOMEM;
+ goto err_out3;
+ }
+ memset(cosa->chan, 0, sizeof(struct channel_data)*cosa->nchannels);
+ for (i=0; inchannels; i++) {
+ cosa->chan[i].cosa = cosa;
+ cosa->chan[i].num = i;
+ channel_init(cosa->chan+i);
+ }
+
+ printk (KERN_INFO "cosa%d: %s (%s at 0x%x irq %d dma %d), %d channels\n",
+ cosa->num, cosa->id_string, cosa->type,
+ cosa->datareg, cosa->irq, cosa->dma, cosa->nchannels);
+
+ return nr_cards++;
+err_out3:
+ kfree(cosa->bouncebuf);
+err_out2:
+ free_dma(cosa->dma);
+err_out1:
+ free_irq(cosa->irq, cosa);
+err_out:
+ release_region(cosa->datareg,is_8bit(cosa)?2:4);
+ printk(KERN_NOTICE "cosa%d: allocating resources failed\n",
+ cosa->num);
+ return err;
+}
+
+
+/*---------- SPPP/HDLC netdevice ---------- */
+
+static void cosa_setup(struct net_device *d)
+{
+ d->open = cosa_sppp_open;
+ d->stop = cosa_sppp_close;
+ d->hard_start_xmit = cosa_sppp_tx;
+ d->do_ioctl = cosa_sppp_ioctl;
+ d->get_stats = cosa_net_stats;
+ d->tx_timeout = cosa_sppp_timeout;
+ d->watchdog_timeo = TX_TIMEOUT;
+}
+
+static void sppp_channel_init(struct channel_data *chan)
+{
+ struct net_device *d;
+ chan->if_ptr = &chan->pppdev;
+ d = alloc_netdev(0, chan->name, cosa_setup);
+ if (!d) {
+ printk(KERN_WARNING "%s: alloc_netdev failed.\n", chan->name);
+ return;
+ }
+ chan->pppdev.dev = d;
+ d->base_addr = chan->cosa->datareg;
+ d->irq = chan->cosa->irq;
+ d->dma = chan->cosa->dma;
+ d->priv = chan;
+ sppp_attach(&chan->pppdev);
+ if (register_netdev(d)) {
+ printk(KERN_WARNING "%s: register_netdev failed.\n", d->name);
+ sppp_detach(d);
+ free_netdev(d);
+ chan->pppdev.dev = NULL;
+ return;
+ }
+}
+
+static void sppp_channel_delete(struct channel_data *chan)
+{
+ unregister_netdev(chan->pppdev.dev);
+ sppp_detach(chan->pppdev.dev);
+ free_netdev(chan->pppdev.dev);
+ chan->pppdev.dev = NULL;
+}
+
+static int cosa_sppp_open(struct net_device *d)
+{
+ struct channel_data *chan = d->priv;
+ int err;
+ unsigned long flags;
+
+ if (!(chan->cosa->firmware_status & COSA_FW_START)) {
+ printk(KERN_NOTICE "%s: start the firmware first (status %d)\n",
+ chan->cosa->name, chan->cosa->firmware_status);
+ return -EPERM;
+ }
+ spin_lock_irqsave(&chan->cosa->lock, flags);
+ if (chan->usage != 0) {
+ printk(KERN_WARNING "%s: sppp_open called with usage count %d\n",
+ chan->name, chan->usage);
+ spin_unlock_irqrestore(&chan->cosa->lock, flags);
+ return -EBUSY;
+ }
+ chan->setup_rx = sppp_setup_rx;
+ chan->tx_done = sppp_tx_done;
+ chan->rx_done = sppp_rx_done;
+ chan->usage=-1;
+ chan->cosa->usage++;
+ spin_unlock_irqrestore(&chan->cosa->lock, flags);
+
+ err = sppp_open(d);
+ if (err) {
+ spin_lock_irqsave(&chan->cosa->lock, flags);
+ chan->usage=0;
+ chan->cosa->usage--;
+
+ spin_unlock_irqrestore(&chan->cosa->lock, flags);
+ return err;
+ }
+
+ netif_start_queue(d);
+ cosa_enable_rx(chan);
+ return 0;
+}
+
+static int cosa_sppp_tx(struct sk_buff *skb, struct net_device *dev)
+{
+ struct channel_data *chan = dev->priv;
+
+ netif_stop_queue(dev);
+
+ chan->tx_skb = skb;
+ cosa_start_tx(chan, skb->data, skb->len);
+ return 0;
+}
+
+static void cosa_sppp_timeout(struct net_device *dev)
+{
+ struct channel_data *chan = dev->priv;
+
+ if (test_bit(RXBIT, &chan->cosa->rxtx)) {
+ chan->stats.rx_errors++;
+ chan->stats.rx_missed_errors++;
+ } else {
+ chan->stats.tx_errors++;
+ chan->stats.tx_aborted_errors++;
+ }
+ cosa_kick(chan->cosa);
+ if (chan->tx_skb) {
+ dev_kfree_skb(chan->tx_skb);
+ chan->tx_skb = NULL;
+ }
+ netif_wake_queue(dev);
+}
+
+static int cosa_sppp_close(struct net_device *d)
+{
+ struct channel_data *chan = d->priv;
+ unsigned long flags;
+
+ netif_stop_queue(d);
+ sppp_close(d);
+ cosa_disable_rx(chan);
+ spin_lock_irqsave(&chan->cosa->lock, flags);
+ if (chan->rx_skb) {
+ kfree_skb(chan->rx_skb);
+ chan->rx_skb = NULL;
+ }
+ if (chan->tx_skb) {
+ kfree_skb(chan->tx_skb);
+ chan->tx_skb = NULL;
+ }
+ chan->usage=0;
+ chan->cosa->usage--;
+ spin_unlock_irqrestore(&chan->cosa->lock, flags);
+ return 0;
+}
+
+static char *sppp_setup_rx(struct channel_data *chan, int size)
+{
+ /*
+ * We can safely fall back to non-dma-able memory, because we have
+ * the cosa->bouncebuf pre-allocated.
+ */
+ if (chan->rx_skb)
+ kfree_skb(chan->rx_skb);
+ chan->rx_skb = dev_alloc_skb(size);
+ if (chan->rx_skb == NULL) {
+ printk(KERN_NOTICE "%s: Memory squeeze, dropping packet\n",
+ chan->name);
+ chan->stats.rx_dropped++;
+ return NULL;
+ }
+ chan->pppdev.dev->trans_start = jiffies;
+ return skb_put(chan->rx_skb, size);
+}
+
+static int sppp_rx_done(struct channel_data *chan)
+{
+ if (!chan->rx_skb) {
+ printk(KERN_WARNING "%s: rx_done with empty skb!\n",
+ chan->name);
+ chan->stats.rx_errors++;
+ chan->stats.rx_frame_errors++;
+ return 0;
+ }
+ chan->rx_skb->protocol = htons(ETH_P_WAN_PPP);
+ chan->rx_skb->dev = chan->pppdev.dev;
+ chan->rx_skb->mac.raw = chan->rx_skb->data;
+ chan->stats.rx_packets++;
+ chan->stats.rx_bytes += chan->cosa->rxsize;
+ netif_rx(chan->rx_skb);
+ chan->rx_skb = NULL;
+ chan->pppdev.dev->last_rx = jiffies;
+ return 0;
+}
+
+/* ARGSUSED */
+static int sppp_tx_done(struct channel_data *chan, int size)
+{
+ if (!chan->tx_skb) {
+ printk(KERN_WARNING "%s: tx_done with empty skb!\n",
+ chan->name);
+ chan->stats.tx_errors++;
+ chan->stats.tx_aborted_errors++;
+ return 1;
+ }
+ dev_kfree_skb_irq(chan->tx_skb);
+ chan->tx_skb = NULL;
+ chan->stats.tx_packets++;
+ chan->stats.tx_bytes += size;
+ netif_wake_queue(chan->pppdev.dev);
+ return 1;
+}
+
+static struct net_device_stats *cosa_net_stats(struct net_device *dev)
+{
+ struct channel_data *chan = dev->priv;
+ return &chan->stats;
+}
+
+
+/*---------- Character device ---------- */
+
+static void chardev_channel_init(struct channel_data *chan)
+{
+ init_MUTEX(&chan->rsem);
+ init_MUTEX(&chan->wsem);
+}
+
+static ssize_t cosa_read(struct file *file,
+ char __user *buf, size_t count, loff_t *ppos)
+{
+ DECLARE_WAITQUEUE(wait, current);
+ unsigned long flags;
+ struct channel_data *chan = file->private_data;
+ struct cosa_data *cosa = chan->cosa;
+ char *kbuf;
+
+ if (!(cosa->firmware_status & COSA_FW_START)) {
+ printk(KERN_NOTICE "%s: start the firmware first (status %d)\n",
+ cosa->name, cosa->firmware_status);
+ return -EPERM;
+ }
+ if (down_interruptible(&chan->rsem))
+ return -ERESTARTSYS;
+
+ if ((chan->rxdata = kmalloc(COSA_MTU, GFP_DMA|GFP_KERNEL)) == NULL) {
+ printk(KERN_INFO "%s: cosa_read() - OOM\n", cosa->name);
+ up(&chan->rsem);
+ return -ENOMEM;
+ }
+
+ chan->rx_status = 0;
+ cosa_enable_rx(chan);
+ spin_lock_irqsave(&cosa->lock, flags);
+ add_wait_queue(&chan->rxwaitq, &wait);
+ while(!chan->rx_status) {
+ current->state = TASK_INTERRUPTIBLE;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ schedule();
+ spin_lock_irqsave(&cosa->lock, flags);
+ if (signal_pending(current) && chan->rx_status == 0) {
+ chan->rx_status = 1;
+ remove_wait_queue(&chan->rxwaitq, &wait);
+ current->state = TASK_RUNNING;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ up(&chan->rsem);
+ return -ERESTARTSYS;
+ }
+ }
+ remove_wait_queue(&chan->rxwaitq, &wait);
+ current->state = TASK_RUNNING;
+ kbuf = chan->rxdata;
+ count = chan->rxsize;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ up(&chan->rsem);
+
+ if (copy_to_user(buf, kbuf, count)) {
+ kfree(kbuf);
+ return -EFAULT;
+ }
+ kfree(kbuf);
+ return count;
+}
+
+static char *chrdev_setup_rx(struct channel_data *chan, int size)
+{
+ /* Expect size <= COSA_MTU */
+ chan->rxsize = size;
+ return chan->rxdata;
+}
+
+static int chrdev_rx_done(struct channel_data *chan)
+{
+ if (chan->rx_status) { /* Reader has died */
+ kfree(chan->rxdata);
+ up(&chan->wsem);
+ }
+ chan->rx_status = 1;
+ wake_up_interruptible(&chan->rxwaitq);
+ return 1;
+}
+
+
+static ssize_t cosa_write(struct file *file,
+ const char __user *buf, size_t count, loff_t *ppos)
+{
+ DECLARE_WAITQUEUE(wait, current);
+ struct channel_data *chan = file->private_data;
+ struct cosa_data *cosa = chan->cosa;
+ unsigned long flags;
+ char *kbuf;
+
+ if (!(cosa->firmware_status & COSA_FW_START)) {
+ printk(KERN_NOTICE "%s: start the firmware first (status %d)\n",
+ cosa->name, cosa->firmware_status);
+ return -EPERM;
+ }
+ if (down_interruptible(&chan->wsem))
+ return -ERESTARTSYS;
+
+ if (count > COSA_MTU)
+ count = COSA_MTU;
+
+ /* Allocate the buffer */
+ if ((kbuf = kmalloc(count, GFP_KERNEL|GFP_DMA)) == NULL) {
+ printk(KERN_NOTICE "%s: cosa_write() OOM - dropping packet\n",
+ cosa->name);
+ up(&chan->wsem);
+ return -ENOMEM;
+ }
+ if (copy_from_user(kbuf, buf, count)) {
+ up(&chan->wsem);
+ kfree(kbuf);
+ return -EFAULT;
+ }
+ chan->tx_status=0;
+ cosa_start_tx(chan, kbuf, count);
+
+ spin_lock_irqsave(&cosa->lock, flags);
+ add_wait_queue(&chan->txwaitq, &wait);
+ while(!chan->tx_status) {
+ current->state = TASK_INTERRUPTIBLE;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ schedule();
+ spin_lock_irqsave(&cosa->lock, flags);
+ if (signal_pending(current) && chan->tx_status == 0) {
+ chan->tx_status = 1;
+ remove_wait_queue(&chan->txwaitq, &wait);
+ current->state = TASK_RUNNING;
+ chan->tx_status = 1;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ return -ERESTARTSYS;
+ }
+ }
+ remove_wait_queue(&chan->txwaitq, &wait);
+ current->state = TASK_RUNNING;
+ up(&chan->wsem);
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ kfree(kbuf);
+ return count;
+}
+
+static int chrdev_tx_done(struct channel_data *chan, int size)
+{
+ if (chan->tx_status) { /* Writer was interrupted */
+ kfree(chan->txbuf);
+ up(&chan->wsem);
+ }
+ chan->tx_status = 1;
+ wake_up_interruptible(&chan->txwaitq);
+ return 1;
+}
+
+static unsigned int cosa_poll(struct file *file, poll_table *poll)
+{
+ printk(KERN_INFO "cosa_poll is here\n");
+ return 0;
+}
+
+static int cosa_open(struct inode *inode, struct file *file)
+{
+ struct cosa_data *cosa;
+ struct channel_data *chan;
+ unsigned long flags;
+ int n;
+
+ if ((n=iminor(file->f_dentry->d_inode)>>CARD_MINOR_BITS)
+ >= nr_cards)
+ return -ENODEV;
+ cosa = cosa_cards+n;
+
+ if ((n=iminor(file->f_dentry->d_inode)
+ & ((1<= cosa->nchannels)
+ return -ENODEV;
+ chan = cosa->chan + n;
+
+ file->private_data = chan;
+
+ spin_lock_irqsave(&cosa->lock, flags);
+
+ if (chan->usage < 0) { /* in netdev mode */
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ return -EBUSY;
+ }
+ cosa->usage++;
+ chan->usage++;
+
+ chan->tx_done = chrdev_tx_done;
+ chan->setup_rx = chrdev_setup_rx;
+ chan->rx_done = chrdev_rx_done;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ return 0;
+}
+
+static int cosa_release(struct inode *inode, struct file *file)
+{
+ struct channel_data *channel = file->private_data;
+ struct cosa_data *cosa;
+ unsigned long flags;
+
+ cosa = channel->cosa;
+ spin_lock_irqsave(&cosa->lock, flags);
+ cosa->usage--;
+ channel->usage--;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ return 0;
+}
+
+#ifdef COSA_FASYNC_WORKING
+static struct fasync_struct *fasync[256] = { NULL, };
+
+/* To be done ... */
+static int cosa_fasync(struct inode *inode, struct file *file, int on)
+{
+ int port = iminor(inode);
+ int rv = fasync_helper(inode, file, on, &fasync[port]);
+ return rv < 0 ? rv : 0;
+}
+#endif
+
+
+/* ---------- Ioctls ---------- */
+
+/*
+ * Ioctl subroutines can safely be made inline, because they are called
+ * only from cosa_ioctl().
+ */
+static inline int cosa_reset(struct cosa_data *cosa)
+{
+ char idstring[COSA_MAX_ID_STRING];
+ if (cosa->usage > 1)
+ printk(KERN_INFO "cosa%d: WARNING: reset requested with cosa->usage > 1 (%d). Odd things may happen.\n",
+ cosa->num, cosa->usage);
+ cosa->firmware_status &= ~(COSA_FW_RESET|COSA_FW_START);
+ if (cosa_reset_and_read_id(cosa, idstring) < 0) {
+ printk(KERN_NOTICE "cosa%d: reset failed\n", cosa->num);
+ return -EIO;
+ }
+ printk(KERN_INFO "cosa%d: resetting device: %s\n", cosa->num,
+ idstring);
+ cosa->firmware_status |= COSA_FW_RESET;
+ return 0;
+}
+
+/* High-level function to download data into COSA memory. Calls download() */
+static inline int cosa_download(struct cosa_data *cosa, void __user *arg)
+{
+ struct cosa_download d;
+ int i;
+
+ if (cosa->usage > 1)
+ printk(KERN_INFO "%s: WARNING: download of microcode requested with cosa->usage > 1 (%d). Odd things may happen.\n",
+ cosa->name, cosa->usage);
+ if (!(cosa->firmware_status & COSA_FW_RESET)) {
+ printk(KERN_NOTICE "%s: reset the card first (status %d).\n",
+ cosa->name, cosa->firmware_status);
+ return -EPERM;
+ }
+
+ if (copy_from_user(&d, arg, sizeof(d)))
+ return -EFAULT;
+
+ if (d.addr < 0 || d.addr > COSA_MAX_FIRMWARE_SIZE)
+ return -EINVAL;
+ if (d.len < 0 || d.len > COSA_MAX_FIRMWARE_SIZE)
+ return -EINVAL;
+
+
+ /* If something fails, force the user to reset the card */
+ cosa->firmware_status &= ~(COSA_FW_RESET|COSA_FW_DOWNLOAD);
+
+ i = download(cosa, d.code, d.len, d.addr);
+ if (i < 0) {
+ printk(KERN_NOTICE "cosa%d: microcode download failed: %d\n",
+ cosa->num, i);
+ return -EIO;
+ }
+ printk(KERN_INFO "cosa%d: downloading microcode - 0x%04x bytes at 0x%04x\n",
+ cosa->num, d.len, d.addr);
+ cosa->firmware_status |= COSA_FW_RESET|COSA_FW_DOWNLOAD;
+ return 0;
+}
+
+/* High-level function to read COSA memory. Calls readmem() */
+static inline int cosa_readmem(struct cosa_data *cosa, void __user *arg)
+{
+ struct cosa_download d;
+ int i;
+
+ if (cosa->usage > 1)
+ printk(KERN_INFO "cosa%d: WARNING: readmem requested with "
+ "cosa->usage > 1 (%d). Odd things may happen.\n",
+ cosa->num, cosa->usage);
+ if (!(cosa->firmware_status & COSA_FW_RESET)) {
+ printk(KERN_NOTICE "%s: reset the card first (status %d).\n",
+ cosa->name, cosa->firmware_status);
+ return -EPERM;
+ }
+
+ if (copy_from_user(&d, arg, sizeof(d)))
+ return -EFAULT;
+
+ /* If something fails, force the user to reset the card */
+ cosa->firmware_status &= ~COSA_FW_RESET;
+
+ i = readmem(cosa, d.code, d.len, d.addr);
+ if (i < 0) {
+ printk(KERN_NOTICE "cosa%d: reading memory failed: %d\n",
+ cosa->num, i);
+ return -EIO;
+ }
+ printk(KERN_INFO "cosa%d: reading card memory - 0x%04x bytes at 0x%04x\n",
+ cosa->num, d.len, d.addr);
+ cosa->firmware_status |= COSA_FW_RESET;
+ return 0;
+}
+
+/* High-level function to start microcode. Calls startmicrocode(). */
+static inline int cosa_start(struct cosa_data *cosa, int address)
+{
+ int i;
+
+ if (cosa->usage > 1)
+ printk(KERN_INFO "cosa%d: WARNING: start microcode requested with cosa->usage > 1 (%d). Odd things may happen.\n",
+ cosa->num, cosa->usage);
+
+ if ((cosa->firmware_status & (COSA_FW_RESET|COSA_FW_DOWNLOAD))
+ != (COSA_FW_RESET|COSA_FW_DOWNLOAD)) {
+ printk(KERN_NOTICE "%s: download the microcode and/or reset the card first (status %d).\n",
+ cosa->name, cosa->firmware_status);
+ return -EPERM;
+ }
+ cosa->firmware_status &= ~COSA_FW_RESET;
+ if ((i=startmicrocode(cosa, address)) < 0) {
+ printk(KERN_NOTICE "cosa%d: start microcode at 0x%04x failed: %d\n",
+ cosa->num, address, i);
+ return -EIO;
+ }
+ printk(KERN_INFO "cosa%d: starting microcode at 0x%04x\n",
+ cosa->num, address);
+ cosa->startaddr = address;
+ cosa->firmware_status |= COSA_FW_START;
+ return 0;
+}
+
+/* Buffer of size at least COSA_MAX_ID_STRING is expected */
+static inline int cosa_getidstr(struct cosa_data *cosa, char __user *string)
+{
+ int l = strlen(cosa->id_string)+1;
+ if (copy_to_user(string, cosa->id_string, l))
+ return -EFAULT;
+ return l;
+}
+
+/* Buffer of size at least COSA_MAX_ID_STRING is expected */
+static inline int cosa_gettype(struct cosa_data *cosa, char __user *string)
+{
+ int l = strlen(cosa->type)+1;
+ if (copy_to_user(string, cosa->type, l))
+ return -EFAULT;
+ return l;
+}
+
+static int cosa_ioctl_common(struct cosa_data *cosa,
+ struct channel_data *channel, unsigned int cmd, unsigned long arg)
+{
+ void __user *argp = (void __user *)arg;
+ switch(cmd) {
+ case COSAIORSET: /* Reset the device */
+ if (!capable(CAP_NET_ADMIN))
+ return -EACCES;
+ return cosa_reset(cosa);
+ case COSAIOSTRT: /* Start the firmware */
+ if (!capable(CAP_SYS_RAWIO))
+ return -EACCES;
+ return cosa_start(cosa, arg);
+ case COSAIODOWNLD: /* Download the firmware */
+ if (!capable(CAP_SYS_RAWIO))
+ return -EACCES;
+
+ return cosa_download(cosa, argp);
+ case COSAIORMEM:
+ if (!capable(CAP_SYS_RAWIO))
+ return -EACCES;
+ return cosa_readmem(cosa, argp);
+ case COSAIORTYPE:
+ return cosa_gettype(cosa, argp);
+ case COSAIORIDSTR:
+ return cosa_getidstr(cosa, argp);
+ case COSAIONRCARDS:
+ return nr_cards;
+ case COSAIONRCHANS:
+ return cosa->nchannels;
+ case COSAIOBMSET:
+ if (!capable(CAP_SYS_RAWIO))
+ return -EACCES;
+ if (is_8bit(cosa))
+ return -EINVAL;
+ if (arg != COSA_BM_OFF && arg != COSA_BM_ON)
+ return -EINVAL;
+ cosa->busmaster = arg;
+ return 0;
+ case COSAIOBMGET:
+ return cosa->busmaster;
+ }
+ return -ENOIOCTLCMD;
+}
+
+static int cosa_sppp_ioctl(struct net_device *dev, struct ifreq *ifr,
+ int cmd)
+{
+ int rv;
+ struct channel_data *chan = dev->priv;
+ rv = cosa_ioctl_common(chan->cosa, chan, cmd, (unsigned long)ifr->ifr_data);
+ if (rv == -ENOIOCTLCMD) {
+ return sppp_do_ioctl(dev, ifr, cmd);
+ }
+ return rv;
+}
+
+static int cosa_chardev_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ struct channel_data *channel = file->private_data;
+ struct cosa_data *cosa = channel->cosa;
+ return cosa_ioctl_common(cosa, channel, cmd, arg);
+}
+
+
+/*---------- HW layer interface ---------- */
+
+/*
+ * The higher layer can bind itself to the HW layer by setting the callbacks
+ * in the channel_data structure and by using these routines.
+ */
+static void cosa_enable_rx(struct channel_data *chan)
+{
+ struct cosa_data *cosa = chan->cosa;
+
+ if (!test_and_set_bit(chan->num, &cosa->rxbitmap))
+ put_driver_status(cosa);
+}
+
+static void cosa_disable_rx(struct channel_data *chan)
+{
+ struct cosa_data *cosa = chan->cosa;
+
+ if (test_and_clear_bit(chan->num, &cosa->rxbitmap))
+ put_driver_status(cosa);
+}
+
+/*
+ * FIXME: This routine probably should check for cosa_start_tx() called when
+ * the previous transmit is still unfinished. In this case the non-zero
+ * return value should indicate to the caller that the queuing(sp?) up
+ * the transmit has failed.
+ */
+static int cosa_start_tx(struct channel_data *chan, char *buf, int len)
+{
+ struct cosa_data *cosa = chan->cosa;
+ unsigned long flags;
+#ifdef DEBUG_DATA
+ int i;
+
+ printk(KERN_INFO "cosa%dc%d: starting tx(0x%x)", chan->cosa->num,
+ chan->num, len);
+ for (i=0; ilock, flags);
+ chan->txbuf = buf;
+ chan->txsize = len;
+ if (len > COSA_MTU)
+ chan->txsize = COSA_MTU;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+
+ /* Tell the firmware we are ready */
+ set_bit(chan->num, &cosa->txbitmap);
+ put_driver_status(cosa);
+
+ return 0;
+}
+
+static void put_driver_status(struct cosa_data *cosa)
+{
+ unsigned long flags;
+ int status;
+
+ spin_lock_irqsave(&cosa->lock, flags);
+
+ status = (cosa->rxbitmap ? DRIVER_RX_READY : 0)
+ | (cosa->txbitmap ? DRIVER_TX_READY : 0)
+ | (cosa->txbitmap? ~(cosa->txbitmap<rxtx) {
+ if (cosa->rxbitmap|cosa->txbitmap) {
+ if (!cosa->enabled) {
+ cosa_putstatus(cosa, SR_RX_INT_ENA);
+#ifdef DEBUG_IO
+ debug_status_out(cosa, SR_RX_INT_ENA);
+#endif
+ cosa->enabled = 1;
+ }
+ } else if (cosa->enabled) {
+ cosa->enabled = 0;
+ cosa_putstatus(cosa, 0);
+#ifdef DEBUG_IO
+ debug_status_out(cosa, 0);
+#endif
+ }
+ cosa_putdata8(cosa, status);
+#ifdef DEBUG_IO
+ debug_data_cmd(cosa, status);
+#endif
+ }
+ spin_unlock_irqrestore(&cosa->lock, flags);
+}
+
+static void put_driver_status_nolock(struct cosa_data *cosa)
+{
+ int status;
+
+ status = (cosa->rxbitmap ? DRIVER_RX_READY : 0)
+ | (cosa->txbitmap ? DRIVER_TX_READY : 0)
+ | (cosa->txbitmap? ~(cosa->txbitmap<rxbitmap|cosa->txbitmap) {
+ cosa_putstatus(cosa, SR_RX_INT_ENA);
+#ifdef DEBUG_IO
+ debug_status_out(cosa, SR_RX_INT_ENA);
+#endif
+ cosa->enabled = 1;
+ } else {
+ cosa_putstatus(cosa, 0);
+#ifdef DEBUG_IO
+ debug_status_out(cosa, 0);
+#endif
+ cosa->enabled = 0;
+ }
+ cosa_putdata8(cosa, status);
+#ifdef DEBUG_IO
+ debug_data_cmd(cosa, status);
+#endif
+}
+
+/*
+ * The "kickme" function: When the DMA times out, this is called to
+ * clean up the driver status.
+ * FIXME: Preliminary support, the interface is probably wrong.
+ */
+static void cosa_kick(struct cosa_data *cosa)
+{
+ unsigned long flags, flags1;
+ char *s = "(probably) IRQ";
+
+ if (test_bit(RXBIT, &cosa->rxtx))
+ s = "RX DMA";
+ if (test_bit(TXBIT, &cosa->rxtx))
+ s = "TX DMA";
+
+ printk(KERN_INFO "%s: %s timeout - restarting.\n", cosa->name, s);
+ spin_lock_irqsave(&cosa->lock, flags);
+ cosa->rxtx = 0;
+
+ flags1 = claim_dma_lock();
+ disable_dma(cosa->dma);
+ clear_dma_ff(cosa->dma);
+ release_dma_lock(flags1);
+
+ /* FIXME: Anything else? */
+ udelay(100);
+ cosa_putstatus(cosa, 0);
+ udelay(100);
+ (void) cosa_getdata8(cosa);
+ udelay(100);
+ cosa_putdata8(cosa, 0);
+ udelay(100);
+ put_driver_status_nolock(cosa);
+ spin_unlock_irqrestore(&cosa->lock, flags);
+}
+
+/*
+ * Check if the whole buffer is DMA-able. It means it is below the 16M of
+ * physical memory and doesn't span the 64k boundary. For now it seems
+ * SKB's never do this, but we'll check this anyway.
+ */
+static int cosa_dma_able(struct channel_data *chan, char *buf, int len)
+{
+ static int count;
+ unsigned long b = (unsigned long)buf;
+ if (b+len >= MAX_DMA_ADDRESS)
+ return 0;
+ if ((b^ (b+len)) & 0x10000) {
+ if (count++ < 5)
+ printk(KERN_INFO "%s: packet spanning a 64k boundary\n",
+ chan->name);
+ return 0;
+ }
+ return 1;
+}
+
+
+/* ---------- The SRP/COSA ROM monitor functions ---------- */
+
+/*
+ * Downloading SRP microcode: say "w" to SRP monitor, it answers by "w=",
+ * drivers need to say 4-digit hex number meaning start address of the microcode
+ * separated by a single space. Monitor replies by saying " =". Now driver
+ * has to write 4-digit hex number meaning the last byte address ended
+ * by a single space. Monitor has to reply with a space. Now the download
+ * begins. After the download monitor replies with "\r\n." (CR LF dot).
+ */
+static int download(struct cosa_data *cosa, const char __user *microcode, int length, int address)
+{
+ int i;
+
+ if (put_wait_data(cosa, 'w') == -1) return -1;
+ if ((i=get_wait_data(cosa)) != 'w') { printk("dnld: 0x%04x\n",i); return -2;}
+ if (get_wait_data(cosa) != '=') return -3;
+
+ if (puthexnumber(cosa, address) < 0) return -4;
+ if (put_wait_data(cosa, ' ') == -1) return -10;
+ if (get_wait_data(cosa) != ' ') return -11;
+ if (get_wait_data(cosa) != '=') return -12;
+
+ if (puthexnumber(cosa, address+length-1) < 0) return -13;
+ if (put_wait_data(cosa, ' ') == -1) return -18;
+ if (get_wait_data(cosa) != ' ') return -19;
+
+ while (length--) {
+ char c;
+#ifndef SRP_DOWNLOAD_AT_BOOT
+ if (get_user(c, microcode))
+ return -23; /* ??? */
+#else
+ c = *microcode;
+#endif
+ if (put_wait_data(cosa, c) == -1)
+ return -20;
+ microcode++;
+ }
+
+ if (get_wait_data(cosa) != '\r') return -21;
+ if (get_wait_data(cosa) != '\n') return -22;
+ if (get_wait_data(cosa) != '.') return -23;
+#if 0
+ printk(KERN_DEBUG "cosa%d: download completed.\n", cosa->num);
+#endif
+ return 0;
+}
+
+
+/*
+ * Starting microcode is done via the "g" command of the SRP monitor.
+ * The chat should be the following: "g" "g=" ""
+ * "".
+ */
+static int startmicrocode(struct cosa_data *cosa, int address)
+{
+ if (put_wait_data(cosa, 'g') == -1) return -1;
+ if (get_wait_data(cosa) != 'g') return -2;
+ if (get_wait_data(cosa) != '=') return -3;
+
+ if (puthexnumber(cosa, address) < 0) return -4;
+ if (put_wait_data(cosa, '\r') == -1) return -5;
+
+ if (get_wait_data(cosa) != '\r') return -6;
+ if (get_wait_data(cosa) != '\r') return -7;
+ if (get_wait_data(cosa) != '\n') return -8;
+ if (get_wait_data(cosa) != '\r') return -9;
+ if (get_wait_data(cosa) != '\n') return -10;
+#if 0
+ printk(KERN_DEBUG "cosa%d: microcode started\n", cosa->num);
+#endif
+ return 0;
+}
+
+/*
+ * Reading memory is done via the "r" command of the SRP monitor.
+ * The chat is the following "r" "r=" " " " =" " " " "
+ * Then driver can read the data and the conversation is finished
+ * by SRP monitor sending "." (dot at the end).
+ *
+ * This routine is not needed during the normal operation and serves
+ * for debugging purposes only.
+ */
+static int readmem(struct cosa_data *cosa, char __user *microcode, int length, int address)
+{
+ if (put_wait_data(cosa, 'r') == -1) return -1;
+ if ((get_wait_data(cosa)) != 'r') return -2;
+ if ((get_wait_data(cosa)) != '=') return -3;
+
+ if (puthexnumber(cosa, address) < 0) return -4;
+ if (put_wait_data(cosa, ' ') == -1) return -5;
+ if (get_wait_data(cosa) != ' ') return -6;
+ if (get_wait_data(cosa) != '=') return -7;
+
+ if (puthexnumber(cosa, address+length-1) < 0) return -8;
+ if (put_wait_data(cosa, ' ') == -1) return -9;
+ if (get_wait_data(cosa) != ' ') return -10;
+
+ while (length--) {
+ char c;
+ int i;
+ if ((i=get_wait_data(cosa)) == -1) {
+ printk (KERN_INFO "cosa: 0x%04x bytes remaining\n",
+ length);
+ return -11;
+ }
+ c=i;
+#if 1
+ if (put_user(c, microcode))
+ return -23; /* ??? */
+#else
+ *microcode = c;
+#endif
+ microcode++;
+ }
+
+ if (get_wait_data(cosa) != '\r') return -21;
+ if (get_wait_data(cosa) != '\n') return -22;
+ if (get_wait_data(cosa) != '.') return -23;
+#if 0
+ printk(KERN_DEBUG "cosa%d: readmem completed.\n", cosa->num);
+#endif
+ return 0;
+}
+
+/*
+ * This function resets the device and reads the initial prompt
+ * of the device's ROM monitor.
+ */
+static int cosa_reset_and_read_id(struct cosa_data *cosa, char *idstring)
+{
+ int i=0, id=0, prev=0, curr=0;
+
+ /* Reset the card ... */
+ cosa_putstatus(cosa, 0);
+ cosa_getdata8(cosa);
+ cosa_putstatus(cosa, SR_RST);
+#ifdef MODULE
+ msleep(500);
+#else
+ udelay(5*100000);
+#endif
+ /* Disable all IRQs from the card */
+ cosa_putstatus(cosa, 0);
+
+ /*
+ * Try to read the ID string. The card then prints out the
+ * identification string ended by the "\n\x2e".
+ *
+ * The following loop is indexed through i (instead of id)
+ * to avoid looping forever when for any reason
+ * the port returns '\r', '\n' or '\x2e' permanently.
+ */
+ for (i=0; istate = TASK_INTERRUPTIBLE;
+ schedule_timeout(1);
+#endif
+ }
+ printk(KERN_INFO "cosa%d: timeout in put_wait_data (status 0x%x)\n",
+ cosa->num, cosa_getstatus(cosa));
+ return -1;
+}
+
+/*
+ * The following routine puts the hexadecimal number into the SRP monitor
+ * and verifies the proper echo of the sent bytes. Returns 0 on success,
+ * negative number on failure (-1,-3,-5,-7) means that put_wait_data() failed,
+ * (-2,-4,-6,-8) means that reading echo failed.
+ */
+static int puthexnumber(struct cosa_data *cosa, int number)
+{
+ char temp[5];
+ int i;
+
+ /* Well, I should probably replace this by something faster. */
+ sprintf(temp, "%04X", number);
+ for (i=0; i<4; i++) {
+ if (put_wait_data(cosa, temp[i]) == -1) {
+ printk(KERN_NOTICE "cosa%d: puthexnumber failed to write byte %d\n",
+ cosa->num, i);
+ return -1-2*i;
+ }
+ if (get_wait_data(cosa) != temp[i]) {
+ printk(KERN_NOTICE "cosa%d: puthexhumber failed to read echo of byte %d\n",
+ cosa->num, i);
+ return -2-2*i;
+ }
+ }
+ return 0;
+}
+
+
+/* ---------- Interrupt routines ---------- */
+
+/*
+ * There are three types of interrupt:
+ * At the beginning of transmit - this handled is in tx_interrupt(),
+ * at the beginning of receive - it is in rx_interrupt() and
+ * at the end of transmit/receive - it is the eot_interrupt() function.
+ * These functions are multiplexed by cosa_interrupt() according to the
+ * COSA status byte. I have moved the rx/tx/eot interrupt handling into
+ * separate functions to make it more readable. These functions are inline,
+ * so there should be no overhead of function call.
+ *
+ * In the COSA bus-master mode, we need to tell the card the address of a
+ * buffer. Unfortunately, COSA may be too slow for us, so we must busy-wait.
+ * It's time to use the bottom half :-(
+ */
+
+/*
+ * Transmit interrupt routine - called when COSA is willing to obtain
+ * data from the OS. The most tricky part of the routine is selection
+ * of channel we (OS) want to send packet for. For SRP we should probably
+ * use the round-robin approach. The newer COSA firmwares have a simple
+ * flow-control - in the status word has bits 2 and 3 set to 1 means that the
+ * channel 0 or 1 doesn't want to receive data.
+ *
+ * It seems there is a bug in COSA firmware (need to trace it further):
+ * When the driver status says that the kernel has no more data for transmit
+ * (e.g. at the end of TX DMA) and then the kernel changes its mind
+ * (e.g. new packet is queued to hard_start_xmit()), the card issues
+ * the TX interrupt but does not mark the channel as ready-to-transmit.
+ * The fix seems to be to push the packet to COSA despite its request.
+ * We first try to obey the card's opinion, and then fall back to forced TX.
+ */
+static inline void tx_interrupt(struct cosa_data *cosa, int status)
+{
+ unsigned long flags, flags1;
+#ifdef DEBUG_IRQS
+ printk(KERN_INFO "cosa%d: SR_DOWN_REQUEST status=0x%04x\n",
+ cosa->num, status);
+#endif
+ spin_lock_irqsave(&cosa->lock, flags);
+ set_bit(TXBIT, &cosa->rxtx);
+ if (!test_bit(IRQBIT, &cosa->rxtx)) {
+ /* flow control, see the comment above */
+ int i=0;
+ if (!cosa->txbitmap) {
+ printk(KERN_WARNING "%s: No channel wants data "
+ "in TX IRQ. Expect DMA timeout.",
+ cosa->name);
+ put_driver_status_nolock(cosa);
+ clear_bit(TXBIT, &cosa->rxtx);
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ return;
+ }
+ while(1) {
+ cosa->txchan++;
+ i++;
+ if (cosa->txchan >= cosa->nchannels)
+ cosa->txchan = 0;
+ if (!(cosa->txbitmap & (1<txchan)))
+ continue;
+ if (~status & (1 << (cosa->txchan+DRIVER_TXMAP_SHIFT)))
+ break;
+ /* in second pass, accept first ready-to-TX channel */
+ if (i > cosa->nchannels) {
+ /* Can be safely ignored */
+#ifdef DEBUG_IRQS
+ printk(KERN_DEBUG "%s: Forcing TX "
+ "to not-ready channel %d\n",
+ cosa->name, cosa->txchan);
+#endif
+ break;
+ }
+ }
+
+ cosa->txsize = cosa->chan[cosa->txchan].txsize;
+ if (cosa_dma_able(cosa->chan+cosa->txchan,
+ cosa->chan[cosa->txchan].txbuf, cosa->txsize)) {
+ cosa->txbuf = cosa->chan[cosa->txchan].txbuf;
+ } else {
+ memcpy(cosa->bouncebuf, cosa->chan[cosa->txchan].txbuf,
+ cosa->txsize);
+ cosa->txbuf = cosa->bouncebuf;
+ }
+ }
+
+ if (is_8bit(cosa)) {
+ if (!test_bit(IRQBIT, &cosa->rxtx)) {
+ cosa_putstatus(cosa, SR_TX_INT_ENA);
+ cosa_putdata8(cosa, ((cosa->txchan << 5) & 0xe0)|
+ ((cosa->txsize >> 8) & 0x1f));
+#ifdef DEBUG_IO
+ debug_status_out(cosa, SR_TX_INT_ENA);
+ debug_data_out(cosa, ((cosa->txchan << 5) & 0xe0)|
+ ((cosa->txsize >> 8) & 0x1f));
+ debug_data_in(cosa, cosa_getdata8(cosa));
+#else
+ cosa_getdata8(cosa);
+#endif
+ set_bit(IRQBIT, &cosa->rxtx);
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ return;
+ } else {
+ clear_bit(IRQBIT, &cosa->rxtx);
+ cosa_putstatus(cosa, 0);
+ cosa_putdata8(cosa, cosa->txsize&0xff);
+#ifdef DEBUG_IO
+ debug_status_out(cosa, 0);
+ debug_data_out(cosa, cosa->txsize&0xff);
+#endif
+ }
+ } else {
+ cosa_putstatus(cosa, SR_TX_INT_ENA);
+ cosa_putdata16(cosa, ((cosa->txchan<<13) & 0xe000)
+ | (cosa->txsize & 0x1fff));
+#ifdef DEBUG_IO
+ debug_status_out(cosa, SR_TX_INT_ENA);
+ debug_data_out(cosa, ((cosa->txchan<<13) & 0xe000)
+ | (cosa->txsize & 0x1fff));
+ debug_data_in(cosa, cosa_getdata8(cosa));
+ debug_status_out(cosa, 0);
+#else
+ cosa_getdata8(cosa);
+#endif
+ cosa_putstatus(cosa, 0);
+ }
+
+ if (cosa->busmaster) {
+ unsigned long addr = virt_to_bus(cosa->txbuf);
+ int count=0;
+ printk(KERN_INFO "busmaster IRQ\n");
+ while (!(cosa_getstatus(cosa)&SR_TX_RDY)) {
+ count++;
+ udelay(10);
+ if (count > 1000) break;
+ }
+ printk(KERN_INFO "status %x\n", cosa_getstatus(cosa));
+ printk(KERN_INFO "ready after %d loops\n", count);
+ cosa_putdata16(cosa, (addr >> 16)&0xffff);
+
+ count = 0;
+ while (!(cosa_getstatus(cosa)&SR_TX_RDY)) {
+ count++;
+ if (count > 1000) break;
+ udelay(10);
+ }
+ printk(KERN_INFO "ready after %d loops\n", count);
+ cosa_putdata16(cosa, addr &0xffff);
+ flags1 = claim_dma_lock();
+ set_dma_mode(cosa->dma, DMA_MODE_CASCADE);
+ enable_dma(cosa->dma);
+ release_dma_lock(flags1);
+ } else {
+ /* start the DMA */
+ flags1 = claim_dma_lock();
+ disable_dma(cosa->dma);
+ clear_dma_ff(cosa->dma);
+ set_dma_mode(cosa->dma, DMA_MODE_WRITE);
+ set_dma_addr(cosa->dma, virt_to_bus(cosa->txbuf));
+ set_dma_count(cosa->dma, cosa->txsize);
+ enable_dma(cosa->dma);
+ release_dma_lock(flags1);
+ }
+ cosa_putstatus(cosa, SR_TX_DMA_ENA|SR_USR_INT_ENA);
+#ifdef DEBUG_IO
+ debug_status_out(cosa, SR_TX_DMA_ENA|SR_USR_INT_ENA);
+#endif
+ spin_unlock_irqrestore(&cosa->lock, flags);
+}
+
+static inline void rx_interrupt(struct cosa_data *cosa, int status)
+{
+ unsigned long flags;
+#ifdef DEBUG_IRQS
+ printk(KERN_INFO "cosa%d: SR_UP_REQUEST\n", cosa->num);
+#endif
+
+ spin_lock_irqsave(&cosa->lock, flags);
+ set_bit(RXBIT, &cosa->rxtx);
+
+ if (is_8bit(cosa)) {
+ if (!test_bit(IRQBIT, &cosa->rxtx)) {
+ set_bit(IRQBIT, &cosa->rxtx);
+ put_driver_status_nolock(cosa);
+ cosa->rxsize = cosa_getdata8(cosa) <<8;
+#ifdef DEBUG_IO
+ debug_data_in(cosa, cosa->rxsize >> 8);
+#endif
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ return;
+ } else {
+ clear_bit(IRQBIT, &cosa->rxtx);
+ cosa->rxsize |= cosa_getdata8(cosa) & 0xff;
+#ifdef DEBUG_IO
+ debug_data_in(cosa, cosa->rxsize & 0xff);
+#endif
+#if 0
+ printk(KERN_INFO "cosa%d: receive rxsize = (0x%04x).\n",
+ cosa->num, cosa->rxsize);
+#endif
+ }
+ } else {
+ cosa->rxsize = cosa_getdata16(cosa);
+#ifdef DEBUG_IO
+ debug_data_in(cosa, cosa->rxsize);
+#endif
+#if 0
+ printk(KERN_INFO "cosa%d: receive rxsize = (0x%04x).\n",
+ cosa->num, cosa->rxsize);
+#endif
+ }
+ if (((cosa->rxsize & 0xe000) >> 13) >= cosa->nchannels) {
+ printk(KERN_WARNING "%s: rx for unknown channel (0x%04x)\n",
+ cosa->name, cosa->rxsize);
+ spin_unlock_irqrestore(&cosa->lock, flags);
+ goto reject;
+ }
+ cosa->rxchan = cosa->chan + ((cosa->rxsize & 0xe000) >> 13);
+ cosa->rxsize &= 0x1fff;
+ spin_unlock_irqrestore(&cosa->lock, flags);
+
+ cosa->rxbuf = NULL;
+ if (cosa->rxchan->setup_rx)
+ cosa->rxbuf = cosa->rxchan->setup_rx(cosa->rxchan, cosa->rxsize);
+
+ if (!cosa->rxbuf) {
+reject: /* Reject the packet */
+ printk(KERN_INFO "cosa%d: rejecting packet on channel %d\n",
+ cosa->num, cosa->rxchan->num);
+ cosa->rxbuf = cosa->bouncebuf;
+ }
+
+ /* start the DMA */
+ flags = claim_dma_lock();
+ disable_dma(cosa->dma);
+ clear_dma_ff(cosa->dma);
+ set_dma_mode(cosa->dma, DMA_MODE_READ);
+ if (cosa_dma_able(cosa->rxchan, cosa->rxbuf, cosa->rxsize & 0x1fff)) {
+ set_dma_addr(cosa->dma, virt_to_bus(cosa->rxbuf));
+ } else {
+ set_dma_addr(cosa->dma, virt_to_bus(cosa->bouncebuf));
+ }
+ set_dma_count(cosa->dma, (cosa->rxsize&0x1fff));
+ enable_dma(cosa->dma);
+ release_dma_lock(flags);
+ spin_lock_irqsave(&cosa->lock, flags);
+ cosa_putstatus(cosa, SR_RX_DMA_ENA|SR_USR_INT_ENA);
+ if (!is_8bit(cosa) && (status & SR_TX_RDY))
+ cosa_putdata8(cosa, DRIVER_RX_READY);
+#ifdef DEBUG_IO
+ debug_status_out(cosa, SR_RX_DMA_ENA|SR_USR_INT_ENA);
+ if (!is_8bit(cosa) && (status & SR_TX_RDY))
+ debug_data_cmd(cosa, DRIVER_RX_READY);
+#endif
+ spin_unlock_irqrestore(&cosa->lock, flags);
+}
+
+static inline void eot_interrupt(struct cosa_data *cosa, int status)
+{
+ unsigned long flags, flags1;
+ spin_lock_irqsave(&cosa->lock, flags);
+ flags1 = claim_dma_lock();
+ disable_dma(cosa->dma);
+ clear_dma_ff(cosa->dma);
+ release_dma_lock(flags1);
+ if (test_bit(TXBIT, &cosa->rxtx)) {
+ struct channel_data *chan = cosa->chan+cosa->txchan;
+ if (chan->tx_done)
+ if (chan->tx_done(chan, cosa->txsize))
+ clear_bit(chan->num, &cosa->txbitmap);
+ } else if (test_bit(RXBIT, &cosa->rxtx)) {
+#ifdef DEBUG_DATA
+ {
+ int i;
+ printk(KERN_INFO "cosa%dc%d: done rx(0x%x)", cosa->num,
+ cosa->rxchan->num, cosa->rxsize);
+ for (i=0; irxsize; i++)
+ printk (" %02x", cosa->rxbuf[i]&0xff);
+ printk("\n");
+ }
+#endif
+ /* Packet for unknown channel? */
+ if (cosa->rxbuf == cosa->bouncebuf)
+ goto out;
+ if (!cosa_dma_able(cosa->rxchan, cosa->rxbuf, cosa->rxsize))
+ memcpy(cosa->rxbuf, cosa->bouncebuf, cosa->rxsize);
+ if (cosa->rxchan->rx_done)
+ if (cosa->rxchan->rx_done(cosa->rxchan))
+ clear_bit(cosa->rxchan->num, &cosa->rxbitmap);
+ } else {
+ printk(KERN_NOTICE "cosa%d: unexpected EOT interrupt\n",
+ cosa->num);
+ }
+ /*
+ * Clear the RXBIT, TXBIT and IRQBIT (the latest should be
+ * cleared anyway). We should do it as soon as possible
+ * so that we can tell the COSA we are done and to give it a time
+ * for recovery.
+ */
+out:
+ cosa->rxtx = 0;
+ put_driver_status_nolock(cosa);
+ spin_unlock_irqrestore(&cosa->lock, flags);
+}
+
+static irqreturn_t cosa_interrupt(int irq, void *cosa_, struct pt_regs *regs)
+{
+ unsigned status;
+ int count = 0;
+ struct cosa_data *cosa = cosa_;
+again:
+ status = cosa_getstatus(cosa);
+#ifdef DEBUG_IRQS
+ printk(KERN_INFO "cosa%d: got IRQ, status 0x%02x\n", cosa->num,
+ status & 0xff);
+#endif
+#ifdef DEBUG_IO
+ debug_status_in(cosa, status);
+#endif
+ switch (status & SR_CMD_FROM_SRP_MASK) {
+ case SR_DOWN_REQUEST:
+ tx_interrupt(cosa, status);
+ break;
+ case SR_UP_REQUEST:
+ rx_interrupt(cosa, status);
+ break;
+ case SR_END_OF_TRANSFER:
+ eot_interrupt(cosa, status);
+ break;
+ default:
+ /* We may be too fast for SRP. Try to wait a bit more. */
+ if (count++ < 100) {
+ udelay(100);
+ goto again;
+ }
+ printk(KERN_INFO "cosa%d: unknown status 0x%02x in IRQ after %d retries\n",
+ cosa->num, status & 0xff, count);
+ }
+#ifdef DEBUG_IRQS
+ if (count)
+ printk(KERN_INFO "%s: %d-times got unknown status in IRQ\n",
+ cosa->name, count);
+ else
+ printk(KERN_INFO "%s: returning from IRQ\n", cosa->name);
+#endif
+ return IRQ_HANDLED;
+}
+
+
+/* ---------- I/O debugging routines ---------- */
+/*
+ * These routines can be used to monitor COSA/SRP I/O and to printk()
+ * the data being transferred on the data and status I/O port in a
+ * readable way.
+ */
+
+#ifdef DEBUG_IO
+static void debug_status_in(struct cosa_data *cosa, int status)
+{
+ char *s;
+ switch(status & SR_CMD_FROM_SRP_MASK) {
+ case SR_UP_REQUEST:
+ s = "RX_REQ";
+ break;
+ case SR_DOWN_REQUEST:
+ s = "TX_REQ";
+ break;
+ case SR_END_OF_TRANSFER:
+ s = "ET_REQ";
+ break;
+ default:
+ s = "NO_REQ";
+ break;
+ }
+ printk(KERN_INFO "%s: IO: status -> 0x%02x (%s%s%s%s)\n",
+ cosa->name,
+ status,
+ status & SR_USR_RQ ? "USR_RQ|":"",
+ status & SR_TX_RDY ? "TX_RDY|":"",
+ status & SR_RX_RDY ? "RX_RDY|":"",
+ s);
+}
+
+static void debug_status_out(struct cosa_data *cosa, int status)
+{
+ printk(KERN_INFO "%s: IO: status <- 0x%02x (%s%s%s%s%s%s)\n",
+ cosa->name,
+ status,
+ status & SR_RX_DMA_ENA ? "RXDMA|":"!rxdma|",
+ status & SR_TX_DMA_ENA ? "TXDMA|":"!txdma|",
+ status & SR_RST ? "RESET|":"",
+ status & SR_USR_INT_ENA ? "USRINT|":"!usrint|",
+ status & SR_TX_INT_ENA ? "TXINT|":"!txint|",
+ status & SR_RX_INT_ENA ? "RXINT":"!rxint");
+}
+
+static void debug_data_in(struct cosa_data *cosa, int data)
+{
+ printk(KERN_INFO "%s: IO: data -> 0x%04x\n", cosa->name, data);
+}
+
+static void debug_data_out(struct cosa_data *cosa, int data)
+{
+ printk(KERN_INFO "%s: IO: data <- 0x%04x\n", cosa->name, data);
+}
+
+static void debug_data_cmd(struct cosa_data *cosa, int data)
+{
+ printk(KERN_INFO "%s: IO: data <- 0x%04x (%s|%s)\n",
+ cosa->name, data,
+ data & SR_RDY_RCV ? "RX_RDY" : "!rx_rdy",
+ data & SR_RDY_SND ? "TX_RDY" : "!tx_rdy");
+}
+#endif
+
+/* EOF -- this file has not been truncated */
diff --git a/drivers/net/wan/cosa.h b/drivers/net/wan/cosa.h
new file mode 100644
index 000000000000..028f3d96b971
--- /dev/null
+++ b/drivers/net/wan/cosa.h
@@ -0,0 +1,117 @@
+/* $Id: cosa.h,v 1.6 1999/01/06 14:02:44 kas Exp $ */
+
+/*
+ * Copyright (C) 1995-1997 Jan "Yenya" Kasprzak
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef COSA_H__
+#define COSA_H__
+
+#include
+
+#ifdef __KERNEL__
+/* status register - output bits */
+#define SR_RX_DMA_ENA 0x04 /* receiver DMA enable bit */
+#define SR_TX_DMA_ENA 0x08 /* transmitter DMA enable bit */
+#define SR_RST 0x10 /* SRP reset */
+#define SR_USR_INT_ENA 0x20 /* user interrupt enable bit */
+#define SR_TX_INT_ENA 0x40 /* transmitter interrupt enable bit */
+#define SR_RX_INT_ENA 0x80 /* receiver interrupt enable bit */
+
+/* status register - input bits */
+#define SR_USR_RQ 0x20 /* user interrupt request pending */
+#define SR_TX_RDY 0x40 /* transmitter empty (ready) */
+#define SR_RX_RDY 0x80 /* receiver data ready */
+
+#define SR_UP_REQUEST 0x02 /* request from SRP to transfer data
+ up to PC */
+#define SR_DOWN_REQUEST 0x01 /* SRP is able to transfer data down
+ from PC to SRP */
+#define SR_END_OF_TRANSFER 0x03 /* SRP signalize end of
+ transfer (up or down) */
+
+#define SR_CMD_FROM_SRP_MASK 0x03 /* mask to get SRP command */
+
+/* bits in driver status byte definitions : */
+#define SR_RDY_RCV 0x01 /* ready to receive packet */
+#define SR_RDY_SND 0x02 /* ready to send packet */
+#define SR_CMD_PND 0x04 /* command pending */ /* not currently used */
+
+/* ???? */
+#define SR_PKT_UP 0x01 /* transfer of packet up in progress */
+#define SR_PKT_DOWN 0x02 /* transfer of packet down in progress */
+
+#endif /* __KERNEL__ */
+
+#define SR_LOAD_ADDR 0x4400 /* SRP microcode load address */
+#define SR_START_ADDR 0x4400 /* SRP microcode start address */
+
+#define COSA_LOAD_ADDR 0x400 /* SRP microcode load address */
+#define COSA_MAX_FIRMWARE_SIZE 0x10000
+
+/* ioctls */
+struct cosa_download {
+ int addr, len;
+ char __user *code;
+};
+
+/* Reset the device */
+#define COSAIORSET _IO('C',0xf0)
+
+/* Start microcode at given address */
+#define COSAIOSTRT _IOW('C',0xf1, int)
+
+/* Read the block from the device memory */
+#define COSAIORMEM _IOWR('C',0xf2, struct cosa_download *)
+ /* actually the struct cosa_download itself; this is to keep
+ * the ioctl number same as in 2.4 in order to keep the user-space
+ * utils compatible. */
+
+/* Write the block to the device memory (i.e. download the microcode) */
+#define COSAIODOWNLD _IOW('C',0xf2, struct cosa_download *)
+ /* actually the struct cosa_download itself; this is to keep
+ * the ioctl number same as in 2.4 in order to keep the user-space
+ * utils compatible. */
+
+/* Read the device type (one of "srp", "cosa", and "cosa8" for now) */
+#define COSAIORTYPE _IOR('C',0xf3, char *)
+
+/* Read the device identification string */
+#define COSAIORIDSTR _IOR('C',0xf4, char *)
+/* Maximum length of the identification string. */
+#define COSA_MAX_ID_STRING 128
+
+/* Increment/decrement the module usage count :-) */
+/* #define COSAIOMINC _IO('C',0xf5) */
+/* #define COSAIOMDEC _IO('C',0xf6) */
+
+/* Get the total number of cards installed */
+#define COSAIONRCARDS _IO('C',0xf7)
+
+/* Get the number of channels on this card */
+#define COSAIONRCHANS _IO('C',0xf8)
+
+/* Set the driver for the bus-master operations */
+#define COSAIOBMSET _IOW('C', 0xf9, unsigned short)
+
+#define COSA_BM_OFF 0 /* Bus-mastering off - use ISA DMA (default) */
+#define COSA_BM_ON 1 /* Bus-mastering on - faster but untested */
+
+/* Gets the busmaster status */
+#define COSAIOBMGET _IO('C', 0xfa)
+
+#endif /* !COSA_H__ */
diff --git a/drivers/net/wan/cycx_drv.c b/drivers/net/wan/cycx_drv.c
new file mode 100644
index 000000000000..6e74af62ca08
--- /dev/null
+++ b/drivers/net/wan/cycx_drv.c
@@ -0,0 +1,586 @@
+/*
+* cycx_drv.c Cyclom 2X Support Module.
+*
+* This module is a library of common hardware specific
+* functions used by the Cyclades Cyclom 2X sync card.
+*
+* Author: Arnaldo Carvalho de Melo
+*
+* Copyright: (c) 1998-2003 Arnaldo Carvalho de Melo
+*
+* Based on sdladrv.c by Gene Kozin
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version
+* 2 of the License, or (at your option) any later version.
+* ============================================================================
+* 1999/11/11 acme set_current_state(TASK_INTERRUPTIBLE), code
+* cleanup
+* 1999/11/08 acme init_cyc2x deleted, doing nothing
+* 1999/11/06 acme back to read[bw], write[bw] and memcpy_to and
+* fromio to use dpmbase ioremaped
+* 1999/10/26 acme use isa_read[bw], isa_write[bw] & isa_memcpy_to
+* & fromio
+* 1999/10/23 acme cleanup to only supports cyclom2x: all the other
+* boards are no longer manufactured by cyclades,
+* if someone wants to support them... be my guest!
+* 1999/05/28 acme cycx_intack & cycx_intde gone for good
+* 1999/05/18 acme lots of unlogged work, submitting to Linus...
+* 1999/01/03 acme more judicious use of data types
+* 1999/01/03 acme judicious use of data types :>
+* cycx_inten trying to reset pending interrupts
+* from cyclom 2x - I think this isn't the way to
+* go, but for now...
+* 1999/01/02 acme cycx_intack ok, I think there's nothing to do
+* to ack an int in cycx_drv.c, only handle it in
+* cyx_isr (or in the other protocols: cyp_isr,
+* cyf_isr, when they get implemented.
+* Dec 31, 1998 acme cycx_data_boot & cycx_code_boot fixed, crossing
+* fingers to see x25_configure in cycx_x25.c
+* work... :)
+* Dec 26, 1998 acme load implementation fixed, seems to work! :)
+* cycx_2x_dpmbase_options with all the possible
+* DPM addresses (20).
+* cycx_intr implemented (test this!)
+* general code cleanup
+* Dec 8, 1998 Ivan Passos Cyclom-2X firmware load implementation.
+* Aug 8, 1998 acme Initial version.
+*/
+
+#include /* __init */
+#include
+#include /* printk(), and other useful stuff */
+#include /* offsetof(), etc. */
+#include /* return codes */
+#include /* for jiffies, HZ, etc. */
+#include /* API definitions */
+#include /* CYCX firmware module definitions */
+#include /* udelay */
+#include /* read[wl], write[wl], ioremap, iounmap */
+
+#define MOD_VERSION 0
+#define MOD_RELEASE 6
+
+MODULE_AUTHOR("Arnaldo Carvalho de Melo");
+MODULE_DESCRIPTION("Cyclom 2x Sync Card Driver");
+MODULE_LICENSE("GPL");
+
+/* Hardware-specific functions */
+static int load_cyc2x(struct cycx_hw *hw, struct cycx_firmware *cfm, u32 len);
+static void cycx_bootcfg(struct cycx_hw *hw);
+
+static int reset_cyc2x(void __iomem *addr);
+static int detect_cyc2x(void __iomem *addr);
+
+/* Miscellaneous functions */
+static void delay_cycx(int sec);
+static int get_option_index(long *optlist, long optval);
+static u16 checksum(u8 *buf, u32 len);
+
+#define wait_cyc(addr) cycx_exec(addr + CMD_OFFSET)
+
+/* Global Data */
+
+/* private data */
+static char modname[] = "cycx_drv";
+static char fullname[] = "Cyclom 2X Support Module";
+static char copyright[] = "(c) 1998-2003 Arnaldo Carvalho de Melo "
+ "";
+
+/* Hardware configuration options.
+ * These are arrays of configuration options used by verification routines.
+ * The first element of each array is its size (i.e. number of options).
+ */
+static long cyc2x_dpmbase_options[] = {
+ 20,
+ 0xA0000, 0xA4000, 0xA8000, 0xAC000, 0xB0000, 0xB4000, 0xB8000,
+ 0xBC000, 0xC0000, 0xC4000, 0xC8000, 0xCC000, 0xD0000, 0xD4000,
+ 0xD8000, 0xDC000, 0xE0000, 0xE4000, 0xE8000, 0xEC000
+};
+
+static long cycx_2x_irq_options[] = { 7, 3, 5, 9, 10, 11, 12, 15 };
+
+/* Kernel Loadable Module Entry Points */
+/* Module 'insert' entry point.
+ * o print announcement
+ * o initialize static data
+ *
+ * Return: 0 Ok
+ * < 0 error.
+ * Context: process */
+
+int __init cycx_drv_init(void)
+{
+ printk(KERN_INFO "%s v%u.%u %s\n", fullname, MOD_VERSION, MOD_RELEASE,
+ copyright);
+
+ return 0;
+}
+
+/* Module 'remove' entry point.
+ * o release all remaining system resources */
+void cycx_drv_cleanup(void)
+{
+}
+
+/* Kernel APIs */
+/* Set up adapter.
+ * o detect adapter type
+ * o verify hardware configuration options
+ * o check for hardware conflicts
+ * o set up adapter shared memory
+ * o test adapter memory
+ * o load firmware
+ * Return: 0 ok.
+ * < 0 error */
+EXPORT_SYMBOL(cycx_setup);
+int cycx_setup(struct cycx_hw *hw, void *cfm, u32 len, unsigned long dpmbase)
+{
+ int err;
+
+ /* Verify IRQ configuration options */
+ if (!get_option_index(cycx_2x_irq_options, hw->irq)) {
+ printk(KERN_ERR "%s: IRQ %d is invalid!\n", modname, hw->irq);
+ return -EINVAL;
+ }
+
+ /* Setup adapter dual-port memory window and test memory */
+ if (!dpmbase) {
+ printk(KERN_ERR "%s: you must specify the dpm address!\n",
+ modname);
+ return -EINVAL;
+ } else if (!get_option_index(cyc2x_dpmbase_options, dpmbase)) {
+ printk(KERN_ERR "%s: memory address 0x%lX is invalid!\n",
+ modname, dpmbase);
+ return -EINVAL;
+ }
+
+ hw->dpmbase = ioremap(dpmbase, CYCX_WINDOWSIZE);
+ hw->dpmsize = CYCX_WINDOWSIZE;
+
+ if (!detect_cyc2x(hw->dpmbase)) {
+ printk(KERN_ERR "%s: adapter Cyclom 2X not found at "
+ "address 0x%lX!\n", modname, dpmbase);
+ return -EINVAL;
+ }
+
+ printk(KERN_INFO "%s: found Cyclom 2X card at address 0x%lX.\n",
+ modname, dpmbase);
+
+ /* Load firmware. If loader fails then shut down adapter */
+ err = load_cyc2x(hw, cfm, len);
+
+ if (err)
+ cycx_down(hw); /* shutdown adapter */
+
+ return err;
+}
+
+EXPORT_SYMBOL(cycx_down);
+int cycx_down(struct cycx_hw *hw)
+{
+ iounmap(hw->dpmbase);
+ return 0;
+}
+
+/* Enable interrupt generation. */
+EXPORT_SYMBOL(cycx_inten);
+void cycx_inten(struct cycx_hw *hw)
+{
+ writeb(0, hw->dpmbase);
+}
+
+/* Generate an interrupt to adapter's CPU. */
+EXPORT_SYMBOL(cycx_intr);
+void cycx_intr(struct cycx_hw *hw)
+{
+ writew(0, hw->dpmbase + GEN_CYCX_INTR);
+}
+
+/* Execute Adapter Command.
+ * o Set exec flag.
+ * o Busy-wait until flag is reset. */
+EXPORT_SYMBOL(cycx_exec);
+int cycx_exec(void __iomem *addr)
+{
+ u16 i = 0;
+ /* wait till addr content is zeroed */
+
+ while (readw(addr)) {
+ udelay(1000);
+
+ if (++i > 50)
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Read absolute adapter memory.
+ * Transfer data from adapter's memory to data buffer. */
+EXPORT_SYMBOL(cycx_peek);
+int cycx_peek(struct cycx_hw *hw, u32 addr, void *buf, u32 len)
+{
+ if (len == 1)
+ *(u8*)buf = readb(hw->dpmbase + addr);
+ else
+ memcpy_fromio(buf, hw->dpmbase + addr, len);
+
+ return 0;
+}
+
+/* Write Absolute Adapter Memory.
+ * Transfer data from data buffer to adapter's memory. */
+EXPORT_SYMBOL(cycx_poke);
+int cycx_poke(struct cycx_hw *hw, u32 addr, void *buf, u32 len)
+{
+ if (len == 1)
+ writeb(*(u8*)buf, hw->dpmbase + addr);
+ else
+ memcpy_toio(hw->dpmbase + addr, buf, len);
+
+ return 0;
+}
+
+/* Hardware-Specific Functions */
+
+/* Load Aux Routines */
+/* Reset board hardware.
+ return 1 if memory exists at addr and 0 if not. */
+static int memory_exists(void __iomem *addr)
+{
+ int tries = 0;
+
+ for (; tries < 3 ; tries++) {
+ writew(TEST_PATTERN, addr + 0x10);
+
+ if (readw(addr + 0x10) == TEST_PATTERN)
+ if (readw(addr + 0x10) == TEST_PATTERN)
+ return 1;
+
+ delay_cycx(1);
+ }
+
+ return 0;
+}
+
+/* Load reset code. */
+static void reset_load(void __iomem *addr, u8 *buffer, u32 cnt)
+{
+ void __iomem *pt_code = addr + RESET_OFFSET;
+ u16 i; /*, j; */
+
+ for (i = 0 ; i < cnt ; i++) {
+/* for (j = 0 ; j < 50 ; j++); Delay - FIXME busy waiting... */
+ writeb(*buffer++, pt_code++);
+ }
+}
+
+/* Load buffer using boot interface.
+ * o copy data from buffer to Cyclom-X memory
+ * o wait for reset code to copy it to right portion of memory */
+static int buffer_load(void __iomem *addr, u8 *buffer, u32 cnt)
+{
+ memcpy_toio(addr + DATA_OFFSET, buffer, cnt);
+ writew(GEN_BOOT_DAT, addr + CMD_OFFSET);
+
+ return wait_cyc(addr);
+}
+
+/* Set up entry point and kick start Cyclom-X CPU. */
+static void cycx_start(void __iomem *addr)
+{
+ /* put in 0x30 offset the jump instruction to the code entry point */
+ writeb(0xea, addr + 0x30);
+ writeb(0x00, addr + 0x31);
+ writeb(0xc4, addr + 0x32);
+ writeb(0x00, addr + 0x33);
+ writeb(0x00, addr + 0x34);
+
+ /* cmd to start executing code */
+ writew(GEN_START, addr + CMD_OFFSET);
+}
+
+/* Load and boot reset code. */
+static void cycx_reset_boot(void __iomem *addr, u8 *code, u32 len)
+{
+ void __iomem *pt_start = addr + START_OFFSET;
+
+ writeb(0xea, pt_start++); /* jmp to f000:3f00 */
+ writeb(0x00, pt_start++);
+ writeb(0xfc, pt_start++);
+ writeb(0x00, pt_start++);
+ writeb(0xf0, pt_start);
+ reset_load(addr, code, len);
+
+ /* 80186 was in hold, go */
+ writeb(0, addr + START_CPU);
+ delay_cycx(1);
+}
+
+/* Load data.bin file through boot (reset) interface. */
+static int cycx_data_boot(void __iomem *addr, u8 *code, u32 len)
+{
+ void __iomem *pt_boot_cmd = addr + CMD_OFFSET;
+ u32 i;
+
+ /* boot buffer lenght */
+ writew(CFM_LOAD_BUFSZ, pt_boot_cmd + sizeof(u16));
+ writew(GEN_DEFPAR, pt_boot_cmd);
+
+ if (wait_cyc(addr) < 0)
+ return -1;
+
+ writew(0, pt_boot_cmd + sizeof(u16));
+ writew(0x4000, pt_boot_cmd + 2 * sizeof(u16));
+ writew(GEN_SET_SEG, pt_boot_cmd);
+
+ if (wait_cyc(addr) < 0)
+ return -1;
+
+ for (i = 0 ; i < len ; i += CFM_LOAD_BUFSZ)
+ if (buffer_load(addr, code + i,
+ min_t(u32, CFM_LOAD_BUFSZ, (len - i))) < 0) {
+ printk(KERN_ERR "%s: Error !!\n", modname);
+ return -1;
+ }
+
+ return 0;
+}
+
+
+/* Load code.bin file through boot (reset) interface. */
+static int cycx_code_boot(void __iomem *addr, u8 *code, u32 len)
+{
+ void __iomem *pt_boot_cmd = addr + CMD_OFFSET;
+ u32 i;
+
+ /* boot buffer lenght */
+ writew(CFM_LOAD_BUFSZ, pt_boot_cmd + sizeof(u16));
+ writew(GEN_DEFPAR, pt_boot_cmd);
+
+ if (wait_cyc(addr) < 0)
+ return -1;
+
+ writew(0x0000, pt_boot_cmd + sizeof(u16));
+ writew(0xc400, pt_boot_cmd + 2 * sizeof(u16));
+ writew(GEN_SET_SEG, pt_boot_cmd);
+
+ if (wait_cyc(addr) < 0)
+ return -1;
+
+ for (i = 0 ; i < len ; i += CFM_LOAD_BUFSZ)
+ if (buffer_load(addr, code + i,
+ min_t(u32, CFM_LOAD_BUFSZ, (len - i)))) {
+ printk(KERN_ERR "%s: Error !!\n", modname);
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Load adapter from the memory image of the CYCX firmware module.
+ * o verify firmware integrity and compatibility
+ * o start adapter up */
+static int load_cyc2x(struct cycx_hw *hw, struct cycx_firmware *cfm, u32 len)
+{
+ int i, j;
+ struct cycx_fw_header *img_hdr;
+ u8 *reset_image,
+ *data_image,
+ *code_image;
+ void __iomem *pt_cycld = hw->dpmbase + 0x400;
+ u16 cksum;
+
+ /* Announce */
+ printk(KERN_INFO "%s: firmware signature=\"%s\"\n", modname,
+ cfm->signature);
+
+ /* Verify firmware signature */
+ if (strcmp(cfm->signature, CFM_SIGNATURE)) {
+ printk(KERN_ERR "%s:load_cyc2x: not Cyclom-2X firmware!\n",
+ modname);
+ return -EINVAL;
+ }
+
+ printk(KERN_INFO "%s: firmware version=%u\n", modname, cfm->version);
+
+ /* Verify firmware module format version */
+ if (cfm->version != CFM_VERSION) {
+ printk(KERN_ERR "%s:%s: firmware format %u rejected! "
+ "Expecting %u.\n",
+ modname, __FUNCTION__, cfm->version, CFM_VERSION);
+ return -EINVAL;
+ }
+
+ /* Verify firmware module length and checksum */
+ cksum = checksum((u8*)&cfm->info, sizeof(struct cycx_fw_info) +
+ cfm->info.codesize);
+/*
+ FIXME cfm->info.codesize is off by 2
+ if (((len - sizeof(struct cycx_firmware) - 1) != cfm->info.codesize) ||
+*/
+ if (cksum != cfm->checksum) {
+ printk(KERN_ERR "%s:%s: firmware corrupted!\n",
+ modname, __FUNCTION__);
+ printk(KERN_ERR " cdsize = 0x%x (expected 0x%lx)\n",
+ len - (int)sizeof(struct cycx_firmware) - 1,
+ cfm->info.codesize);
+ printk(KERN_ERR " chksum = 0x%x (expected 0x%x)\n",
+ cksum, cfm->checksum);
+ return -EINVAL;
+ }
+
+ /* If everything is ok, set reset, data and code pointers */
+ img_hdr = (struct cycx_fw_header *)&cfm->image;
+#ifdef FIRMWARE_DEBUG
+ printk(KERN_INFO "%s:%s: image sizes\n", __FUNCTION__, modname);
+ printk(KERN_INFO " reset=%lu\n", img_hdr->reset_size);
+ printk(KERN_INFO " data=%lu\n", img_hdr->data_size);
+ printk(KERN_INFO " code=%lu\n", img_hdr->code_size);
+#endif
+ reset_image = ((u8 *)img_hdr) + sizeof(struct cycx_fw_header);
+ data_image = reset_image + img_hdr->reset_size;
+ code_image = data_image + img_hdr->data_size;
+
+ /*---- Start load ----*/
+ /* Announce */
+ printk(KERN_INFO "%s: loading firmware %s (ID=%u)...\n", modname,
+ cfm->descr[0] ? cfm->descr : "unknown firmware",
+ cfm->info.codeid);
+
+ for (i = 0 ; i < 5 ; i++) {
+ /* Reset Cyclom hardware */
+ if (!reset_cyc2x(hw->dpmbase)) {
+ printk(KERN_ERR "%s: dpm problem or board not found\n",
+ modname);
+ return -EINVAL;
+ }
+
+ /* Load reset.bin */
+ cycx_reset_boot(hw->dpmbase, reset_image, img_hdr->reset_size);
+ /* reset is waiting for boot */
+ writew(GEN_POWER_ON, pt_cycld);
+ delay_cycx(1);
+
+ for (j = 0 ; j < 3 ; j++)
+ if (!readw(pt_cycld))
+ goto reset_loaded;
+ else
+ delay_cycx(1);
+ }
+
+ printk(KERN_ERR "%s: reset not started.\n", modname);
+ return -EINVAL;
+
+reset_loaded:
+ /* Load data.bin */
+ if (cycx_data_boot(hw->dpmbase, data_image, img_hdr->data_size)) {
+ printk(KERN_ERR "%s: cannot load data file.\n", modname);
+ return -EINVAL;
+ }
+
+ /* Load code.bin */
+ if (cycx_code_boot(hw->dpmbase, code_image, img_hdr->code_size)) {
+ printk(KERN_ERR "%s: cannot load code file.\n", modname);
+ return -EINVAL;
+ }
+
+ /* Prepare boot-time configuration data */
+ cycx_bootcfg(hw);
+
+ /* kick-off CPU */
+ cycx_start(hw->dpmbase);
+
+ /* Arthur Ganzert's tip: wait a while after the firmware loading...
+ seg abr 26 17:17:12 EST 1999 - acme */
+ delay_cycx(7);
+ printk(KERN_INFO "%s: firmware loaded!\n", modname);
+
+ /* enable interrupts */
+ cycx_inten(hw);
+
+ return 0;
+}
+
+/* Prepare boot-time firmware configuration data.
+ * o initialize configuration data area
+ From async.doc - V_3.4.0 - 07/18/1994
+ - As of now, only static buffers are available to the user.
+ So, the bit VD_RXDIRC must be set in 'valid'. That means that user
+ wants to use the static transmission and reception buffers. */
+static void cycx_bootcfg(struct cycx_hw *hw)
+{
+ /* use fixed buffers */
+ writeb(FIXED_BUFFERS, hw->dpmbase + CONF_OFFSET);
+}
+
+/* Detect Cyclom 2x adapter.
+ * Following tests are used to detect Cyclom 2x adapter:
+ * to be completed based on the tests done below
+ * Return 1 if detected o.k. or 0 if failed.
+ * Note: This test is destructive! Adapter will be left in shutdown
+ * state after the test. */
+static int detect_cyc2x(void __iomem *addr)
+{
+ reset_cyc2x(addr);
+
+ return memory_exists(addr);
+}
+
+/* Miscellaneous */
+/* Get option's index into the options list.
+ * Return option's index (1 .. N) or zero if option is invalid. */
+static int get_option_index(long *optlist, long optval)
+{
+ int i = 1;
+
+ for (; i <= optlist[0]; ++i)
+ if (optlist[i] == optval)
+ return i;
+
+ return 0;
+}
+
+/* Reset adapter's CPU. */
+static int reset_cyc2x(void __iomem *addr)
+{
+ writeb(0, addr + RST_ENABLE);
+ delay_cycx(2);
+ writeb(0, addr + RST_DISABLE);
+ delay_cycx(2);
+
+ return memory_exists(addr);
+}
+
+/* Delay */
+static void delay_cycx(int sec)
+{
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(sec * HZ);
+}
+
+/* Calculate 16-bit CRC using CCITT polynomial. */
+static u16 checksum(u8 *buf, u32 len)
+{
+ u16 crc = 0;
+ u16 mask, flag;
+
+ for (; len; --len, ++buf)
+ for (mask = 0x80; mask; mask >>= 1) {
+ flag = (crc & 0x8000);
+ crc <<= 1;
+ crc |= ((*buf & mask) ? 1 : 0);
+
+ if (flag)
+ crc ^= 0x1021;
+ }
+
+ return crc;
+}
+
+module_init(cycx_drv_init);
+module_exit(cycx_drv_cleanup);
+
+/* End */
diff --git a/drivers/net/wan/cycx_main.c b/drivers/net/wan/cycx_main.c
new file mode 100644
index 000000000000..7b48064364dc
--- /dev/null
+++ b/drivers/net/wan/cycx_main.c
@@ -0,0 +1,351 @@
+/*
+* cycx_main.c Cyclades Cyclom 2X WAN Link Driver. Main module.
+*
+* Author: Arnaldo Carvalho de Melo
+*
+* Copyright: (c) 1998-2003 Arnaldo Carvalho de Melo
+*
+* Based on sdlamain.c by Gene Kozin &
+* Jaspreet Singh
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version
+* 2 of the License, or (at your option) any later version.
+* ============================================================================
+* Please look at the bitkeeper changelog (or any other scm tool that ends up
+* importing bitkeeper changelog or that replaces bitkeeper in the future as
+* main tool for linux development).
+*
+* 2001/05/09 acme Fix MODULE_DESC for debug, .bss nitpicks,
+* some cleanups
+* 2000/07/13 acme remove useless #ifdef MODULE and crap
+* #if KERNEL_VERSION > blah
+* 2000/07/06 acme __exit at cyclomx_cleanup
+* 2000/04/02 acme dprintk and cycx_debug
+* module_init/module_exit
+* 2000/01/21 acme rename cyclomx_open to cyclomx_mod_inc_use_count
+* and cyclomx_close to cyclomx_mod_dec_use_count
+* 2000/01/08 acme cleanup
+* 1999/11/06 acme cycx_down back to life (it needs to be
+* called to iounmap the dpmbase)
+* 1999/08/09 acme removed references to enable_tx_int
+* use spinlocks instead of cli/sti in
+* cyclomx_set_state
+* 1999/05/19 acme works directly linked into the kernel
+* init_waitqueue_head for 2.3.* kernel
+* 1999/05/18 acme major cleanup (polling not needed), etc
+* 1998/08/28 acme minor cleanup (ioctls for firmware deleted)
+* queue_task activated
+* 1998/08/08 acme Initial version.
+*/
+
+#include /* OS configuration options */
+#include /* offsetof(), etc. */
+#include /* return codes */
+#include /* inline memset(), etc. */
+#include /* kmalloc(), kfree() */
+#include /* printk(), and other useful stuff */
+#include /* support for loadable modules */
+#include /* request_region(), release_region() */
+#include /* WAN router definitions */
+#include /* cyclomx common user API definitions */
+#include /* __init (when not using as a module) */
+
+unsigned int cycx_debug;
+
+MODULE_AUTHOR("Arnaldo Carvalho de Melo");
+MODULE_DESCRIPTION("Cyclom 2X Sync Card Driver.");
+MODULE_LICENSE("GPL");
+module_param(cycx_debug, int, 0);
+MODULE_PARM_DESC(cycx_debug, "cyclomx debug level");
+
+/* Defines & Macros */
+
+#define CYCX_DRV_VERSION 0 /* version number */
+#define CYCX_DRV_RELEASE 11 /* release (minor version) number */
+#define CYCX_MAX_CARDS 1 /* max number of adapters */
+
+#define CONFIG_CYCX_CARDS 1
+
+/* Function Prototypes */
+
+/* WAN link driver entry points */
+static int cycx_wan_setup(struct wan_device *wandev, wandev_conf_t *conf);
+static int cycx_wan_shutdown(struct wan_device *wandev);
+
+/* Miscellaneous functions */
+static irqreturn_t cycx_isr(int irq, void *dev_id, struct pt_regs *regs);
+
+/* Global Data
+ * Note: All data must be explicitly initialized!!!
+ */
+
+/* private data */
+static char cycx_drvname[] = "cyclomx";
+static char cycx_fullname[] = "CYCLOM 2X(tm) Sync Card Driver";
+static char cycx_copyright[] = "(c) 1998-2003 Arnaldo Carvalho de Melo "
+ "";
+static int cycx_ncards = CONFIG_CYCX_CARDS;
+static struct cycx_device *cycx_card_array; /* adapter data space */
+
+/* Kernel Loadable Module Entry Points */
+
+/*
+ * Module 'insert' entry point.
+ * o print announcement
+ * o allocate adapter data space
+ * o initialize static data
+ * o register all cards with WAN router
+ * o calibrate Cyclom 2X shared memory access delay.
+ *
+ * Return: 0 Ok
+ * < 0 error.
+ * Context: process
+ */
+int __init cycx_init(void)
+{
+ int cnt, err = -ENOMEM;
+
+ printk(KERN_INFO "%s v%u.%u %s\n",
+ cycx_fullname, CYCX_DRV_VERSION, CYCX_DRV_RELEASE,
+ cycx_copyright);
+
+ /* Verify number of cards and allocate adapter data space */
+ cycx_ncards = min_t(int, cycx_ncards, CYCX_MAX_CARDS);
+ cycx_ncards = max_t(int, cycx_ncards, 1);
+ cycx_card_array = kmalloc(sizeof(struct cycx_device) * cycx_ncards,
+ GFP_KERNEL);
+ if (!cycx_card_array)
+ goto out;
+
+ memset(cycx_card_array, 0, sizeof(struct cycx_device) * cycx_ncards);
+
+ /* Register adapters with WAN router */
+ for (cnt = 0; cnt < cycx_ncards; ++cnt) {
+ struct cycx_device *card = &cycx_card_array[cnt];
+ struct wan_device *wandev = &card->wandev;
+
+ sprintf(card->devname, "%s%d", cycx_drvname, cnt + 1);
+ wandev->magic = ROUTER_MAGIC;
+ wandev->name = card->devname;
+ wandev->private = card;
+ wandev->setup = cycx_wan_setup;
+ wandev->shutdown = cycx_wan_shutdown;
+ err = register_wan_device(wandev);
+
+ if (err) {
+ printk(KERN_ERR "%s: %s registration failed with "
+ "error %d!\n",
+ cycx_drvname, card->devname, err);
+ break;
+ }
+ }
+
+ err = -ENODEV;
+ if (!cnt) {
+ kfree(cycx_card_array);
+ goto out;
+ }
+ err = 0;
+ cycx_ncards = cnt; /* adjust actual number of cards */
+out: return err;
+}
+
+/*
+ * Module 'remove' entry point.
+ * o unregister all adapters from the WAN router
+ * o release all remaining system resources
+ */
+static void __exit cycx_exit(void)
+{
+ int i = 0;
+
+ for (; i < cycx_ncards; ++i) {
+ struct cycx_device *card = &cycx_card_array[i];
+ unregister_wan_device(card->devname);
+ }
+
+ kfree(cycx_card_array);
+}
+
+/* WAN Device Driver Entry Points */
+/*
+ * Setup/configure WAN link driver.
+ * o check adapter state
+ * o make sure firmware is present in configuration
+ * o allocate interrupt vector
+ * o setup Cyclom 2X hardware
+ * o call appropriate routine to perform protocol-specific initialization
+ *
+ * This function is called when router handles ROUTER_SETUP IOCTL. The
+ * configuration structure is in kernel memory (including extended data, if
+ * any).
+ */
+static int cycx_wan_setup(struct wan_device *wandev, wandev_conf_t *conf)
+{
+ int rc = -EFAULT;
+ struct cycx_device *card;
+ int irq;
+
+ /* Sanity checks */
+
+ if (!wandev || !wandev->private || !conf)
+ goto out;
+
+ card = wandev->private;
+ rc = -EBUSY;
+ if (wandev->state != WAN_UNCONFIGURED)
+ goto out;
+
+ rc = -EINVAL;
+ if (!conf->data_size || !conf->data) {
+ printk(KERN_ERR "%s: firmware not found in configuration "
+ "data!\n", wandev->name);
+ goto out;
+ }
+
+ if (conf->irq <= 0) {
+ printk(KERN_ERR "%s: can't configure without IRQ!\n",
+ wandev->name);
+ goto out;
+ }
+
+ /* Allocate IRQ */
+ irq = conf->irq == 2 ? 9 : conf->irq; /* IRQ2 -> IRQ9 */
+
+ if (request_irq(irq, cycx_isr, 0, wandev->name, card)) {
+ printk(KERN_ERR "%s: can't reserve IRQ %d!\n",
+ wandev->name, irq);
+ goto out;
+ }
+
+ /* Configure hardware, load firmware, etc. */
+ memset(&card->hw, 0, sizeof(card->hw));
+ card->hw.irq = irq;
+ card->hw.dpmsize = CYCX_WINDOWSIZE;
+ card->hw.fwid = CFID_X25_2X;
+ spin_lock_init(&card->lock);
+ init_waitqueue_head(&card->wait_stats);
+
+ rc = cycx_setup(&card->hw, conf->data, conf->data_size, conf->maddr);
+ if (rc)
+ goto out_irq;
+
+ /* Initialize WAN device data space */
+ wandev->irq = irq;
+ wandev->dma = wandev->ioport = 0;
+ wandev->maddr = (unsigned long)card->hw.dpmbase;
+ wandev->msize = card->hw.dpmsize;
+ wandev->hw_opt[2] = 0;
+ wandev->hw_opt[3] = card->hw.fwid;
+
+ /* Protocol-specific initialization */
+ switch (card->hw.fwid) {
+#ifdef CONFIG_CYCLOMX_X25
+ case CFID_X25_2X:
+ rc = cycx_x25_wan_init(card, conf);
+ break;
+#endif
+ default:
+ printk(KERN_ERR "%s: this firmware is not supported!\n",
+ wandev->name);
+ rc = -EINVAL;
+ }
+
+ if (rc) {
+ cycx_down(&card->hw);
+ goto out_irq;
+ }
+
+ rc = 0;
+out:
+ return rc;
+out_irq:
+ free_irq(irq, card);
+ goto out;
+}
+
+/*
+ * Shut down WAN link driver.
+ * o shut down adapter hardware
+ * o release system resources.
+ *
+ * This function is called by the router when device is being unregistered or
+ * when it handles ROUTER_DOWN IOCTL.
+ */
+static int cycx_wan_shutdown(struct wan_device *wandev)
+{
+ int ret = -EFAULT;
+ struct cycx_device *card;
+
+ /* sanity checks */
+ if (!wandev || !wandev->private)
+ goto out;
+
+ ret = 0;
+ if (wandev->state == WAN_UNCONFIGURED)
+ goto out;
+
+ card = wandev->private;
+ wandev->state = WAN_UNCONFIGURED;
+ cycx_down(&card->hw);
+ printk(KERN_INFO "%s: irq %d being freed!\n", wandev->name,
+ wandev->irq);
+ free_irq(wandev->irq, card);
+out: return ret;
+}
+
+/* Miscellaneous */
+/*
+ * Cyclom 2X Interrupt Service Routine.
+ * o acknowledge Cyclom 2X hardware interrupt.
+ * o call protocol-specific interrupt service routine, if any.
+ */
+static irqreturn_t cycx_isr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct cycx_device *card = (struct cycx_device *)dev_id;
+
+ if (!card || card->wandev.state == WAN_UNCONFIGURED)
+ goto out;
+
+ if (card->in_isr) {
+ printk(KERN_WARNING "%s: interrupt re-entrancy on IRQ %d!\n",
+ card->devname, card->wandev.irq);
+ goto out;
+ }
+
+ if (card->isr)
+ card->isr(card);
+ return IRQ_HANDLED;
+out:
+ return IRQ_NONE;
+}
+
+/* Set WAN device state. */
+void cycx_set_state(struct cycx_device *card, int state)
+{
+ unsigned long flags;
+ char *string_state = NULL;
+
+ spin_lock_irqsave(&card->lock, flags);
+
+ if (card->wandev.state != state) {
+ switch (state) {
+ case WAN_CONNECTED:
+ string_state = "connected!";
+ break;
+ case WAN_DISCONNECTED:
+ string_state = "disconnected!";
+ break;
+ }
+ printk(KERN_INFO "%s: link %s\n", card->devname, string_state);
+ card->wandev.state = state;
+ }
+
+ card->state_tick = jiffies;
+ spin_unlock_irqrestore(&card->lock, flags);
+}
+
+module_init(cycx_init);
+module_exit(cycx_exit);
diff --git a/drivers/net/wan/cycx_x25.c b/drivers/net/wan/cycx_x25.c
new file mode 100644
index 000000000000..5b48cd8568f5
--- /dev/null
+++ b/drivers/net/wan/cycx_x25.c
@@ -0,0 +1,1609 @@
+/*
+* cycx_x25.c Cyclom 2X WAN Link Driver. X.25 module.
+*
+* Author: Arnaldo Carvalho de Melo
+*
+* Copyright: (c) 1998-2003 Arnaldo Carvalho de Melo
+*
+* Based on sdla_x25.c by Gene Kozin
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version
+* 2 of the License, or (at your option) any later version.
+* ============================================================================
+* 2001/01/12 acme use dev_kfree_skb_irq on interrupt context
+* 2000/04/02 acme dprintk, cycx_debug
+* fixed the bug introduced in get_dev_by_lcn and
+* get_dev_by_dte_addr by the anonymous hacker
+* that converted this driver to softnet
+* 2000/01/08 acme cleanup
+* 1999/10/27 acme use ARPHRD_HWX25 so that the X.25 stack know
+* that we have a X.25 stack implemented in
+* firmware onboard
+* 1999/10/18 acme support for X.25 sockets in if_send,
+* beware: socket(AF_X25...) IS WORK IN PROGRESS,
+* TCP/IP over X.25 via wanrouter not affected,
+* working.
+* 1999/10/09 acme chan_disc renamed to chan_disconnect,
+* began adding support for X.25 sockets:
+* conf->protocol in new_if
+* 1999/10/05 acme fixed return E... to return -E...
+* 1999/08/10 acme serialized access to the card thru a spinlock
+* in x25_exec
+* 1999/08/09 acme removed per channel spinlocks
+* removed references to enable_tx_int
+* 1999/05/28 acme fixed nibble_to_byte, ackvc now properly treated
+* if_send simplified
+* 1999/05/25 acme fixed t1, t2, t21 & t23 configuration
+* use spinlocks instead of cli/sti in some points
+* 1999/05/24 acme finished the x25_get_stat function
+* 1999/05/23 acme dev->type = ARPHRD_X25 (tcpdump only works,
+* AFAIT, with ARPHRD_ETHER). This seems to be
+* needed to use socket(AF_X25)...
+* Now the config file must specify a peer media
+* address for svc channels over a crossover cable.
+* Removed hold_timeout from x25_channel_t,
+* not used.
+* A little enhancement in the DEBUG processing
+* 1999/05/22 acme go to DISCONNECTED in disconnect_confirm_intr,
+* instead of chan_disc.
+* 1999/05/16 marcelo fixed timer initialization in SVCs
+* 1999/01/05 acme x25_configure now get (most of) all
+* parameters...
+* 1999/01/05 acme pktlen now (correctly) uses log2 (value
+* configured)
+* 1999/01/03 acme judicious use of data types (u8, u16, u32, etc)
+* 1999/01/03 acme cyx_isr: reset dpmbase to acknowledge
+* indication (interrupt from cyclom 2x)
+* 1999/01/02 acme cyx_isr: first hackings...
+* 1999/01/0203 acme when initializing an array don't give less
+* elements than declared...
+* example: char send_cmd[6] = "?\xFF\x10";
+* you'll gonna lose a couple hours, 'cause your
+* brain won't admit that there's an error in the
+* above declaration... the side effect is that
+* memset is put into the unresolved symbols
+* instead of using the inline memset functions...
+* 1999/01/02 acme began chan_connect, chan_send, x25_send
+* 1998/12/31 acme x25_configure
+* this code can be compiled as non module
+* 1998/12/27 acme code cleanup
+* IPX code wiped out! let's decrease code
+* complexity for now, remember: I'm learning! :)
+* bps_to_speed_code OK
+* 1998/12/26 acme Minimal debug code cleanup
+* 1998/08/08 acme Initial version.
+*/
+
+#define CYCLOMX_X25_DEBUG 1
+
+#include /* return codes */
+#include /* ARPHRD_HWX25 */
+#include /* printk(), and other useful stuff */
+#include
+#include /* inline memset(), etc. */
+#include /* kmalloc(), kfree() */
+#include /* offsetof(), etc. */
+#include /* WAN router definitions */
+
+#include /* htons(), etc. */
+
+#include /* Cyclom 2X common user API definitions */
+#include /* X.25 firmware API definitions */
+
+#include
+
+/* Defines & Macros */
+#define CYCX_X25_MAX_CMD_RETRY 5
+#define CYCX_X25_CHAN_MTU 2048 /* unfragmented logical channel MTU */
+
+/* Data Structures */
+/* This is an extension of the 'struct net_device' we create for each network
+ interface to keep the rest of X.25 channel-specific data. */
+struct cycx_x25_channel {
+ /* This member must be first. */
+ struct net_device *slave; /* WAN slave */
+
+ char name[WAN_IFNAME_SZ+1]; /* interface name, ASCIIZ */
+ char addr[WAN_ADDRESS_SZ+1]; /* media address, ASCIIZ */
+ char *local_addr; /* local media address, ASCIIZ -
+ svc thru crossover cable */
+ s16 lcn; /* logical channel number/conn.req.key*/
+ u8 link;
+ struct timer_list timer; /* timer used for svc channel disc. */
+ u16 protocol; /* ethertype, 0 - multiplexed */
+ u8 svc; /* 0 - permanent, 1 - switched */
+ u8 state; /* channel state */
+ u8 drop_sequence; /* mark sequence for dropping */
+ u32 idle_tmout; /* sec, before disconnecting */
+ struct sk_buff *rx_skb; /* receive socket buffer */
+ struct cycx_device *card; /* -> owner */
+ struct net_device_stats ifstats;/* interface statistics */
+};
+
+/* Function Prototypes */
+/* WAN link driver entry points. These are called by the WAN router module. */
+static int cycx_wan_update(struct wan_device *wandev),
+ cycx_wan_new_if(struct wan_device *wandev, struct net_device *dev,
+ wanif_conf_t *conf),
+ cycx_wan_del_if(struct wan_device *wandev, struct net_device *dev);
+
+/* Network device interface */
+static int cycx_netdevice_init(struct net_device *dev),
+ cycx_netdevice_open(struct net_device *dev),
+ cycx_netdevice_stop(struct net_device *dev),
+ cycx_netdevice_hard_header(struct sk_buff *skb,
+ struct net_device *dev, u16 type,
+ void *daddr, void *saddr, unsigned len),
+ cycx_netdevice_rebuild_header(struct sk_buff *skb),
+ cycx_netdevice_hard_start_xmit(struct sk_buff *skb,
+ struct net_device *dev);
+
+static struct net_device_stats *
+ cycx_netdevice_get_stats(struct net_device *dev);
+
+/* Interrupt handlers */
+static void cycx_x25_irq_handler(struct cycx_device *card),
+ cycx_x25_irq_tx(struct cycx_device *card, struct cycx_x25_cmd *cmd),
+ cycx_x25_irq_rx(struct cycx_device *card, struct cycx_x25_cmd *cmd),
+ cycx_x25_irq_log(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd),
+ cycx_x25_irq_stat(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd),
+ cycx_x25_irq_connect_confirm(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd),
+ cycx_x25_irq_disconnect_confirm(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd),
+ cycx_x25_irq_connect(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd),
+ cycx_x25_irq_disconnect(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd),
+ cycx_x25_irq_spurious(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd);
+
+/* X.25 firmware interface functions */
+static int cycx_x25_configure(struct cycx_device *card,
+ struct cycx_x25_config *conf),
+ cycx_x25_get_stats(struct cycx_device *card),
+ cycx_x25_send(struct cycx_device *card, u8 link, u8 lcn, u8 bitm,
+ int len, void *buf),
+ cycx_x25_connect_response(struct cycx_device *card,
+ struct cycx_x25_channel *chan),
+ cycx_x25_disconnect_response(struct cycx_device *card, u8 link,
+ u8 lcn);
+
+/* channel functions */
+static int cycx_x25_chan_connect(struct net_device *dev),
+ cycx_x25_chan_send(struct net_device *dev, struct sk_buff *skb);
+
+static void cycx_x25_chan_disconnect(struct net_device *dev),
+ cycx_x25_chan_send_event(struct net_device *dev, u8 event);
+
+/* Miscellaneous functions */
+static void cycx_x25_set_chan_state(struct net_device *dev, u8 state),
+ cycx_x25_chan_timer(unsigned long d);
+
+static void nibble_to_byte(u8 *s, u8 *d, u8 len, u8 nibble),
+ reset_timer(struct net_device *dev);
+
+static u8 bps_to_speed_code(u32 bps);
+static u8 cycx_log2(u32 n);
+
+static unsigned dec_to_uint(u8 *str, int len);
+
+static struct net_device *cycx_x25_get_dev_by_lcn(struct wan_device *wandev,
+ s16 lcn);
+static struct net_device *
+ cycx_x25_get_dev_by_dte_addr(struct wan_device *wandev, char *dte);
+
+#ifdef CYCLOMX_X25_DEBUG
+static void hex_dump(char *msg, unsigned char *p, int len);
+static void cycx_x25_dump_config(struct cycx_x25_config *conf);
+static void cycx_x25_dump_stats(struct cycx_x25_stats *stats);
+static void cycx_x25_dump_devs(struct wan_device *wandev);
+#else
+#define hex_dump(msg, p, len)
+#define cycx_x25_dump_config(conf)
+#define cycx_x25_dump_stats(stats)
+#define cycx_x25_dump_devs(wandev)
+#endif
+/* Public Functions */
+
+/* X.25 Protocol Initialization routine.
+ *
+ * This routine is called by the main Cyclom 2X module during setup. At this
+ * point adapter is completely initialized and X.25 firmware is running.
+ * o configure adapter
+ * o initialize protocol-specific fields of the adapter data space.
+ *
+ * Return: 0 o.k.
+ * < 0 failure. */
+int cycx_x25_wan_init(struct cycx_device *card, wandev_conf_t *conf)
+{
+ struct cycx_x25_config cfg;
+
+ /* Verify configuration ID */
+ if (conf->config_id != WANCONFIG_X25) {
+ printk(KERN_INFO "%s: invalid configuration ID %u!\n",
+ card->devname, conf->config_id);
+ return -EINVAL;
+ }
+
+ /* Initialize protocol-specific fields */
+ card->mbox = card->hw.dpmbase + X25_MBOX_OFFS;
+ card->u.x.connection_keys = 0;
+ spin_lock_init(&card->u.x.lock);
+
+ /* Configure adapter. Here we set reasonable defaults, then parse
+ * device configuration structure and set configuration options.
+ * Most configuration options are verified and corrected (if
+ * necessary) since we can't rely on the adapter to do so and don't
+ * want it to fail either. */
+ memset(&cfg, 0, sizeof(cfg));
+ cfg.link = 0;
+ cfg.clock = conf->clocking == WANOPT_EXTERNAL ? 8 : 55;
+ cfg.speed = bps_to_speed_code(conf->bps);
+ cfg.n3win = 7;
+ cfg.n2win = 2;
+ cfg.n2 = 5;
+ cfg.nvc = 1;
+ cfg.npvc = 1;
+ cfg.flags = 0x02; /* default = V35 */
+ cfg.t1 = 10; /* line carrier timeout */
+ cfg.t2 = 29; /* tx timeout */
+ cfg.t21 = 180; /* CALL timeout */
+ cfg.t23 = 180; /* CLEAR timeout */
+
+ /* adjust MTU */
+ if (!conf->mtu || conf->mtu >= 512)
+ card->wandev.mtu = 512;
+ else if (conf->mtu >= 256)
+ card->wandev.mtu = 256;
+ else if (conf->mtu >= 128)
+ card->wandev.mtu = 128;
+ else
+ card->wandev.mtu = 64;
+
+ cfg.pktlen = cycx_log2(card->wandev.mtu);
+
+ if (conf->station == WANOPT_DTE) {
+ cfg.locaddr = 3; /* DTE */
+ cfg.remaddr = 1; /* DCE */
+ } else {
+ cfg.locaddr = 1; /* DCE */
+ cfg.remaddr = 3; /* DTE */
+ }
+
+ if (conf->interface == WANOPT_RS232)
+ cfg.flags = 0; /* FIXME just reset the 2nd bit */
+
+ if (conf->u.x25.hi_pvc) {
+ card->u.x.hi_pvc = min_t(unsigned int, conf->u.x25.hi_pvc, 4095);
+ card->u.x.lo_pvc = min_t(unsigned int, conf->u.x25.lo_pvc, card->u.x.hi_pvc);
+ }
+
+ if (conf->u.x25.hi_svc) {
+ card->u.x.hi_svc = min_t(unsigned int, conf->u.x25.hi_svc, 4095);
+ card->u.x.lo_svc = min_t(unsigned int, conf->u.x25.lo_svc, card->u.x.hi_svc);
+ }
+
+ if (card->u.x.lo_pvc == 255)
+ cfg.npvc = 0;
+ else
+ cfg.npvc = card->u.x.hi_pvc - card->u.x.lo_pvc + 1;
+
+ cfg.nvc = card->u.x.hi_svc - card->u.x.lo_svc + 1 + cfg.npvc;
+
+ if (conf->u.x25.hdlc_window)
+ cfg.n2win = min_t(unsigned int, conf->u.x25.hdlc_window, 7);
+
+ if (conf->u.x25.pkt_window)
+ cfg.n3win = min_t(unsigned int, conf->u.x25.pkt_window, 7);
+
+ if (conf->u.x25.t1)
+ cfg.t1 = min_t(unsigned int, conf->u.x25.t1, 30);
+
+ if (conf->u.x25.t2)
+ cfg.t2 = min_t(unsigned int, conf->u.x25.t2, 30);
+
+ if (conf->u.x25.t11_t21)
+ cfg.t21 = min_t(unsigned int, conf->u.x25.t11_t21, 30);
+
+ if (conf->u.x25.t13_t23)
+ cfg.t23 = min_t(unsigned int, conf->u.x25.t13_t23, 30);
+
+ if (conf->u.x25.n2)
+ cfg.n2 = min_t(unsigned int, conf->u.x25.n2, 30);
+
+ /* initialize adapter */
+ if (cycx_x25_configure(card, &cfg))
+ return -EIO;
+
+ /* Initialize protocol-specific fields of adapter data space */
+ card->wandev.bps = conf->bps;
+ card->wandev.interface = conf->interface;
+ card->wandev.clocking = conf->clocking;
+ card->wandev.station = conf->station;
+ card->isr = cycx_x25_irq_handler;
+ card->exec = NULL;
+ card->wandev.update = cycx_wan_update;
+ card->wandev.new_if = cycx_wan_new_if;
+ card->wandev.del_if = cycx_wan_del_if;
+ card->wandev.state = WAN_DISCONNECTED;
+
+ return 0;
+}
+
+/* WAN Device Driver Entry Points */
+/* Update device status & statistics. */
+static int cycx_wan_update(struct wan_device *wandev)
+{
+ /* sanity checks */
+ if (!wandev || !wandev->private)
+ return -EFAULT;
+
+ if (wandev->state == WAN_UNCONFIGURED)
+ return -ENODEV;
+
+ cycx_x25_get_stats(wandev->private);
+
+ return 0;
+}
+
+/* Create new logical channel.
+ * This routine is called by the router when ROUTER_IFNEW IOCTL is being
+ * handled.
+ * o parse media- and hardware-specific configuration
+ * o make sure that a new channel can be created
+ * o allocate resources, if necessary
+ * o prepare network device structure for registration.
+ *
+ * Return: 0 o.k.
+ * < 0 failure (channel will not be created) */
+static int cycx_wan_new_if(struct wan_device *wandev, struct net_device *dev,
+ wanif_conf_t *conf)
+{
+ struct cycx_device *card = wandev->private;
+ struct cycx_x25_channel *chan;
+ int err = 0;
+
+ if (!conf->name[0] || strlen(conf->name) > WAN_IFNAME_SZ) {
+ printk(KERN_INFO "%s: invalid interface name!\n",
+ card->devname);
+ return -EINVAL;
+ }
+
+ /* allocate and initialize private data */
+ chan = kmalloc(sizeof(struct cycx_x25_channel), GFP_KERNEL);
+ if (!chan)
+ return -ENOMEM;
+
+ memset(chan, 0, sizeof(*chan));
+ strcpy(chan->name, conf->name);
+ chan->card = card;
+ chan->link = conf->port;
+ chan->protocol = conf->protocol ? ETH_P_X25 : ETH_P_IP;
+ chan->rx_skb = NULL;
+ /* only used in svc connected thru crossover cable */
+ chan->local_addr = NULL;
+
+ if (conf->addr[0] == '@') { /* SVC */
+ int len = strlen(conf->local_addr);
+
+ if (len) {
+ if (len > WAN_ADDRESS_SZ) {
+ printk(KERN_ERR "%s: %s local addr too long!\n",
+ wandev->name, chan->name);
+ kfree(chan);
+ return -EINVAL;
+ } else {
+ chan->local_addr = kmalloc(len + 1, GFP_KERNEL);
+
+ if (!chan->local_addr) {
+ kfree(chan);
+ return -ENOMEM;
+ }
+ }
+
+ strncpy(chan->local_addr, conf->local_addr,
+ WAN_ADDRESS_SZ);
+ }
+
+ chan->svc = 1;
+ strncpy(chan->addr, &conf->addr[1], WAN_ADDRESS_SZ);
+ init_timer(&chan->timer);
+ chan->timer.function = cycx_x25_chan_timer;
+ chan->timer.data = (unsigned long)dev;
+
+ /* Set channel timeouts (default if not specified) */
+ chan->idle_tmout = conf->idle_timeout ? conf->idle_timeout : 90;
+ } else if (is_digit(conf->addr[0])) { /* PVC */
+ s16 lcn = dec_to_uint(conf->addr, 0);
+
+ if (lcn >= card->u.x.lo_pvc && lcn <= card->u.x.hi_pvc)
+ chan->lcn = lcn;
+ else {
+ printk(KERN_ERR
+ "%s: PVC %u is out of range on interface %s!\n",
+ wandev->name, lcn, chan->name);
+ err = -EINVAL;
+ }
+ } else {
+ printk(KERN_ERR "%s: invalid media address on interface %s!\n",
+ wandev->name, chan->name);
+ err = -EINVAL;
+ }
+
+ if (err) {
+ if (chan->local_addr)
+ kfree(chan->local_addr);
+
+ kfree(chan);
+ return err;
+ }
+
+ /* prepare network device data space for registration */
+ strcpy(dev->name, chan->name);
+ dev->init = cycx_netdevice_init;
+ dev->priv = chan;
+
+ return 0;
+}
+
+/* Delete logical channel. */
+static int cycx_wan_del_if(struct wan_device *wandev, struct net_device *dev)
+{
+ if (dev->priv) {
+ struct cycx_x25_channel *chan = dev->priv;
+
+ if (chan->svc) {
+ if (chan->local_addr)
+ kfree(chan->local_addr);
+
+ if (chan->state == WAN_CONNECTED)
+ del_timer(&chan->timer);
+ }
+
+ kfree(chan);
+ dev->priv = NULL;
+ }
+
+ return 0;
+}
+
+/* Network Device Interface */
+/* Initialize Linux network interface.
+ *
+ * This routine is called only once for each interface, during Linux network
+ * interface registration. Returning anything but zero will fail interface
+ * registration. */
+static int cycx_netdevice_init(struct net_device *dev)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+ struct cycx_device *card = chan->card;
+ struct wan_device *wandev = &card->wandev;
+
+ /* Initialize device driver entry points */
+ dev->open = cycx_netdevice_open;
+ dev->stop = cycx_netdevice_stop;
+ dev->hard_header = cycx_netdevice_hard_header;
+ dev->rebuild_header = cycx_netdevice_rebuild_header;
+ dev->hard_start_xmit = cycx_netdevice_hard_start_xmit;
+ dev->get_stats = cycx_netdevice_get_stats;
+
+ /* Initialize media-specific parameters */
+ dev->mtu = CYCX_X25_CHAN_MTU;
+ dev->type = ARPHRD_HWX25; /* ARP h/w type */
+ dev->hard_header_len = 0; /* media header length */
+ dev->addr_len = 0; /* hardware address length */
+
+ if (!chan->svc)
+ *(u16*)dev->dev_addr = htons(chan->lcn);
+
+ /* Initialize hardware parameters (just for reference) */
+ dev->irq = wandev->irq;
+ dev->dma = wandev->dma;
+ dev->base_addr = wandev->ioport;
+ dev->mem_start = (unsigned long)wandev->maddr;
+ dev->mem_end = (unsigned long)(wandev->maddr +
+ wandev->msize - 1);
+ dev->flags |= IFF_NOARP;
+
+ /* Set transmit buffer queue length */
+ dev->tx_queue_len = 10;
+ SET_MODULE_OWNER(dev);
+
+ /* Initialize socket buffers */
+ cycx_x25_set_chan_state(dev, WAN_DISCONNECTED);
+
+ return 0;
+}
+
+/* Open network interface.
+ * o prevent module from unloading by incrementing use count
+ * o if link is disconnected then initiate connection
+ *
+ * Return 0 if O.k. or errno. */
+static int cycx_netdevice_open(struct net_device *dev)
+{
+ if (netif_running(dev))
+ return -EBUSY; /* only one open is allowed */
+
+ netif_start_queue(dev);
+ return 0;
+}
+
+/* Close network interface.
+ * o reset flags.
+ * o if there's no more open channels then disconnect physical link. */
+static int cycx_netdevice_stop(struct net_device *dev)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+
+ netif_stop_queue(dev);
+
+ if (chan->state == WAN_CONNECTED || chan->state == WAN_CONNECTING)
+ cycx_x25_chan_disconnect(dev);
+
+ return 0;
+}
+
+/* Build media header.
+ * o encapsulate packet according to encapsulation type.
+ *
+ * The trick here is to put packet type (Ethertype) into 'protocol' field of
+ * the socket buffer, so that we don't forget it. If encapsulation fails,
+ * set skb->protocol to 0 and discard packet later.
+ *
+ * Return: media header length. */
+static int cycx_netdevice_hard_header(struct sk_buff *skb,
+ struct net_device *dev, u16 type,
+ void *daddr, void *saddr, unsigned len)
+{
+ skb->protocol = type;
+
+ return dev->hard_header_len;
+}
+
+/* * Re-build media header.
+ * Return: 1 physical address resolved.
+ * 0 physical address not resolved */
+static int cycx_netdevice_rebuild_header(struct sk_buff *skb)
+{
+ return 1;
+}
+
+/* Send a packet on a network interface.
+ * o set busy flag (marks start of the transmission).
+ * o check link state. If link is not up, then drop the packet.
+ * o check channel status. If it's down then initiate a call.
+ * o pass a packet to corresponding WAN device.
+ * o free socket buffer
+ *
+ * Return: 0 complete (socket buffer must be freed)
+ * non-0 packet may be re-transmitted (tbusy must be set)
+ *
+ * Notes:
+ * 1. This routine is called either by the protocol stack or by the "net
+ * bottom half" (with interrupts enabled).
+ * 2. Setting tbusy flag will inhibit further transmit requests from the
+ * protocol stack and can be used for flow control with protocol layer. */
+static int cycx_netdevice_hard_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+ struct cycx_device *card = chan->card;
+
+ if (!chan->svc)
+ chan->protocol = skb->protocol;
+
+ if (card->wandev.state != WAN_CONNECTED)
+ ++chan->ifstats.tx_dropped;
+ else if (chan->svc && chan->protocol &&
+ chan->protocol != skb->protocol) {
+ printk(KERN_INFO
+ "%s: unsupported Ethertype 0x%04X on interface %s!\n",
+ card->devname, skb->protocol, dev->name);
+ ++chan->ifstats.tx_errors;
+ } else if (chan->protocol == ETH_P_IP) {
+ switch (chan->state) {
+ case WAN_DISCONNECTED:
+ if (cycx_x25_chan_connect(dev)) {
+ netif_stop_queue(dev);
+ return -EBUSY;
+ }
+ /* fall thru */
+ case WAN_CONNECTED:
+ reset_timer(dev);
+ dev->trans_start = jiffies;
+ netif_stop_queue(dev);
+
+ if (cycx_x25_chan_send(dev, skb))
+ return -EBUSY;
+
+ break;
+ default:
+ ++chan->ifstats.tx_dropped;
+ ++card->wandev.stats.tx_dropped;
+ }
+ } else { /* chan->protocol == ETH_P_X25 */
+ switch (skb->data[0]) {
+ case 0: break;
+ case 1: /* Connect request */
+ cycx_x25_chan_connect(dev);
+ goto free_packet;
+ case 2: /* Disconnect request */
+ cycx_x25_chan_disconnect(dev);
+ goto free_packet;
+ default:
+ printk(KERN_INFO
+ "%s: unknown %d x25-iface request on %s!\n",
+ card->devname, skb->data[0], dev->name);
+ ++chan->ifstats.tx_errors;
+ goto free_packet;
+ }
+
+ skb_pull(skb, 1); /* Remove control byte */
+ reset_timer(dev);
+ dev->trans_start = jiffies;
+ netif_stop_queue(dev);
+
+ if (cycx_x25_chan_send(dev, skb)) {
+ /* prepare for future retransmissions */
+ skb_push(skb, 1);
+ return -EBUSY;
+ }
+ }
+
+free_packet:
+ dev_kfree_skb(skb);
+
+ return 0;
+}
+
+/* Get Ethernet-style interface statistics.
+ * Return a pointer to struct net_device_stats */
+static struct net_device_stats *cycx_netdevice_get_stats(struct net_device *dev)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+
+ return chan ? &chan->ifstats : NULL;
+}
+
+/* Interrupt Handlers */
+/* X.25 Interrupt Service Routine. */
+static void cycx_x25_irq_handler(struct cycx_device *card)
+{
+ struct cycx_x25_cmd cmd;
+ u16 z = 0;
+
+ card->in_isr = 1;
+ card->buff_int_mode_unbusy = 0;
+ cycx_peek(&card->hw, X25_RXMBOX_OFFS, &cmd, sizeof(cmd));
+
+ switch (cmd.command) {
+ case X25_DATA_INDICATION:
+ cycx_x25_irq_rx(card, &cmd);
+ break;
+ case X25_ACK_FROM_VC:
+ cycx_x25_irq_tx(card, &cmd);
+ break;
+ case X25_LOG:
+ cycx_x25_irq_log(card, &cmd);
+ break;
+ case X25_STATISTIC:
+ cycx_x25_irq_stat(card, &cmd);
+ break;
+ case X25_CONNECT_CONFIRM:
+ cycx_x25_irq_connect_confirm(card, &cmd);
+ break;
+ case X25_CONNECT_INDICATION:
+ cycx_x25_irq_connect(card, &cmd);
+ break;
+ case X25_DISCONNECT_INDICATION:
+ cycx_x25_irq_disconnect(card, &cmd);
+ break;
+ case X25_DISCONNECT_CONFIRM:
+ cycx_x25_irq_disconnect_confirm(card, &cmd);
+ break;
+ case X25_LINE_ON:
+ cycx_set_state(card, WAN_CONNECTED);
+ break;
+ case X25_LINE_OFF:
+ cycx_set_state(card, WAN_DISCONNECTED);
+ break;
+ default:
+ cycx_x25_irq_spurious(card, &cmd);
+ break;
+ }
+
+ cycx_poke(&card->hw, 0, &z, sizeof(z));
+ cycx_poke(&card->hw, X25_RXMBOX_OFFS, &z, sizeof(z));
+ card->in_isr = 0;
+}
+
+/* Transmit interrupt handler.
+ * o Release socket buffer
+ * o Clear 'tbusy' flag */
+static void cycx_x25_irq_tx(struct cycx_device *card, struct cycx_x25_cmd *cmd)
+{
+ struct net_device *dev;
+ struct wan_device *wandev = &card->wandev;
+ u8 lcn;
+
+ cycx_peek(&card->hw, cmd->buf, &lcn, sizeof(lcn));
+
+ /* unbusy device and then dev_tint(); */
+ dev = cycx_x25_get_dev_by_lcn(wandev, lcn);
+ if (dev) {
+ card->buff_int_mode_unbusy = 1;
+ netif_wake_queue(dev);
+ } else
+ printk(KERN_ERR "%s:ackvc for inexistent lcn %d\n",
+ card->devname, lcn);
+}
+
+/* Receive interrupt handler.
+ * This routine handles fragmented IP packets using M-bit according to the
+ * RFC1356.
+ * o map logical channel number to network interface.
+ * o allocate socket buffer or append received packet to the existing one.
+ * o if M-bit is reset (i.e. it's the last packet in a sequence) then
+ * decapsulate packet and pass socket buffer to the protocol stack.
+ *
+ * Notes:
+ * 1. When allocating a socket buffer, if M-bit is set then more data is
+ * coming and we have to allocate buffer for the maximum IP packet size
+ * expected on this channel.
+ * 2. If something goes wrong and X.25 packet has to be dropped (e.g. no
+ * socket buffers available) the whole packet sequence must be discarded. */
+static void cycx_x25_irq_rx(struct cycx_device *card, struct cycx_x25_cmd *cmd)
+{
+ struct wan_device *wandev = &card->wandev;
+ struct net_device *dev;
+ struct cycx_x25_channel *chan;
+ struct sk_buff *skb;
+ u8 bitm, lcn;
+ int pktlen = cmd->len - 5;
+
+ cycx_peek(&card->hw, cmd->buf, &lcn, sizeof(lcn));
+ cycx_peek(&card->hw, cmd->buf + 4, &bitm, sizeof(bitm));
+ bitm &= 0x10;
+
+ dev = cycx_x25_get_dev_by_lcn(wandev, lcn);
+ if (!dev) {
+ /* Invalid channel, discard packet */
+ printk(KERN_INFO "%s: receiving on orphaned LCN %d!\n",
+ card->devname, lcn);
+ return;
+ }
+
+ chan = dev->priv;
+ reset_timer(dev);
+
+ if (chan->drop_sequence) {
+ if (!bitm)
+ chan->drop_sequence = 0;
+ else
+ return;
+ }
+
+ if ((skb = chan->rx_skb) == NULL) {
+ /* Allocate new socket buffer */
+ int bufsize = bitm ? dev->mtu : pktlen;
+
+ if ((skb = dev_alloc_skb((chan->protocol == ETH_P_X25 ? 1 : 0) +
+ bufsize +
+ dev->hard_header_len)) == NULL) {
+ printk(KERN_INFO "%s: no socket buffers available!\n",
+ card->devname);
+ chan->drop_sequence = 1;
+ ++chan->ifstats.rx_dropped;
+ return;
+ }
+
+ if (chan->protocol == ETH_P_X25) /* X.25 socket layer control */
+ /* 0 = data packet (dev_alloc_skb zeroed skb->data) */
+ skb_put(skb, 1);
+
+ skb->dev = dev;
+ skb->protocol = htons(chan->protocol);
+ chan->rx_skb = skb;
+ }
+
+ if (skb_tailroom(skb) < pktlen) {
+ /* No room for the packet. Call off the whole thing! */
+ dev_kfree_skb_irq(skb);
+ chan->rx_skb = NULL;
+
+ if (bitm)
+ chan->drop_sequence = 1;
+
+ printk(KERN_INFO "%s: unexpectedly long packet sequence "
+ "on interface %s!\n", card->devname, dev->name);
+ ++chan->ifstats.rx_length_errors;
+ return;
+ }
+
+ /* Append packet to the socket buffer */
+ cycx_peek(&card->hw, cmd->buf + 5, skb_put(skb, pktlen), pktlen);
+
+ if (bitm)
+ return; /* more data is coming */
+
+ chan->rx_skb = NULL; /* dequeue packet */
+
+ ++chan->ifstats.rx_packets;
+ chan->ifstats.rx_bytes += pktlen;
+
+ skb->mac.raw = skb->data;
+ netif_rx(skb);
+ dev->last_rx = jiffies; /* timestamp */
+}
+
+/* Connect interrupt handler. */
+static void cycx_x25_irq_connect(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd)
+{
+ struct wan_device *wandev = &card->wandev;
+ struct net_device *dev = NULL;
+ struct cycx_x25_channel *chan;
+ u8 d[32],
+ loc[24],
+ rem[24];
+ u8 lcn, sizeloc, sizerem;
+
+ cycx_peek(&card->hw, cmd->buf, &lcn, sizeof(lcn));
+ cycx_peek(&card->hw, cmd->buf + 5, &sizeloc, sizeof(sizeloc));
+ cycx_peek(&card->hw, cmd->buf + 6, d, cmd->len - 6);
+
+ sizerem = sizeloc >> 4;
+ sizeloc &= 0x0F;
+
+ loc[0] = rem[0] = '\0';
+
+ if (sizeloc)
+ nibble_to_byte(d, loc, sizeloc, 0);
+
+ if (sizerem)
+ nibble_to_byte(d + (sizeloc >> 1), rem, sizerem, sizeloc & 1);
+
+ dprintk(1, KERN_INFO "%s:lcn=%d, local=%s, remote=%s\n",
+ __FUNCTION__, lcn, loc, rem);
+
+ dev = cycx_x25_get_dev_by_dte_addr(wandev, rem);
+ if (!dev) {
+ /* Invalid channel, discard packet */
+ printk(KERN_INFO "%s: connect not expected: remote %s!\n",
+ card->devname, rem);
+ return;
+ }
+
+ chan = dev->priv;
+ chan->lcn = lcn;
+ cycx_x25_connect_response(card, chan);
+ cycx_x25_set_chan_state(dev, WAN_CONNECTED);
+}
+
+/* Connect confirm interrupt handler. */
+static void cycx_x25_irq_connect_confirm(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd)
+{
+ struct wan_device *wandev = &card->wandev;
+ struct net_device *dev;
+ struct cycx_x25_channel *chan;
+ u8 lcn, key;
+
+ cycx_peek(&card->hw, cmd->buf, &lcn, sizeof(lcn));
+ cycx_peek(&card->hw, cmd->buf + 1, &key, sizeof(key));
+ dprintk(1, KERN_INFO "%s: %s:lcn=%d, key=%d\n",
+ card->devname, __FUNCTION__, lcn, key);
+
+ dev = cycx_x25_get_dev_by_lcn(wandev, -key);
+ if (!dev) {
+ /* Invalid channel, discard packet */
+ clear_bit(--key, (void*)&card->u.x.connection_keys);
+ printk(KERN_INFO "%s: connect confirm not expected: lcn %d, "
+ "key=%d!\n", card->devname, lcn, key);
+ return;
+ }
+
+ clear_bit(--key, (void*)&card->u.x.connection_keys);
+ chan = dev->priv;
+ chan->lcn = lcn;
+ cycx_x25_set_chan_state(dev, WAN_CONNECTED);
+}
+
+/* Disconnect confirm interrupt handler. */
+static void cycx_x25_irq_disconnect_confirm(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd)
+{
+ struct wan_device *wandev = &card->wandev;
+ struct net_device *dev;
+ u8 lcn;
+
+ cycx_peek(&card->hw, cmd->buf, &lcn, sizeof(lcn));
+ dprintk(1, KERN_INFO "%s: %s:lcn=%d\n",
+ card->devname, __FUNCTION__, lcn);
+ dev = cycx_x25_get_dev_by_lcn(wandev, lcn);
+ if (!dev) {
+ /* Invalid channel, discard packet */
+ printk(KERN_INFO "%s:disconnect confirm not expected!:lcn %d\n",
+ card->devname, lcn);
+ return;
+ }
+
+ cycx_x25_set_chan_state(dev, WAN_DISCONNECTED);
+}
+
+/* disconnect interrupt handler. */
+static void cycx_x25_irq_disconnect(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd)
+{
+ struct wan_device *wandev = &card->wandev;
+ struct net_device *dev;
+ u8 lcn;
+
+ cycx_peek(&card->hw, cmd->buf, &lcn, sizeof(lcn));
+ dprintk(1, KERN_INFO "%s:lcn=%d\n", __FUNCTION__, lcn);
+
+ dev = cycx_x25_get_dev_by_lcn(wandev, lcn);
+ if (dev) {
+ struct cycx_x25_channel *chan = dev->priv;
+
+ cycx_x25_disconnect_response(card, chan->link, lcn);
+ cycx_x25_set_chan_state(dev, WAN_DISCONNECTED);
+ } else
+ cycx_x25_disconnect_response(card, 0, lcn);
+}
+
+/* LOG interrupt handler. */
+static void cycx_x25_irq_log(struct cycx_device *card, struct cycx_x25_cmd *cmd)
+{
+#if CYCLOMX_X25_DEBUG
+ char bf[20];
+ u16 size, toread, link, msg_code;
+ u8 code, routine;
+
+ cycx_peek(&card->hw, cmd->buf, &msg_code, sizeof(msg_code));
+ cycx_peek(&card->hw, cmd->buf + 2, &link, sizeof(link));
+ cycx_peek(&card->hw, cmd->buf + 4, &size, sizeof(size));
+ /* at most 20 bytes are available... thanks to Daniela :) */
+ toread = size < 20 ? size : 20;
+ cycx_peek(&card->hw, cmd->buf + 10, &bf, toread);
+ cycx_peek(&card->hw, cmd->buf + 10 + toread, &code, 1);
+ cycx_peek(&card->hw, cmd->buf + 10 + toread + 1, &routine, 1);
+
+ printk(KERN_INFO "cycx_x25_irq_handler: X25_LOG (0x4500) indic.:\n");
+ printk(KERN_INFO "cmd->buf=0x%X\n", cmd->buf);
+ printk(KERN_INFO "Log message code=0x%X\n", msg_code);
+ printk(KERN_INFO "Link=%d\n", link);
+ printk(KERN_INFO "log code=0x%X\n", code);
+ printk(KERN_INFO "log routine=0x%X\n", routine);
+ printk(KERN_INFO "Message size=%d\n", size);
+ hex_dump("Message", bf, toread);
+#endif
+}
+
+/* STATISTIC interrupt handler. */
+static void cycx_x25_irq_stat(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd)
+{
+ cycx_peek(&card->hw, cmd->buf, &card->u.x.stats,
+ sizeof(card->u.x.stats));
+ hex_dump("cycx_x25_irq_stat", (unsigned char*)&card->u.x.stats,
+ sizeof(card->u.x.stats));
+ cycx_x25_dump_stats(&card->u.x.stats);
+ wake_up_interruptible(&card->wait_stats);
+}
+
+/* Spurious interrupt handler.
+ * o print a warning
+ * If number of spurious interrupts exceeded some limit, then ??? */
+static void cycx_x25_irq_spurious(struct cycx_device *card,
+ struct cycx_x25_cmd *cmd)
+{
+ printk(KERN_INFO "%s: spurious interrupt (0x%X)!\n",
+ card->devname, cmd->command);
+}
+#ifdef CYCLOMX_X25_DEBUG
+static void hex_dump(char *msg, unsigned char *p, int len)
+{
+ unsigned char hex[1024],
+ * phex = hex;
+
+ if (len >= (sizeof(hex) / 2))
+ len = (sizeof(hex) / 2) - 1;
+
+ while (len--) {
+ sprintf(phex, "%02x", *p++);
+ phex += 2;
+ }
+
+ printk(KERN_INFO "%s: %s\n", msg, hex);
+}
+#endif
+
+/* Cyclom 2X Firmware-Specific Functions */
+/* Exec X.25 command. */
+static int x25_exec(struct cycx_device *card, int command, int link,
+ void *d1, int len1, void *d2, int len2)
+{
+ struct cycx_x25_cmd c;
+ unsigned long flags;
+ u32 addr = 0x1200 + 0x2E0 * link + 0x1E2;
+ u8 retry = CYCX_X25_MAX_CMD_RETRY;
+ int err = 0;
+
+ c.command = command;
+ c.link = link;
+ c.len = len1 + len2;
+
+ spin_lock_irqsave(&card->u.x.lock, flags);
+
+ /* write command */
+ cycx_poke(&card->hw, X25_MBOX_OFFS, &c, sizeof(c) - sizeof(c.buf));
+
+ /* write X.25 data */
+ if (d1) {
+ cycx_poke(&card->hw, addr, d1, len1);
+
+ if (d2) {
+ if (len2 > 254) {
+ u32 addr1 = 0xA00 + 0x400 * link;
+
+ cycx_poke(&card->hw, addr + len1, d2, 249);
+ cycx_poke(&card->hw, addr1, ((u8*)d2) + 249,
+ len2 - 249);
+ } else
+ cycx_poke(&card->hw, addr + len1, d2, len2);
+ }
+ }
+
+ /* generate interruption, executing command */
+ cycx_intr(&card->hw);
+
+ /* wait till card->mbox == 0 */
+ do {
+ err = cycx_exec(card->mbox);
+ } while (retry-- && err);
+
+ spin_unlock_irqrestore(&card->u.x.lock, flags);
+
+ return err;
+}
+
+/* Configure adapter. */
+static int cycx_x25_configure(struct cycx_device *card,
+ struct cycx_x25_config *conf)
+{
+ struct {
+ u16 nlinks;
+ struct cycx_x25_config conf[2];
+ } x25_cmd_conf;
+
+ memset(&x25_cmd_conf, 0, sizeof(x25_cmd_conf));
+ x25_cmd_conf.nlinks = 2;
+ x25_cmd_conf.conf[0] = *conf;
+ /* FIXME: we need to find a way in the wanrouter framework
+ to configure the second link, for now lets use it
+ with the same config from the first link, fixing
+ the interface type to RS232, the speed in 38400 and
+ the clock to external */
+ x25_cmd_conf.conf[1] = *conf;
+ x25_cmd_conf.conf[1].link = 1;
+ x25_cmd_conf.conf[1].speed = 5; /* 38400 */
+ x25_cmd_conf.conf[1].clock = 8;
+ x25_cmd_conf.conf[1].flags = 0; /* default = RS232 */
+
+ cycx_x25_dump_config(&x25_cmd_conf.conf[0]);
+ cycx_x25_dump_config(&x25_cmd_conf.conf[1]);
+
+ return x25_exec(card, X25_CONFIG, 0,
+ &x25_cmd_conf, sizeof(x25_cmd_conf), NULL, 0);
+}
+
+/* Get protocol statistics. */
+static int cycx_x25_get_stats(struct cycx_device *card)
+{
+ /* the firmware expects 20 in the size field!!!
+ thanks to Daniela */
+ int err = x25_exec(card, X25_STATISTIC, 0, NULL, 20, NULL, 0);
+
+ if (err)
+ return err;
+
+ interruptible_sleep_on(&card->wait_stats);
+
+ if (signal_pending(current))
+ return -EINTR;
+
+ card->wandev.stats.rx_packets = card->u.x.stats.n2_rx_frames;
+ card->wandev.stats.rx_over_errors = card->u.x.stats.rx_over_errors;
+ card->wandev.stats.rx_crc_errors = card->u.x.stats.rx_crc_errors;
+ card->wandev.stats.rx_length_errors = 0; /* not available from fw */
+ card->wandev.stats.rx_frame_errors = 0; /* not available from fw */
+ card->wandev.stats.rx_missed_errors = card->u.x.stats.rx_aborts;
+ card->wandev.stats.rx_dropped = 0; /* not available from fw */
+ card->wandev.stats.rx_errors = 0; /* not available from fw */
+ card->wandev.stats.tx_packets = card->u.x.stats.n2_tx_frames;
+ card->wandev.stats.tx_aborted_errors = card->u.x.stats.tx_aborts;
+ card->wandev.stats.tx_dropped = 0; /* not available from fw */
+ card->wandev.stats.collisions = 0; /* not available from fw */
+ card->wandev.stats.tx_errors = 0; /* not available from fw */
+
+ cycx_x25_dump_devs(&card->wandev);
+
+ return 0;
+}
+
+/* return the number of nibbles */
+static int byte_to_nibble(u8 *s, u8 *d, char *nibble)
+{
+ int i = 0;
+
+ if (*nibble && *s) {
+ d[i] |= *s++ - '0';
+ *nibble = 0;
+ ++i;
+ }
+
+ while (*s) {
+ d[i] = (*s - '0') << 4;
+ if (*(s + 1))
+ d[i] |= *(s + 1) - '0';
+ else {
+ *nibble = 1;
+ break;
+ }
+ ++i;
+ s += 2;
+ }
+
+ return i;
+}
+
+static void nibble_to_byte(u8 *s, u8 *d, u8 len, u8 nibble)
+{
+ if (nibble) {
+ *d++ = '0' + (*s++ & 0x0F);
+ --len;
+ }
+
+ while (len) {
+ *d++ = '0' + (*s >> 4);
+
+ if (--len) {
+ *d++ = '0' + (*s & 0x0F);
+ --len;
+ } else break;
+
+ ++s;
+ }
+
+ *d = '\0';
+}
+
+/* Place X.25 call. */
+static int x25_place_call(struct cycx_device *card,
+ struct cycx_x25_channel *chan)
+{
+ int err = 0,
+ len;
+ char d[64],
+ nibble = 0,
+ mylen = chan->local_addr ? strlen(chan->local_addr) : 0,
+ remotelen = strlen(chan->addr);
+ u8 key;
+
+ if (card->u.x.connection_keys == ~0U) {
+ printk(KERN_INFO "%s: too many simultaneous connection "
+ "requests!\n", card->devname);
+ return -EAGAIN;
+ }
+
+ key = ffz(card->u.x.connection_keys);
+ set_bit(key, (void*)&card->u.x.connection_keys);
+ ++key;
+ dprintk(1, KERN_INFO "%s:x25_place_call:key=%d\n", card->devname, key);
+ memset(d, 0, sizeof(d));
+ d[1] = key; /* user key */
+ d[2] = 0x10;
+ d[4] = 0x0B;
+
+ len = byte_to_nibble(chan->addr, d + 6, &nibble);
+
+ if (chan->local_addr)
+ len += byte_to_nibble(chan->local_addr, d + 6 + len, &nibble);
+
+ if (nibble)
+ ++len;
+
+ d[5] = mylen << 4 | remotelen;
+ d[6 + len + 1] = 0xCC; /* TCP/IP over X.25, thanks to Daniela :) */
+
+ if ((err = x25_exec(card, X25_CONNECT_REQUEST, chan->link,
+ &d, 7 + len + 1, NULL, 0)) != 0)
+ clear_bit(--key, (void*)&card->u.x.connection_keys);
+ else
+ chan->lcn = -key;
+
+ return err;
+}
+
+/* Place X.25 CONNECT RESPONSE. */
+static int cycx_x25_connect_response(struct cycx_device *card,
+ struct cycx_x25_channel *chan)
+{
+ u8 d[8];
+
+ memset(d, 0, sizeof(d));
+ d[0] = d[3] = chan->lcn;
+ d[2] = 0x10;
+ d[4] = 0x0F;
+ d[7] = 0xCC; /* TCP/IP over X.25, thanks Daniela */
+
+ return x25_exec(card, X25_CONNECT_RESPONSE, chan->link, &d, 8, NULL, 0);
+}
+
+/* Place X.25 DISCONNECT RESPONSE. */
+static int cycx_x25_disconnect_response(struct cycx_device *card, u8 link,
+ u8 lcn)
+{
+ char d[5];
+
+ memset(d, 0, sizeof(d));
+ d[0] = d[3] = lcn;
+ d[2] = 0x10;
+ d[4] = 0x17;
+
+ return x25_exec(card, X25_DISCONNECT_RESPONSE, link, &d, 5, NULL, 0);
+}
+
+/* Clear X.25 call. */
+static int x25_clear_call(struct cycx_device *card, u8 link, u8 lcn, u8 cause,
+ u8 diagn)
+{
+ u8 d[7];
+
+ memset(d, 0, sizeof(d));
+ d[0] = d[3] = lcn;
+ d[2] = 0x10;
+ d[4] = 0x13;
+ d[5] = cause;
+ d[6] = diagn;
+
+ return x25_exec(card, X25_DISCONNECT_REQUEST, link, d, 7, NULL, 0);
+}
+
+/* Send X.25 data packet. */
+static int cycx_x25_send(struct cycx_device *card, u8 link, u8 lcn, u8 bitm,
+ int len, void *buf)
+{
+ u8 d[] = "?\xFF\x10??";
+
+ d[0] = d[3] = lcn;
+ d[4] = bitm;
+
+ return x25_exec(card, X25_DATA_REQUEST, link, &d, 5, buf, len);
+}
+
+/* Miscellaneous */
+/* Find network device by its channel number. */
+static struct net_device *cycx_x25_get_dev_by_lcn(struct wan_device *wandev,
+ s16 lcn)
+{
+ struct net_device *dev = wandev->dev;
+ struct cycx_x25_channel *chan;
+
+ while (dev) {
+ chan = (struct cycx_x25_channel*)dev->priv;
+
+ if (chan->lcn == lcn)
+ break;
+ dev = chan->slave;
+ }
+ return dev;
+}
+
+/* Find network device by its remote dte address. */
+static struct net_device *
+ cycx_x25_get_dev_by_dte_addr(struct wan_device *wandev, char *dte)
+{
+ struct net_device *dev = wandev->dev;
+ struct cycx_x25_channel *chan;
+
+ while (dev) {
+ chan = (struct cycx_x25_channel*)dev->priv;
+
+ if (!strcmp(chan->addr, dte))
+ break;
+ dev = chan->slave;
+ }
+ return dev;
+}
+
+/* Initiate connection on the logical channel.
+ * o for PVC we just get channel configuration
+ * o for SVCs place an X.25 call
+ *
+ * Return: 0 connected
+ * >0 connection in progress
+ * <0 failure */
+static int cycx_x25_chan_connect(struct net_device *dev)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+ struct cycx_device *card = chan->card;
+
+ if (chan->svc) {
+ if (!chan->addr[0])
+ return -EINVAL; /* no destination address */
+
+ dprintk(1, KERN_INFO "%s: placing X.25 call to %s...\n",
+ card->devname, chan->addr);
+
+ if (x25_place_call(card, chan))
+ return -EIO;
+
+ cycx_x25_set_chan_state(dev, WAN_CONNECTING);
+ return 1;
+ } else
+ cycx_x25_set_chan_state(dev, WAN_CONNECTED);
+
+ return 0;
+}
+
+/* Disconnect logical channel.
+ * o if SVC then clear X.25 call */
+static void cycx_x25_chan_disconnect(struct net_device *dev)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+
+ if (chan->svc) {
+ x25_clear_call(chan->card, chan->link, chan->lcn, 0, 0);
+ cycx_x25_set_chan_state(dev, WAN_DISCONNECTING);
+ } else
+ cycx_x25_set_chan_state(dev, WAN_DISCONNECTED);
+}
+
+/* Called by kernel timer */
+static void cycx_x25_chan_timer(unsigned long d)
+{
+ struct net_device *dev = (struct net_device *)d;
+ struct cycx_x25_channel *chan = dev->priv;
+
+ if (chan->state == WAN_CONNECTED)
+ cycx_x25_chan_disconnect(dev);
+ else
+ printk(KERN_ERR "%s: %s for svc (%s) not connected!\n",
+ chan->card->devname, __FUNCTION__, dev->name);
+}
+
+/* Set logical channel state. */
+static void cycx_x25_set_chan_state(struct net_device *dev, u8 state)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+ struct cycx_device *card = chan->card;
+ unsigned long flags;
+ char *string_state = NULL;
+
+ spin_lock_irqsave(&card->lock, flags);
+
+ if (chan->state != state) {
+ if (chan->svc && chan->state == WAN_CONNECTED)
+ del_timer(&chan->timer);
+
+ switch (state) {
+ case WAN_CONNECTED:
+ string_state = "connected!";
+ *(u16*)dev->dev_addr = htons(chan->lcn);
+ netif_wake_queue(dev);
+ reset_timer(dev);
+
+ if (chan->protocol == ETH_P_X25)
+ cycx_x25_chan_send_event(dev, 1);
+
+ break;
+ case WAN_CONNECTING:
+ string_state = "connecting...";
+ break;
+ case WAN_DISCONNECTING:
+ string_state = "disconnecting...";
+ break;
+ case WAN_DISCONNECTED:
+ string_state = "disconnected!";
+
+ if (chan->svc) {
+ *(unsigned short*)dev->dev_addr = 0;
+ chan->lcn = 0;
+ }
+
+ if (chan->protocol == ETH_P_X25)
+ cycx_x25_chan_send_event(dev, 2);
+
+ netif_wake_queue(dev);
+ break;
+ }
+
+ printk(KERN_INFO "%s: interface %s %s\n", card->devname,
+ dev->name, string_state);
+ chan->state = state;
+ }
+
+ spin_unlock_irqrestore(&card->lock, flags);
+}
+
+/* Send packet on a logical channel.
+ * When this function is called, tx_skb field of the channel data space
+ * points to the transmit socket buffer. When transmission is complete,
+ * release socket buffer and reset 'tbusy' flag.
+ *
+ * Return: 0 - transmission complete
+ * 1 - busy
+ *
+ * Notes:
+ * 1. If packet length is greater than MTU for this channel, we'll fragment
+ * the packet into 'complete sequence' using M-bit.
+ * 2. When transmission is complete, an event notification should be issued
+ * to the router. */
+static int cycx_x25_chan_send(struct net_device *dev, struct sk_buff *skb)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+ struct cycx_device *card = chan->card;
+ int bitm = 0; /* final packet */
+ unsigned len = skb->len;
+
+ if (skb->len > card->wandev.mtu) {
+ len = card->wandev.mtu;
+ bitm = 0x10; /* set M-bit (more data) */
+ }
+
+ if (cycx_x25_send(card, chan->link, chan->lcn, bitm, len, skb->data))
+ return 1;
+
+ if (bitm) {
+ skb_pull(skb, len);
+ return 1;
+ }
+
+ ++chan->ifstats.tx_packets;
+ chan->ifstats.tx_bytes += len;
+
+ return 0;
+}
+
+/* Send event (connection, disconnection, etc) to X.25 socket layer */
+
+static void cycx_x25_chan_send_event(struct net_device *dev, u8 event)
+{
+ struct sk_buff *skb;
+ unsigned char *ptr;
+
+ if ((skb = dev_alloc_skb(1)) == NULL) {
+ printk(KERN_ERR "%s: out of memory\n", __FUNCTION__);
+ return;
+ }
+
+ ptr = skb_put(skb, 1);
+ *ptr = event;
+
+ skb->protocol = x25_type_trans(skb, dev);
+ netif_rx(skb);
+ dev->last_rx = jiffies; /* timestamp */
+}
+
+/* Convert line speed in bps to a number used by cyclom 2x code. */
+static u8 bps_to_speed_code(u32 bps)
+{
+ u8 number = 0; /* defaults to the lowest (1200) speed ;> */
+
+ if (bps >= 512000) number = 8;
+ else if (bps >= 256000) number = 7;
+ else if (bps >= 64000) number = 6;
+ else if (bps >= 38400) number = 5;
+ else if (bps >= 19200) number = 4;
+ else if (bps >= 9600) number = 3;
+ else if (bps >= 4800) number = 2;
+ else if (bps >= 2400) number = 1;
+
+ return number;
+}
+
+/* log base 2 */
+static u8 cycx_log2(u32 n)
+{
+ u8 log = 0;
+
+ if (!n)
+ return 0;
+
+ while (n > 1) {
+ n >>= 1;
+ ++log;
+ }
+
+ return log;
+}
+
+/* Convert decimal string to unsigned integer.
+ * If len != 0 then only 'len' characters of the string are converted. */
+static unsigned dec_to_uint(u8 *str, int len)
+{
+ unsigned val = 0;
+
+ if (!len)
+ len = strlen(str);
+
+ for (; len && is_digit(*str); ++str, --len)
+ val = (val * 10) + (*str - (unsigned) '0');
+
+ return val;
+}
+
+static void reset_timer(struct net_device *dev)
+{
+ struct cycx_x25_channel *chan = dev->priv;
+
+ if (chan->svc)
+ mod_timer(&chan->timer, jiffies+chan->idle_tmout*HZ);
+}
+#ifdef CYCLOMX_X25_DEBUG
+static void cycx_x25_dump_config(struct cycx_x25_config *conf)
+{
+ printk(KERN_INFO "X.25 configuration\n");
+ printk(KERN_INFO "-----------------\n");
+ printk(KERN_INFO "link number=%d\n", conf->link);
+ printk(KERN_INFO "line speed=%d\n", conf->speed);
+ printk(KERN_INFO "clock=%sternal\n", conf->clock == 8 ? "Ex" : "In");
+ printk(KERN_INFO "# level 2 retransm.=%d\n", conf->n2);
+ printk(KERN_INFO "level 2 window=%d\n", conf->n2win);
+ printk(KERN_INFO "level 3 window=%d\n", conf->n3win);
+ printk(KERN_INFO "# logical channels=%d\n", conf->nvc);
+ printk(KERN_INFO "level 3 pkt len=%d\n", conf->pktlen);
+ printk(KERN_INFO "my address=%d\n", conf->locaddr);
+ printk(KERN_INFO "remote address=%d\n", conf->remaddr);
+ printk(KERN_INFO "t1=%d seconds\n", conf->t1);
+ printk(KERN_INFO "t2=%d seconds\n", conf->t2);
+ printk(KERN_INFO "t21=%d seconds\n", conf->t21);
+ printk(KERN_INFO "# PVCs=%d\n", conf->npvc);
+ printk(KERN_INFO "t23=%d seconds\n", conf->t23);
+ printk(KERN_INFO "flags=0x%x\n", conf->flags);
+}
+
+static void cycx_x25_dump_stats(struct cycx_x25_stats *stats)
+{
+ printk(KERN_INFO "X.25 statistics\n");
+ printk(KERN_INFO "--------------\n");
+ printk(KERN_INFO "rx_crc_errors=%d\n", stats->rx_crc_errors);
+ printk(KERN_INFO "rx_over_errors=%d\n", stats->rx_over_errors);
+ printk(KERN_INFO "n2_tx_frames=%d\n", stats->n2_tx_frames);
+ printk(KERN_INFO "n2_rx_frames=%d\n", stats->n2_rx_frames);
+ printk(KERN_INFO "tx_timeouts=%d\n", stats->tx_timeouts);
+ printk(KERN_INFO "rx_timeouts=%d\n", stats->rx_timeouts);
+ printk(KERN_INFO "n3_tx_packets=%d\n", stats->n3_tx_packets);
+ printk(KERN_INFO "n3_rx_packets=%d\n", stats->n3_rx_packets);
+ printk(KERN_INFO "tx_aborts=%d\n", stats->tx_aborts);
+ printk(KERN_INFO "rx_aborts=%d\n", stats->rx_aborts);
+}
+
+static void cycx_x25_dump_devs(struct wan_device *wandev)
+{
+ struct net_device *dev = wandev->dev;
+
+ printk(KERN_INFO "X.25 dev states\n");
+ printk(KERN_INFO "name: addr: txoff: protocol:\n");
+ printk(KERN_INFO "---------------------------------------\n");
+
+ while(dev) {
+ struct cycx_x25_channel *chan = dev->priv;
+
+ printk(KERN_INFO "%-5.5s %-15.15s %d ETH_P_%s\n",
+ chan->name, chan->addr, netif_queue_stopped(dev),
+ chan->protocol == ETH_P_IP ? "IP" : "X25");
+ dev = chan->slave;
+ }
+}
+
+#endif /* CYCLOMX_X25_DEBUG */
+/* End */
diff --git a/drivers/net/wan/dlci.c b/drivers/net/wan/dlci.c
new file mode 100644
index 000000000000..6e1ec5bf22fc
--- /dev/null
+++ b/drivers/net/wan/dlci.c
@@ -0,0 +1,566 @@
+/*
+ * DLCI Implementation of Frame Relay protocol for Linux, according to
+ * RFC 1490. This generic device provides en/decapsulation for an
+ * underlying hardware driver. Routes & IPs are assigned to these
+ * interfaces. Requires 'dlcicfg' program to create usable
+ * interfaces, the initial one, 'dlci' is for IOCTL use only.
+ *
+ * Version: @(#)dlci.c 0.35 4 Jan 1997
+ *
+ * Author: Mike McLagan
+ *
+ * Changes:
+ *
+ * 0.15 Mike Mclagan Packet freeing, bug in kmalloc call
+ * DLCI_RET handling
+ * 0.20 Mike McLagan More conservative on which packets
+ * are returned for retry and which are
+ * are dropped. If DLCI_RET_DROP is
+ * returned from the FRAD, the packet is
+ * sent back to Linux for re-transmission
+ * 0.25 Mike McLagan Converted to use SIOC IOCTL calls
+ * 0.30 Jim Freeman Fixed to allow IPX traffic
+ * 0.35 Michael Elizabeth Fixed incorrect memcpy_fromfs
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include /* for CONFIG_DLCI_COUNT */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+
+static const char version[] = "DLCI driver v0.35, 4 Jan 1997, mike.mclagan@linux.org";
+
+static LIST_HEAD(dlci_devs);
+
+static void dlci_setup(struct net_device *);
+
+/*
+ * these encapsulate the RFC 1490 requirements as well as
+ * deal with packet transmission and reception, working with
+ * the upper network layers
+ */
+
+static int dlci_header(struct sk_buff *skb, struct net_device *dev,
+ unsigned short type, void *daddr, void *saddr,
+ unsigned len)
+{
+ struct frhdr hdr;
+ struct dlci_local *dlp;
+ unsigned int hlen;
+ char *dest;
+
+ dlp = dev->priv;
+
+ hdr.control = FRAD_I_UI;
+ switch(type)
+ {
+ case ETH_P_IP:
+ hdr.IP_NLPID = FRAD_P_IP;
+ hlen = sizeof(hdr.control) + sizeof(hdr.IP_NLPID);
+ break;
+
+ /* feel free to add other types, if necessary */
+
+ default:
+ hdr.pad = FRAD_P_PADDING;
+ hdr.NLPID = FRAD_P_SNAP;
+ memset(hdr.OUI, 0, sizeof(hdr.OUI));
+ hdr.PID = htons(type);
+ hlen = sizeof(hdr);
+ break;
+ }
+
+ dest = skb_push(skb, hlen);
+ if (!dest)
+ return(0);
+
+ memcpy(dest, &hdr, hlen);
+
+ return(hlen);
+}
+
+static void dlci_receive(struct sk_buff *skb, struct net_device *dev)
+{
+ struct dlci_local *dlp;
+ struct frhdr *hdr;
+ int process, header;
+
+ dlp = dev->priv;
+ if (!pskb_may_pull(skb, sizeof(*hdr))) {
+ printk(KERN_NOTICE "%s: invalid data no header\n",
+ dev->name);
+ dlp->stats.rx_errors++;
+ kfree_skb(skb);
+ return;
+ }
+
+ hdr = (struct frhdr *) skb->data;
+ process = 0;
+ header = 0;
+ skb->dev = dev;
+
+ if (hdr->control != FRAD_I_UI)
+ {
+ printk(KERN_NOTICE "%s: Invalid header flag 0x%02X.\n", dev->name, hdr->control);
+ dlp->stats.rx_errors++;
+ }
+ else
+ switch(hdr->IP_NLPID)
+ {
+ case FRAD_P_PADDING:
+ if (hdr->NLPID != FRAD_P_SNAP)
+ {
+ printk(KERN_NOTICE "%s: Unsupported NLPID 0x%02X.\n", dev->name, hdr->NLPID);
+ dlp->stats.rx_errors++;
+ break;
+ }
+
+ if (hdr->OUI[0] + hdr->OUI[1] + hdr->OUI[2] != 0)
+ {
+ printk(KERN_NOTICE "%s: Unsupported organizationally unique identifier 0x%02X-%02X-%02X.\n", dev->name, hdr->OUI[0], hdr->OUI[1], hdr->OUI[2]);
+ dlp->stats.rx_errors++;
+ break;
+ }
+
+ /* at this point, it's an EtherType frame */
+ header = sizeof(struct frhdr);
+ /* Already in network order ! */
+ skb->protocol = hdr->PID;
+ process = 1;
+ break;
+
+ case FRAD_P_IP:
+ header = sizeof(hdr->control) + sizeof(hdr->IP_NLPID);
+ skb->protocol = htons(ETH_P_IP);
+ process = 1;
+ break;
+
+ case FRAD_P_SNAP:
+ case FRAD_P_Q933:
+ case FRAD_P_CLNP:
+ printk(KERN_NOTICE "%s: Unsupported NLPID 0x%02X.\n", dev->name, hdr->pad);
+ dlp->stats.rx_errors++;
+ break;
+
+ default:
+ printk(KERN_NOTICE "%s: Invalid pad byte 0x%02X.\n", dev->name, hdr->pad);
+ dlp->stats.rx_errors++;
+ break;
+ }
+
+ if (process)
+ {
+ /* we've set up the protocol, so discard the header */
+ skb->mac.raw = skb->data;
+ skb_pull(skb, header);
+ dlp->stats.rx_bytes += skb->len;
+ netif_rx(skb);
+ dlp->stats.rx_packets++;
+ dev->last_rx = jiffies;
+ }
+ else
+ dev_kfree_skb(skb);
+}
+
+static int dlci_transmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct dlci_local *dlp;
+ int ret;
+
+ ret = 0;
+
+ if (!skb || !dev)
+ return(0);
+
+ dlp = dev->priv;
+
+ netif_stop_queue(dev);
+
+ ret = dlp->slave->hard_start_xmit(skb, dlp->slave);
+ switch (ret)
+ {
+ case DLCI_RET_OK:
+ dlp->stats.tx_packets++;
+ ret = 0;
+ break;
+ case DLCI_RET_ERR:
+ dlp->stats.tx_errors++;
+ ret = 0;
+ break;
+ case DLCI_RET_DROP:
+ dlp->stats.tx_dropped++;
+ ret = 1;
+ break;
+ }
+ /* Alan Cox recommends always returning 0, and always freeing the packet */
+ /* experience suggest a slightly more conservative approach */
+
+ if (!ret)
+ {
+ dev_kfree_skb(skb);
+ netif_wake_queue(dev);
+ }
+ return(ret);
+}
+
+static int dlci_config(struct net_device *dev, struct dlci_conf __user *conf, int get)
+{
+ struct dlci_conf config;
+ struct dlci_local *dlp;
+ struct frad_local *flp;
+ int err;
+
+ dlp = dev->priv;
+
+ flp = dlp->slave->priv;
+
+ if (!get)
+ {
+ if(copy_from_user(&config, conf, sizeof(struct dlci_conf)))
+ return -EFAULT;
+ if (config.flags & ~DLCI_VALID_FLAGS)
+ return(-EINVAL);
+ memcpy(&dlp->config, &config, sizeof(struct dlci_conf));
+ dlp->configured = 1;
+ }
+
+ err = (*flp->dlci_conf)(dlp->slave, dev, get);
+ if (err)
+ return(err);
+
+ if (get)
+ {
+ if(copy_to_user(conf, &dlp->config, sizeof(struct dlci_conf)))
+ return -EFAULT;
+ }
+
+ return(0);
+}
+
+static int dlci_dev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ struct dlci_local *dlp;
+
+ if (!capable(CAP_NET_ADMIN))
+ return(-EPERM);
+
+ dlp = dev->priv;
+
+ switch(cmd)
+ {
+ case DLCI_GET_SLAVE:
+ if (!*(short *)(dev->dev_addr))
+ return(-EINVAL);
+
+ strncpy(ifr->ifr_slave, dlp->slave->name, sizeof(ifr->ifr_slave));
+ break;
+
+ case DLCI_GET_CONF:
+ case DLCI_SET_CONF:
+ if (!*(short *)(dev->dev_addr))
+ return(-EINVAL);
+
+ return(dlci_config(dev, ifr->ifr_data, cmd == DLCI_GET_CONF));
+ break;
+
+ default:
+ return(-EOPNOTSUPP);
+ }
+ return(0);
+}
+
+static int dlci_change_mtu(struct net_device *dev, int new_mtu)
+{
+ struct dlci_local *dlp;
+
+ dlp = dev->priv;
+
+ return((*dlp->slave->change_mtu)(dlp->slave, new_mtu));
+}
+
+static int dlci_open(struct net_device *dev)
+{
+ struct dlci_local *dlp;
+ struct frad_local *flp;
+ int err;
+
+ dlp = dev->priv;
+
+ if (!*(short *)(dev->dev_addr))
+ return(-EINVAL);
+
+ if (!netif_running(dlp->slave))
+ return(-ENOTCONN);
+
+ flp = dlp->slave->priv;
+ err = (*flp->activate)(dlp->slave, dev);
+ if (err)
+ return(err);
+
+ netif_start_queue(dev);
+
+ return 0;
+}
+
+static int dlci_close(struct net_device *dev)
+{
+ struct dlci_local *dlp;
+ struct frad_local *flp;
+ int err;
+
+ netif_stop_queue(dev);
+
+ dlp = dev->priv;
+
+ flp = dlp->slave->priv;
+ err = (*flp->deactivate)(dlp->slave, dev);
+
+ return 0;
+}
+
+static struct net_device_stats *dlci_get_stats(struct net_device *dev)
+{
+ struct dlci_local *dlp;
+
+ dlp = dev->priv;
+
+ return(&dlp->stats);
+}
+
+static int dlci_add(struct dlci_add *dlci)
+{
+ struct net_device *master, *slave;
+ struct dlci_local *dlp;
+ struct frad_local *flp;
+ int err = -EINVAL;
+
+
+ /* validate slave device */
+ slave = dev_get_by_name(dlci->devname);
+ if (!slave)
+ return -ENODEV;
+
+ if (slave->type != ARPHRD_FRAD || slave->priv == NULL)
+ goto err1;
+
+ /* create device name */
+ master = alloc_netdev( sizeof(struct dlci_local), "dlci%d",
+ dlci_setup);
+ if (!master) {
+ err = -ENOMEM;
+ goto err1;
+ }
+
+ /* make sure same slave not already registered */
+ rtnl_lock();
+ list_for_each_entry(dlp, &dlci_devs, list) {
+ if (dlp->slave == slave) {
+ err = -EBUSY;
+ goto err2;
+ }
+ }
+
+ err = dev_alloc_name(master, master->name);
+ if (err < 0)
+ goto err2;
+
+ *(short *)(master->dev_addr) = dlci->dlci;
+
+ dlp = (struct dlci_local *) master->priv;
+ dlp->slave = slave;
+ dlp->master = master;
+
+ flp = slave->priv;
+ err = (*flp->assoc)(slave, master);
+ if (err < 0)
+ goto err2;
+
+ err = register_netdevice(master);
+ if (err < 0)
+ goto err2;
+
+ strcpy(dlci->devname, master->name);
+
+ list_add(&dlp->list, &dlci_devs);
+ rtnl_unlock();
+
+ return(0);
+
+ err2:
+ rtnl_unlock();
+ free_netdev(master);
+ err1:
+ dev_put(slave);
+ return(err);
+}
+
+static int dlci_del(struct dlci_add *dlci)
+{
+ struct dlci_local *dlp;
+ struct frad_local *flp;
+ struct net_device *master, *slave;
+ int err;
+
+ /* validate slave device */
+ master = __dev_get_by_name(dlci->devname);
+ if (!master)
+ return(-ENODEV);
+
+ if (netif_running(master)) {
+ return(-EBUSY);
+ }
+
+ dlp = master->priv;
+ slave = dlp->slave;
+ flp = slave->priv;
+
+ rtnl_lock();
+ err = (*flp->deassoc)(slave, master);
+ if (!err) {
+ list_del(&dlp->list);
+
+ unregister_netdevice(master);
+
+ dev_put(slave);
+ }
+ rtnl_unlock();
+
+ return(err);
+}
+
+static int dlci_ioctl(unsigned int cmd, void __user *arg)
+{
+ struct dlci_add add;
+ int err;
+
+ if (!capable(CAP_NET_ADMIN))
+ return(-EPERM);
+
+ if(copy_from_user(&add, arg, sizeof(struct dlci_add)))
+ return -EFAULT;
+
+ switch (cmd)
+ {
+ case SIOCADDDLCI:
+ err = dlci_add(&add);
+
+ if (!err)
+ if(copy_to_user(arg, &add, sizeof(struct dlci_add)))
+ return -EFAULT;
+ break;
+
+ case SIOCDELDLCI:
+ err = dlci_del(&add);
+ break;
+
+ default:
+ err = -EINVAL;
+ }
+
+ return(err);
+}
+
+static void dlci_setup(struct net_device *dev)
+{
+ struct dlci_local *dlp = dev->priv;
+
+ dev->flags = 0;
+ dev->open = dlci_open;
+ dev->stop = dlci_close;
+ dev->do_ioctl = dlci_dev_ioctl;
+ dev->hard_start_xmit = dlci_transmit;
+ dev->hard_header = dlci_header;
+ dev->get_stats = dlci_get_stats;
+ dev->change_mtu = dlci_change_mtu;
+ dev->destructor = free_netdev;
+
+ dlp->receive = dlci_receive;
+
+ dev->type = ARPHRD_DLCI;
+ dev->hard_header_len = sizeof(struct frhdr);
+ dev->addr_len = sizeof(short);
+
+}
+
+/* if slave is unregistering, then cleanup master */
+static int dlci_dev_event(struct notifier_block *unused,
+ unsigned long event, void *ptr)
+{
+ struct net_device *dev = (struct net_device *) ptr;
+
+ if (event == NETDEV_UNREGISTER) {
+ struct dlci_local *dlp;
+
+ list_for_each_entry(dlp, &dlci_devs, list) {
+ if (dlp->slave == dev) {
+ list_del(&dlp->list);
+ unregister_netdevice(dlp->master);
+ dev_put(dlp->slave);
+ break;
+ }
+ }
+ }
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block dlci_notifier = {
+ .notifier_call = dlci_dev_event,
+};
+
+static int __init init_dlci(void)
+{
+ dlci_ioctl_set(dlci_ioctl);
+ register_netdevice_notifier(&dlci_notifier);
+
+ printk("%s.\n", version);
+
+ return 0;
+}
+
+static void __exit dlci_exit(void)
+{
+ struct dlci_local *dlp, *nxt;
+
+ dlci_ioctl_set(NULL);
+ unregister_netdevice_notifier(&dlci_notifier);
+
+ rtnl_lock();
+ list_for_each_entry_safe(dlp, nxt, &dlci_devs, list) {
+ unregister_netdevice(dlp->master);
+ dev_put(dlp->slave);
+ }
+ rtnl_unlock();
+}
+
+module_init(init_dlci);
+module_exit(dlci_exit);
+
+MODULE_AUTHOR("Mike McLagan");
+MODULE_DESCRIPTION("Frame Relay DLCI layer");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/wan/dscc4.c b/drivers/net/wan/dscc4.c
new file mode 100644
index 000000000000..520a77a798e2
--- /dev/null
+++ b/drivers/net/wan/dscc4.c
@@ -0,0 +1,2074 @@
+/*
+ * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
+ *
+ * This software may be used and distributed according to the terms of the
+ * GNU General Public License.
+ *
+ * The author may be reached as romieu@cogenit.fr.
+ * Specific bug reports/asian food will be welcome.
+ *
+ * Special thanks to the nice people at CS-Telecom for the hardware and the
+ * access to the test/measure tools.
+ *
+ *
+ * Theory of Operation
+ *
+ * I. Board Compatibility
+ *
+ * This device driver is designed for the Siemens PEB20534 4 ports serial
+ * controller as found on Etinc PCISYNC cards. The documentation for the
+ * chipset is available at http://www.infineon.com:
+ * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
+ * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
+ * - Application Hint "Management of DSCC4 on-chip FIFO resources".
+ * - Errata sheet DS5 (courtesy of Michael Skerritt).
+ * Jens David has built an adapter based on the same chipset. Take a look
+ * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
+ * driver.
+ * Sample code (2 revisions) is available at Infineon.
+ *
+ * II. Board-specific settings
+ *
+ * Pcisync can transmit some clock signal to the outside world on the
+ * *first two* ports provided you put a quartz and a line driver on it and
+ * remove the jumpers. The operation is described on Etinc web site. If you
+ * go DCE on these ports, don't forget to use an adequate cable.
+ *
+ * Sharing of the PCI interrupt line for this board is possible.
+ *
+ * III. Driver operation
+ *
+ * The rx/tx operations are based on a linked list of descriptors. The driver
+ * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
+ * I tried to fix it, the more it started to look like (convoluted) software
+ * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
+ * this a rfc2119 MUST.
+ *
+ * Tx direction
+ * When the tx ring is full, the xmit routine issues a call to netdev_stop.
+ * The device is supposed to be enabled again during an ALLS irq (we could
+ * use HI but as it's easy to lose events, it's fscked).
+ *
+ * Rx direction
+ * The received frames aren't supposed to span over multiple receiving areas.
+ * I may implement it some day but it isn't the highest ranked item.
+ *
+ * IV. Notes
+ * The current error (XDU, RFO) recovery code is untested.
+ * So far, RDO takes his RX channel down and the right sequence to enable it
+ * again is still a mistery. If RDO happens, plan a reboot. More details
+ * in the code (NB: as this happens, TX still works).
+ * Don't mess the cables during operation, especially on DTE ports. I don't
+ * suggest it for DCE either but at least one can get some messages instead
+ * of a complete instant freeze.
+ * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
+ * the documentation/chipset releases.
+ *
+ * TODO:
+ * - test X25.
+ * - use polling at high irq/s,
+ * - performance analysis,
+ * - endianness.
+ *
+ * 2001/12/10 Daniela Squassoni
+ * - Contribution to support the new generic HDLC layer.
+ *
+ * 2002/01 Ueimor
+ * - old style interface removal
+ * - dscc4_release_ring fix (related to DMA mapping)
+ * - hard_start_xmit fix (hint: TxSizeMax)
+ * - misc crapectomy.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Version */
+static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
+static int debug;
+static int quartz;
+
+#ifdef CONFIG_DSCC4_PCI_RST
+static DECLARE_MUTEX(dscc4_sem);
+static u32 dscc4_pci_config_store[16];
+#endif
+
+#define DRV_NAME "dscc4"
+
+#undef DSCC4_POLLING
+
+/* Module parameters */
+
+MODULE_AUTHOR("Maintainer: Francois Romieu ");
+MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
+MODULE_LICENSE("GPL");
+module_param(debug, int, 0);
+MODULE_PARM_DESC(debug,"Enable/disable extra messages");
+module_param(quartz, int, 0);
+MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
+
+/* Structures */
+
+struct thingie {
+ int define;
+ u32 bits;
+};
+
+struct TxFD {
+ u32 state;
+ u32 next;
+ u32 data;
+ u32 complete;
+ u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
+};
+
+struct RxFD {
+ u32 state1;
+ u32 next;
+ u32 data;
+ u32 state2;
+ u32 end;
+};
+
+#define DUMMY_SKB_SIZE 64
+#define TX_LOW 8
+#define TX_RING_SIZE 32
+#define RX_RING_SIZE 32
+#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
+#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
+#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
+#define TX_TIMEOUT (HZ/10)
+#define DSCC4_HZ_MAX 33000000
+#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
+#define dev_per_card 4
+#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
+
+#define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
+#define TO_SIZE(state) (((state) >> 16) & 0x1fff)
+
+/*
+ * Given the operating range of Linux HDLC, the 2 defines below could be
+ * made simpler. However they are a fine reminder for the limitations of
+ * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
+ */
+#define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
+#define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
+#define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
+#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
+
+struct dscc4_pci_priv {
+ u32 *iqcfg;
+ int cfg_cur;
+ spinlock_t lock;
+ struct pci_dev *pdev;
+
+ struct dscc4_dev_priv *root;
+ dma_addr_t iqcfg_dma;
+ u32 xtal_hz;
+};
+
+struct dscc4_dev_priv {
+ struct sk_buff *rx_skbuff[RX_RING_SIZE];
+ struct sk_buff *tx_skbuff[TX_RING_SIZE];
+
+ struct RxFD *rx_fd;
+ struct TxFD *tx_fd;
+ u32 *iqrx;
+ u32 *iqtx;
+
+ /* FIXME: check all the volatile are required */
+ volatile u32 tx_current;
+ u32 rx_current;
+ u32 iqtx_current;
+ u32 iqrx_current;
+
+ volatile u32 tx_dirty;
+ volatile u32 ltda;
+ u32 rx_dirty;
+ u32 lrda;
+
+ dma_addr_t tx_fd_dma;
+ dma_addr_t rx_fd_dma;
+ dma_addr_t iqtx_dma;
+ dma_addr_t iqrx_dma;
+
+ u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
+
+ struct timer_list timer;
+
+ struct dscc4_pci_priv *pci_priv;
+ spinlock_t lock;
+
+ int dev_id;
+ volatile u32 flags;
+ u32 timer_help;
+
+ unsigned short encoding;
+ unsigned short parity;
+ struct net_device *dev;
+ sync_serial_settings settings;
+ void __iomem *base_addr;
+ u32 __pad __attribute__ ((aligned (4)));
+};
+
+/* GLOBAL registers definitions */
+#define GCMDR 0x00
+#define GSTAR 0x04
+#define GMODE 0x08
+#define IQLENR0 0x0C
+#define IQLENR1 0x10
+#define IQRX0 0x14
+#define IQTX0 0x24
+#define IQCFG 0x3c
+#define FIFOCR1 0x44
+#define FIFOCR2 0x48
+#define FIFOCR3 0x4c
+#define FIFOCR4 0x34
+#define CH0CFG 0x50
+#define CH0BRDA 0x54
+#define CH0BTDA 0x58
+#define CH0FRDA 0x98
+#define CH0FTDA 0xb0
+#define CH0LRDA 0xc8
+#define CH0LTDA 0xe0
+
+/* SCC registers definitions */
+#define SCC_START 0x0100
+#define SCC_OFFSET 0x80
+#define CMDR 0x00
+#define STAR 0x04
+#define CCR0 0x08
+#define CCR1 0x0c
+#define CCR2 0x10
+#define BRR 0x2C
+#define RLCR 0x40
+#define IMR 0x54
+#define ISR 0x58
+
+#define GPDIR 0x0400
+#define GPDATA 0x0404
+#define GPIM 0x0408
+
+/* Bit masks */
+#define EncodingMask 0x00700000
+#define CrcMask 0x00000003
+
+#define IntRxScc0 0x10000000
+#define IntTxScc0 0x01000000
+
+#define TxPollCmd 0x00000400
+#define RxActivate 0x08000000
+#define MTFi 0x04000000
+#define Rdr 0x00400000
+#define Rdt 0x00200000
+#define Idr 0x00100000
+#define Idt 0x00080000
+#define TxSccRes 0x01000000
+#define RxSccRes 0x00010000
+#define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
+#define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
+
+#define Ccr0ClockMask 0x0000003f
+#define Ccr1LoopMask 0x00000200
+#define IsrMask 0x000fffff
+#define BrrExpMask 0x00000f00
+#define BrrMultMask 0x0000003f
+#define EncodingMask 0x00700000
+#define Hold 0x40000000
+#define SccBusy 0x10000000
+#define PowerUp 0x80000000
+#define Vis 0x00001000
+#define FrameOk (FrameVfr | FrameCrc)
+#define FrameVfr 0x80
+#define FrameRdo 0x40
+#define FrameCrc 0x20
+#define FrameRab 0x10
+#define FrameAborted 0x00000200
+#define FrameEnd 0x80000000
+#define DataComplete 0x40000000
+#define LengthCheck 0x00008000
+#define SccEvt 0x02000000
+#define NoAck 0x00000200
+#define Action 0x00000001
+#define HiDesc 0x20000000
+
+/* SCC events */
+#define RxEvt 0xf0000000
+#define TxEvt 0x0f000000
+#define Alls 0x00040000
+#define Xdu 0x00010000
+#define Cts 0x00004000
+#define Xmr 0x00002000
+#define Xpr 0x00001000
+#define Rdo 0x00000080
+#define Rfs 0x00000040
+#define Cd 0x00000004
+#define Rfo 0x00000002
+#define Flex 0x00000001
+
+/* DMA core events */
+#define Cfg 0x00200000
+#define Hi 0x00040000
+#define Fi 0x00020000
+#define Err 0x00010000
+#define Arf 0x00000002
+#define ArAck 0x00000001
+
+/* State flags */
+#define Ready 0x00000000
+#define NeedIDR 0x00000001
+#define NeedIDT 0x00000002
+#define RdoSet 0x00000004
+#define FakeReset 0x00000008
+
+/* Don't mask RDO. Ever. */
+#ifdef DSCC4_POLLING
+#define EventsMask 0xfffeef7f
+#else
+#define EventsMask 0xfffa8f7a
+#endif
+
+/* Functions prototypes */
+static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
+static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
+static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
+static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
+static int dscc4_open(struct net_device *);
+static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
+static int dscc4_close(struct net_device *);
+static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+static int dscc4_init_ring(struct net_device *);
+static void dscc4_release_ring(struct dscc4_dev_priv *);
+static void dscc4_timer(unsigned long);
+static void dscc4_tx_timeout(struct net_device *);
+static irqreturn_t dscc4_irq(int irq, void *dev_id, struct pt_regs *ptregs);
+static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
+static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
+#ifdef DSCC4_POLLING
+static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
+#endif
+
+static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
+{
+ return dev_to_hdlc(dev)->priv;
+}
+
+static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
+{
+ return p->dev;
+}
+
+static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
+ struct net_device *dev, int offset)
+{
+ u32 state;
+
+ /* Cf scc_writel for concern regarding thread-safety */
+ state = dpriv->scc_regs[offset >> 2];
+ state &= ~mask;
+ state |= value;
+ dpriv->scc_regs[offset >> 2] = state;
+ writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
+}
+
+static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
+ struct net_device *dev, int offset)
+{
+ /*
+ * Thread-UNsafe.
+ * As of 2002/02/16, there are no thread racing for access.
+ */
+ dpriv->scc_regs[offset >> 2] = bits;
+ writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
+}
+
+static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
+{
+ return dpriv->scc_regs[offset >> 2];
+}
+
+static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
+{
+ /* Cf errata DS5 p.4 */
+ readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
+ return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
+}
+
+static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ dpriv->ltda = dpriv->tx_fd_dma +
+ ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
+ writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
+ /* Flush posted writes *NOW* */
+ readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
+}
+
+static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ dpriv->lrda = dpriv->rx_fd_dma +
+ ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
+ writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
+}
+
+static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
+{
+ return dpriv->tx_current == dpriv->tx_dirty;
+}
+
+static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
+}
+
+int state_check(u32 state, struct dscc4_dev_priv *dpriv, struct net_device *dev,
+ const char *msg)
+{
+ int ret = 0;
+
+ if (debug > 1) {
+ if (SOURCE_ID(state) != dpriv->dev_id) {
+ printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
+ dev->name, msg, SOURCE_ID(state), state );
+ ret = -1;
+ }
+ if (state & 0x0df80c00) {
+ printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
+ dev->name, msg, state);
+ ret = -1;
+ }
+ }
+ return ret;
+}
+
+void dscc4_tx_print(struct net_device *dev, struct dscc4_dev_priv *dpriv,
+ char *msg)
+{
+ printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
+ dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
+}
+
+static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
+{
+ struct pci_dev *pdev = dpriv->pci_priv->pdev;
+ struct TxFD *tx_fd = dpriv->tx_fd;
+ struct RxFD *rx_fd = dpriv->rx_fd;
+ struct sk_buff **skbuff;
+ int i;
+
+ pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
+ pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
+
+ skbuff = dpriv->tx_skbuff;
+ for (i = 0; i < TX_RING_SIZE; i++) {
+ if (*skbuff) {
+ pci_unmap_single(pdev, tx_fd->data, (*skbuff)->len,
+ PCI_DMA_TODEVICE);
+ dev_kfree_skb(*skbuff);
+ }
+ skbuff++;
+ tx_fd++;
+ }
+
+ skbuff = dpriv->rx_skbuff;
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ if (*skbuff) {
+ pci_unmap_single(pdev, rx_fd->data,
+ RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
+ dev_kfree_skb(*skbuff);
+ }
+ skbuff++;
+ rx_fd++;
+ }
+}
+
+inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv, struct net_device *dev)
+{
+ unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
+ struct RxFD *rx_fd = dpriv->rx_fd + dirty;
+ const int len = RX_MAX(HDLC_MAX_MRU);
+ struct sk_buff *skb;
+ int ret = 0;
+
+ skb = dev_alloc_skb(len);
+ dpriv->rx_skbuff[dirty] = skb;
+ if (skb) {
+ skb->protocol = hdlc_type_trans(skb, dev);
+ rx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
+ len, PCI_DMA_FROMDEVICE);
+ } else {
+ rx_fd->data = (u32) NULL;
+ ret = -1;
+ }
+ return ret;
+}
+
+/*
+ * IRQ/thread/whatever safe
+ */
+static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev, char *msg)
+{
+ s8 i = 0;
+
+ do {
+ if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
+ printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
+ msg, i);
+ goto done;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(10);
+ rmb();
+ } while (++i > 0);
+ printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
+done:
+ return (i >= 0) ? i : -EAGAIN;
+}
+
+static int dscc4_do_action(struct net_device *dev, char *msg)
+{
+ void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
+ s16 i = 0;
+
+ writel(Action, ioaddr + GCMDR);
+ ioaddr += GSTAR;
+ do {
+ u32 state = readl(ioaddr);
+
+ if (state & ArAck) {
+ printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
+ writel(ArAck, ioaddr);
+ goto done;
+ } else if (state & Arf) {
+ printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
+ writel(Arf, ioaddr);
+ i = -1;
+ goto done;
+ }
+ rmb();
+ } while (++i > 0);
+ printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
+done:
+ return i;
+}
+
+static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
+{
+ int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
+ s8 i = 0;
+
+ do {
+ if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
+ (dpriv->iqtx[cur] & Xpr))
+ break;
+ smp_rmb();
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(10);
+ } while (++i > 0);
+
+ return (i >= 0 ) ? i : -EAGAIN;
+}
+
+#if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
+static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
+ /* Cf errata DS5 p.6 */
+ writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
+ scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
+ readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
+ writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
+ writel(Action, dpriv->base_addr + GCMDR);
+ spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
+}
+
+#endif
+
+#if 0
+static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
+{
+ u16 i = 0;
+
+ /* Cf errata DS5 p.7 */
+ scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
+ scc_writel(0x00050000, dpriv, dev, CCR2);
+ /*
+ * Must be longer than the time required to fill the fifo.
+ */
+ while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
+ udelay(1);
+ wmb();
+ }
+
+ writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
+ if (dscc4_do_action(dev, "Rdt") < 0)
+ printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
+}
+#endif
+
+/* TODO: (ab)use this function to refill a completely depleted RX ring. */
+static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
+ struct net_device_stats *stats = hdlc_stats(dev);
+ struct pci_dev *pdev = dpriv->pci_priv->pdev;
+ struct sk_buff *skb;
+ int pkt_len;
+
+ skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
+ if (!skb) {
+ printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__);
+ goto refill;
+ }
+ pkt_len = TO_SIZE(rx_fd->state2);
+ pci_unmap_single(pdev, rx_fd->data, RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
+ if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
+ stats->rx_packets++;
+ stats->rx_bytes += pkt_len;
+ skb_put(skb, pkt_len);
+ if (netif_running(dev))
+ skb->protocol = hdlc_type_trans(skb, dev);
+ skb->dev->last_rx = jiffies;
+ netif_rx(skb);
+ } else {
+ if (skb->data[pkt_len] & FrameRdo)
+ stats->rx_fifo_errors++;
+ else if (!(skb->data[pkt_len] | ~FrameCrc))
+ stats->rx_crc_errors++;
+ else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
+ stats->rx_length_errors++;
+ else
+ stats->rx_errors++;
+ dev_kfree_skb_irq(skb);
+ }
+refill:
+ while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
+ if (try_get_rx_skb(dpriv, dev) < 0)
+ break;
+ dpriv->rx_dirty++;
+ }
+ dscc4_rx_update(dpriv, dev);
+ rx_fd->state2 = 0x00000000;
+ rx_fd->end = 0xbabeface;
+}
+
+static void dscc4_free1(struct pci_dev *pdev)
+{
+ struct dscc4_pci_priv *ppriv;
+ struct dscc4_dev_priv *root;
+ int i;
+
+ ppriv = pci_get_drvdata(pdev);
+ root = ppriv->root;
+
+ for (i = 0; i < dev_per_card; i++)
+ unregister_hdlc_device(dscc4_to_dev(root + i));
+
+ pci_set_drvdata(pdev, NULL);
+
+ for (i = 0; i < dev_per_card; i++)
+ free_netdev(root[i].dev);
+ kfree(root);
+ kfree(ppriv);
+}
+
+static int __devinit dscc4_init_one(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct dscc4_pci_priv *priv;
+ struct dscc4_dev_priv *dpriv;
+ void __iomem *ioaddr;
+ int i, rc;
+
+ printk(KERN_DEBUG "%s", version);
+
+ rc = pci_enable_device(pdev);
+ if (rc < 0)
+ goto out;
+
+ rc = pci_request_region(pdev, 0, "registers");
+ if (rc < 0) {
+ printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
+ DRV_NAME);
+ goto err_disable_0;
+ }
+ rc = pci_request_region(pdev, 1, "LBI interface");
+ if (rc < 0) {
+ printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
+ DRV_NAME);
+ goto err_free_mmio_region_1;
+ }
+
+ ioaddr = ioremap(pci_resource_start(pdev, 0),
+ pci_resource_len(pdev, 0));
+ if (!ioaddr) {
+ printk(KERN_ERR "%s: cannot remap MMIO region %lx @ %lx\n",
+ DRV_NAME, pci_resource_len(pdev, 0),
+ pci_resource_start(pdev, 0));
+ rc = -EIO;
+ goto err_free_mmio_regions_2;
+ }
+ printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#lx (regs), %#lx (lbi), IRQ %d\n",
+ pci_resource_start(pdev, 0),
+ pci_resource_start(pdev, 1), pdev->irq);
+
+ /* Cf errata DS5 p.2 */
+ pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
+ pci_set_master(pdev);
+
+ rc = dscc4_found1(pdev, ioaddr);
+ if (rc < 0)
+ goto err_iounmap_3;
+
+ priv = pci_get_drvdata(pdev);
+
+ rc = request_irq(pdev->irq, dscc4_irq, SA_SHIRQ, DRV_NAME, priv->root);
+ if (rc < 0) {
+ printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
+ goto err_release_4;
+ }
+
+ /* power up/little endian/dma core controlled via lrda/ltda */
+ writel(0x00000001, ioaddr + GMODE);
+ /* Shared interrupt queue */
+ {
+ u32 bits;
+
+ bits = (IRQ_RING_SIZE >> 5) - 1;
+ bits |= bits << 4;
+ bits |= bits << 8;
+ bits |= bits << 16;
+ writel(bits, ioaddr + IQLENR0);
+ }
+ /* Global interrupt queue */
+ writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
+ priv->iqcfg = (u32 *) pci_alloc_consistent(pdev,
+ IRQ_RING_SIZE*sizeof(u32), &priv->iqcfg_dma);
+ if (!priv->iqcfg)
+ goto err_free_irq_5;
+ writel(priv->iqcfg_dma, ioaddr + IQCFG);
+
+ rc = -ENOMEM;
+
+ /*
+ * SCC 0-3 private rx/tx irq structures
+ * IQRX/TXi needs to be set soon. Learned it the hard way...
+ */
+ for (i = 0; i < dev_per_card; i++) {
+ dpriv = priv->root + i;
+ dpriv->iqtx = (u32 *) pci_alloc_consistent(pdev,
+ IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
+ if (!dpriv->iqtx)
+ goto err_free_iqtx_6;
+ writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
+ }
+ for (i = 0; i < dev_per_card; i++) {
+ dpriv = priv->root + i;
+ dpriv->iqrx = (u32 *) pci_alloc_consistent(pdev,
+ IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
+ if (!dpriv->iqrx)
+ goto err_free_iqrx_7;
+ writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
+ }
+
+ /* Cf application hint. Beware of hard-lock condition on threshold. */
+ writel(0x42104000, ioaddr + FIFOCR1);
+ //writel(0x9ce69800, ioaddr + FIFOCR2);
+ writel(0xdef6d800, ioaddr + FIFOCR2);
+ //writel(0x11111111, ioaddr + FIFOCR4);
+ writel(0x18181818, ioaddr + FIFOCR4);
+ // FIXME: should depend on the chipset revision
+ writel(0x0000000e, ioaddr + FIFOCR3);
+
+ writel(0xff200001, ioaddr + GCMDR);
+
+ rc = 0;
+out:
+ return rc;
+
+err_free_iqrx_7:
+ while (--i >= 0) {
+ dpriv = priv->root + i;
+ pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
+ dpriv->iqrx, dpriv->iqrx_dma);
+ }
+ i = dev_per_card;
+err_free_iqtx_6:
+ while (--i >= 0) {
+ dpriv = priv->root + i;
+ pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
+ dpriv->iqtx, dpriv->iqtx_dma);
+ }
+ pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
+ priv->iqcfg_dma);
+err_free_irq_5:
+ free_irq(pdev->irq, priv->root);
+err_release_4:
+ dscc4_free1(pdev);
+err_iounmap_3:
+ iounmap (ioaddr);
+err_free_mmio_regions_2:
+ pci_release_region(pdev, 1);
+err_free_mmio_region_1:
+ pci_release_region(pdev, 0);
+err_disable_0:
+ pci_disable_device(pdev);
+ goto out;
+};
+
+/*
+ * Let's hope the default values are decent enough to protect my
+ * feet from the user's gun - Ueimor
+ */
+static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ /* No interrupts, SCC core disabled. Let's relax */
+ scc_writel(0x00000000, dpriv, dev, CCR0);
+
+ scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
+
+ /*
+ * No address recognition/crc-CCITT/cts enabled
+ * Shared flags transmission disabled - cf errata DS5 p.11
+ * Carrier detect disabled - cf errata p.14
+ * FIXME: carrier detection/polarity may be handled more gracefully.
+ */
+ scc_writel(0x02408000, dpriv, dev, CCR1);
+
+ /* crc not forwarded - Cf errata DS5 p.11 */
+ scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
+ // crc forwarded
+ //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
+}
+
+static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
+{
+ int ret = 0;
+
+ if ((hz < 0) || (hz > DSCC4_HZ_MAX))
+ ret = -EOPNOTSUPP;
+ else
+ dpriv->pci_priv->xtal_hz = hz;
+
+ return ret;
+}
+
+static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
+{
+ struct dscc4_pci_priv *ppriv;
+ struct dscc4_dev_priv *root;
+ int i, ret = -ENOMEM;
+
+ root = kmalloc(dev_per_card*sizeof(*root), GFP_KERNEL);
+ if (!root) {
+ printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
+ goto err_out;
+ }
+ memset(root, 0, dev_per_card*sizeof(*root));
+
+ for (i = 0; i < dev_per_card; i++) {
+ root[i].dev = alloc_hdlcdev(root + i);
+ if (!root[i].dev)
+ goto err_free_dev;
+ }
+
+ ppriv = kmalloc(sizeof(*ppriv), GFP_KERNEL);
+ if (!ppriv) {
+ printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
+ goto err_free_dev;
+ }
+ memset(ppriv, 0, sizeof(struct dscc4_pci_priv));
+
+ ppriv->root = root;
+ spin_lock_init(&ppriv->lock);
+
+ for (i = 0; i < dev_per_card; i++) {
+ struct dscc4_dev_priv *dpriv = root + i;
+ struct net_device *d = dscc4_to_dev(dpriv);
+ hdlc_device *hdlc = dev_to_hdlc(d);
+
+ d->base_addr = (unsigned long)ioaddr;
+ d->init = NULL;
+ d->irq = pdev->irq;
+ d->open = dscc4_open;
+ d->stop = dscc4_close;
+ d->set_multicast_list = NULL;
+ d->do_ioctl = dscc4_ioctl;
+ d->tx_timeout = dscc4_tx_timeout;
+ d->watchdog_timeo = TX_TIMEOUT;
+ SET_MODULE_OWNER(d);
+ SET_NETDEV_DEV(d, &pdev->dev);
+
+ dpriv->dev_id = i;
+ dpriv->pci_priv = ppriv;
+ dpriv->base_addr = ioaddr;
+ spin_lock_init(&dpriv->lock);
+
+ hdlc->xmit = dscc4_start_xmit;
+ hdlc->attach = dscc4_hdlc_attach;
+
+ dscc4_init_registers(dpriv, d);
+ dpriv->parity = PARITY_CRC16_PR0_CCITT;
+ dpriv->encoding = ENCODING_NRZ;
+
+ ret = dscc4_init_ring(d);
+ if (ret < 0)
+ goto err_unregister;
+
+ ret = register_hdlc_device(d);
+ if (ret < 0) {
+ printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
+ dscc4_release_ring(dpriv);
+ goto err_unregister;
+ }
+ }
+
+ ret = dscc4_set_quartz(root, quartz);
+ if (ret < 0)
+ goto err_unregister;
+
+ pci_set_drvdata(pdev, ppriv);
+ return ret;
+
+err_unregister:
+ while (i-- > 0) {
+ dscc4_release_ring(root + i);
+ unregister_hdlc_device(dscc4_to_dev(root + i));
+ }
+ kfree(ppriv);
+ i = dev_per_card;
+err_free_dev:
+ while (i-- > 0)
+ free_netdev(root[i].dev);
+ kfree(root);
+err_out:
+ return ret;
+};
+
+/* FIXME: get rid of the unneeded code */
+static void dscc4_timer(unsigned long data)
+{
+ struct net_device *dev = (struct net_device *)data;
+ struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
+// struct dscc4_pci_priv *ppriv;
+
+ goto done;
+done:
+ dpriv->timer.expires = jiffies + TX_TIMEOUT;
+ add_timer(&dpriv->timer);
+}
+
+static void dscc4_tx_timeout(struct net_device *dev)
+{
+ /* FIXME: something is missing there */
+}
+
+static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
+{
+ sync_serial_settings *settings = &dpriv->settings;
+
+ if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
+ struct net_device *dev = dscc4_to_dev(dpriv);
+
+ printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
+ return -1;
+ }
+ return 0;
+}
+
+#ifdef CONFIG_DSCC4_PCI_RST
+/*
+ * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
+ * so as to provide a safe way to reset the asic while not the whole machine
+ * rebooting.
+ *
+ * This code doesn't need to be efficient. Keep It Simple
+ */
+static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
+{
+ int i;
+
+ down(&dscc4_sem);
+ for (i = 0; i < 16; i++)
+ pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
+
+ /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
+ writel(0x001c0000, ioaddr + GMODE);
+ /* Configure GPIO port as output */
+ writel(0x0000ffff, ioaddr + GPDIR);
+ /* Disable interruption */
+ writel(0x0000ffff, ioaddr + GPIM);
+
+ writel(0x0000ffff, ioaddr + GPDATA);
+ writel(0x00000000, ioaddr + GPDATA);
+
+ /* Flush posted writes */
+ readl(ioaddr + GSTAR);
+
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(10);
+
+ for (i = 0; i < 16; i++)
+ pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
+ up(&dscc4_sem);
+}
+#else
+#define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
+#endif /* CONFIG_DSCC4_PCI_RST */
+
+static int dscc4_open(struct net_device *dev)
+{
+ struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
+ struct dscc4_pci_priv *ppriv;
+ int ret = -EAGAIN;
+
+ if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
+ goto err;
+
+ if ((ret = hdlc_open(dev)))
+ goto err;
+
+ ppriv = dpriv->pci_priv;
+
+ /*
+ * Due to various bugs, there is no way to reliably reset a
+ * specific port (manufacturer's dependant special PCI #RST wiring
+ * apart: it affects all ports). Thus the device goes in the best
+ * silent mode possible at dscc4_close() time and simply claims to
+ * be up if it's opened again. It still isn't possible to change
+ * the HDLC configuration without rebooting but at least the ports
+ * can be up/down ifconfig'ed without killing the host.
+ */
+ if (dpriv->flags & FakeReset) {
+ dpriv->flags &= ~FakeReset;
+ scc_patchl(0, PowerUp, dpriv, dev, CCR0);
+ scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
+ scc_writel(EventsMask, dpriv, dev, IMR);
+ printk(KERN_INFO "%s: up again.\n", dev->name);
+ goto done;
+ }
+
+ /* IDT+IDR during XPR */
+ dpriv->flags = NeedIDR | NeedIDT;
+
+ scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
+
+ /*
+ * The following is a bit paranoid...
+ *
+ * NB: the datasheet "...CEC will stay active if the SCC is in
+ * power-down mode or..." and CCR2.RAC = 1 are two different
+ * situations.
+ */
+ if (scc_readl_star(dpriv, dev) & SccBusy) {
+ printk(KERN_ERR "%s busy. Try later\n", dev->name);
+ ret = -EAGAIN;
+ goto err_out;
+ } else
+ printk(KERN_INFO "%s: available. Good\n", dev->name);
+
+ scc_writel(EventsMask, dpriv, dev, IMR);
+
+ /* Posted write is flushed in the wait_ack loop */
+ scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
+
+ if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
+ goto err_disable_scc_events;
+
+ /*
+ * I would expect XPR near CE completion (before ? after ?).
+ * At worst, this code won't see a late XPR and people
+ * will have to re-issue an ifconfig (this is harmless).
+ * WARNING, a really missing XPR usually means a hardware
+ * reset is needed. Suggestions anyone ?
+ */
+ if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
+ printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
+ goto err_disable_scc_events;
+ }
+
+ if (debug > 2)
+ dscc4_tx_print(dev, dpriv, "Open");
+
+done:
+ netif_start_queue(dev);
+
+ init_timer(&dpriv->timer);
+ dpriv->timer.expires = jiffies + 10*HZ;
+ dpriv->timer.data = (unsigned long)dev;
+ dpriv->timer.function = &dscc4_timer;
+ add_timer(&dpriv->timer);
+ netif_carrier_on(dev);
+
+ return 0;
+
+err_disable_scc_events:
+ scc_writel(0xffffffff, dpriv, dev, IMR);
+ scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
+err_out:
+ hdlc_close(dev);
+err:
+ return ret;
+}
+
+#ifdef DSCC4_POLLING
+static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
+{
+ /* FIXME: it's gonna be easy (TM), for sure */
+}
+#endif /* DSCC4_POLLING */
+
+static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
+ struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
+ struct TxFD *tx_fd;
+ int next;
+
+ next = dpriv->tx_current%TX_RING_SIZE;
+ dpriv->tx_skbuff[next] = skb;
+ tx_fd = dpriv->tx_fd + next;
+ tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
+ tx_fd->data = pci_map_single(ppriv->pdev, skb->data, skb->len,
+ PCI_DMA_TODEVICE);
+ tx_fd->complete = 0x00000000;
+ tx_fd->jiffies = jiffies;
+ mb();
+
+#ifdef DSCC4_POLLING
+ spin_lock(&dpriv->lock);
+ while (dscc4_tx_poll(dpriv, dev));
+ spin_unlock(&dpriv->lock);
+#endif
+
+ dev->trans_start = jiffies;
+
+ if (debug > 2)
+ dscc4_tx_print(dev, dpriv, "Xmit");
+ /* To be cleaned(unsigned int)/optimized. Later, ok ? */
+ if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
+ netif_stop_queue(dev);
+
+ if (dscc4_tx_quiescent(dpriv, dev))
+ dscc4_do_tx(dpriv, dev);
+
+ return 0;
+}
+
+static int dscc4_close(struct net_device *dev)
+{
+ struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
+
+ del_timer_sync(&dpriv->timer);
+ netif_stop_queue(dev);
+
+ scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
+ scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
+ scc_writel(0xffffffff, dpriv, dev, IMR);
+
+ dpriv->flags |= FakeReset;
+
+ hdlc_close(dev);
+
+ return 0;
+}
+
+static inline int dscc4_check_clock_ability(int port)
+{
+ int ret = 0;
+
+#ifdef CONFIG_DSCC4_PCISYNC
+ if (port >= 2)
+ ret = -1;
+#endif
+ return ret;
+}
+
+/*
+ * DS1 p.137: "There are a total of 13 different clocking modes..."
+ * ^^
+ * Design choices:
+ * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
+ * Clock mode 3b _should_ work but the testing seems to make this point
+ * dubious (DIY testing requires setting CCR0 at 0x00000033).
+ * This is supposed to provide least surprise "DTE like" behavior.
+ * - if line rate is specified, clocks are assumed to be locally generated.
+ * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
+ * between these it automagically done according on the required frequency
+ * scaling. Of course some rounding may take place.
+ * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
+ * appropriate external clocking device for testing.
+ * - no time-slot/clock mode 5: shameless lazyness.
+ *
+ * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
+ *
+ * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
+ * won't pass the init sequence. For example, straight back-to-back DTE without
+ * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
+ * called.
+ *
+ * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
+ * DS0 for example)
+ *
+ * Clock mode related bits of CCR0:
+ * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
+ * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
+ * | | +-------- High Speed: say 0
+ * | | | +-+-+-- Clock Mode: 0..7
+ * | | | | | |
+ * -+-+-+-+-+-+-+-+
+ * x|x|5|4|3|2|1|0| lower bits
+ *
+ * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
+ * +-+-+-+------------------ M (0..15)
+ * | | | | +-+-+-+-+-+-- N (0..63)
+ * 0 0 0 0 | | | | 0 0 | | | | | |
+ * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
+ *
+ */
+static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
+{
+ struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
+ int ret = -1;
+ u32 brr;
+
+ *state &= ~Ccr0ClockMask;
+ if (*bps) { /* Clock generated - required for DCE */
+ u32 n = 0, m = 0, divider;
+ int xtal;
+
+ xtal = dpriv->pci_priv->xtal_hz;
+ if (!xtal)
+ goto done;
+ if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
+ goto done;
+ divider = xtal / *bps;
+ if (divider > BRR_DIVIDER_MAX) {
+ divider >>= 4;
+ *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
+ } else
+ *state |= 0x00000037; /* Clock mode 7b (BRG) */
+ if (divider >> 22) {
+ n = 63;
+ m = 15;
+ } else if (divider) {
+ /* Extraction of the 6 highest weighted bits */
+ m = 0;
+ while (0xffffffc0 & divider) {
+ m++;
+ divider >>= 1;
+ }
+ n = divider;
+ }
+ brr = (m << 8) | n;
+ divider = n << m;
+ if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
+ divider <<= 4;
+ *bps = xtal / divider;
+ } else {
+ /*
+ * External clock - DTE
+ * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
+ * Nothing more to be done
+ */
+ brr = 0;
+ }
+ scc_writel(brr, dpriv, dev, BRR);
+ ret = 0;
+done:
+ return ret;
+}
+
+static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
+ struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
+ const size_t size = sizeof(dpriv->settings);
+ int ret = 0;
+
+ if (dev->flags & IFF_UP)
+ return -EBUSY;
+
+ if (cmd != SIOCWANDEV)
+ return -EOPNOTSUPP;
+
+ switch(ifr->ifr_settings.type) {
+ case IF_GET_IFACE:
+ ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
+ if (ifr->ifr_settings.size < size) {
+ ifr->ifr_settings.size = size; /* data size wanted */
+ return -ENOBUFS;
+ }
+ if (copy_to_user(line, &dpriv->settings, size))
+ return -EFAULT;
+ break;
+
+ case IF_IFACE_SYNC_SERIAL:
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ if (dpriv->flags & FakeReset) {
+ printk(KERN_INFO "%s: please reset the device"
+ " before this command\n", dev->name);
+ return -EPERM;
+ }
+ if (copy_from_user(&dpriv->settings, line, size))
+ return -EFAULT;
+ ret = dscc4_set_iface(dpriv, dev);
+ break;
+
+ default:
+ ret = hdlc_ioctl(dev, ifr, cmd);
+ break;
+ }
+
+ return ret;
+}
+
+static int dscc4_match(struct thingie *p, int value)
+{
+ int i;
+
+ for (i = 0; p[i].define != -1; i++) {
+ if (value == p[i].define)
+ break;
+ }
+ if (p[i].define == -1)
+ return -1;
+ else
+ return i;
+}
+
+static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ sync_serial_settings *settings = &dpriv->settings;
+ int ret = -EOPNOTSUPP;
+ u32 bps, state;
+
+ bps = settings->clock_rate;
+ state = scc_readl(dpriv, CCR0);
+ if (dscc4_set_clock(dev, &bps, &state) < 0)
+ goto done;
+ if (bps) { /* DCE */
+ printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
+ if (settings->clock_rate != bps) {
+ printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
+ dev->name, settings->clock_rate, bps);
+ settings->clock_rate = bps;
+ }
+ } else { /* DTE */
+ state |= PowerUp | Vis;
+ printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
+ }
+ scc_writel(state, dpriv, dev, CCR0);
+ ret = 0;
+done:
+ return ret;
+}
+
+static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ struct thingie encoding[] = {
+ { ENCODING_NRZ, 0x00000000 },
+ { ENCODING_NRZI, 0x00200000 },
+ { ENCODING_FM_MARK, 0x00400000 },
+ { ENCODING_FM_SPACE, 0x00500000 },
+ { ENCODING_MANCHESTER, 0x00600000 },
+ { -1, 0}
+ };
+ int i, ret = 0;
+
+ i = dscc4_match(encoding, dpriv->encoding);
+ if (i >= 0)
+ scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
+ else
+ ret = -EOPNOTSUPP;
+ return ret;
+}
+
+static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ sync_serial_settings *settings = &dpriv->settings;
+ u32 state;
+
+ state = scc_readl(dpriv, CCR1);
+ if (settings->loopback) {
+ printk(KERN_DEBUG "%s: loopback\n", dev->name);
+ state |= 0x00000100;
+ } else {
+ printk(KERN_DEBUG "%s: normal\n", dev->name);
+ state &= ~0x00000100;
+ }
+ scc_writel(state, dpriv, dev, CCR1);
+ return 0;
+}
+
+static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
+ struct net_device *dev)
+{
+ struct thingie crc[] = {
+ { PARITY_CRC16_PR0_CCITT, 0x00000010 },
+ { PARITY_CRC16_PR1_CCITT, 0x00000000 },
+ { PARITY_CRC32_PR0_CCITT, 0x00000011 },
+ { PARITY_CRC32_PR1_CCITT, 0x00000001 }
+ };
+ int i, ret = 0;
+
+ i = dscc4_match(crc, dpriv->parity);
+ if (i >= 0)
+ scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
+ else
+ ret = -EOPNOTSUPP;
+ return ret;
+}
+
+static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
+{
+ struct {
+ int (*action)(struct dscc4_dev_priv *, struct net_device *);
+ } *p, do_setting[] = {
+ { dscc4_encoding_setting },
+ { dscc4_clock_setting },
+ { dscc4_loopback_setting },
+ { dscc4_crc_setting },
+ { NULL }
+ };
+ int ret = 0;
+
+ for (p = do_setting; p->action; p++) {
+ if ((ret = p->action(dpriv, dev)) < 0)
+ break;
+ }
+ return ret;
+}
+
+static irqreturn_t dscc4_irq(int irq, void *token, struct pt_regs *ptregs)
+{
+ struct dscc4_dev_priv *root = token;
+ struct dscc4_pci_priv *priv;
+ struct net_device *dev;
+ void __iomem *ioaddr;
+ u32 state;
+ unsigned long flags;
+ int i, handled = 1;
+
+ priv = root->pci_priv;
+ dev = dscc4_to_dev(root);
+
+ spin_lock_irqsave(&priv->lock, flags);
+
+ ioaddr = root->base_addr;
+
+ state = readl(ioaddr + GSTAR);
+ if (!state) {
+ handled = 0;
+ goto out;
+ }
+ if (debug > 3)
+ printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
+ writel(state, ioaddr + GSTAR);
+
+ if (state & Arf) {
+ printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
+ dev->name);
+ goto out;
+ }
+ state &= ~ArAck;
+ if (state & Cfg) {
+ if (debug > 0)
+ printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
+ if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & Arf)
+ printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
+ if (!(state &= ~Cfg))
+ goto out;
+ }
+ if (state & RxEvt) {
+ i = dev_per_card - 1;
+ do {
+ dscc4_rx_irq(priv, root + i);
+ } while (--i >= 0);
+ state &= ~RxEvt;
+ }
+ if (state & TxEvt) {
+ i = dev_per_card - 1;
+ do {
+ dscc4_tx_irq(priv, root + i);
+ } while (--i >= 0);
+ state &= ~TxEvt;
+ }
+out:
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return IRQ_RETVAL(handled);
+}
+
+static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
+ struct dscc4_dev_priv *dpriv)
+{
+ struct net_device *dev = dscc4_to_dev(dpriv);
+ u32 state;
+ int cur, loop = 0;
+
+try:
+ cur = dpriv->iqtx_current%IRQ_RING_SIZE;
+ state = dpriv->iqtx[cur];
+ if (!state) {
+ if (debug > 4)
+ printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
+ state);
+ if ((debug > 1) && (loop > 1))
+ printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
+ if (loop && netif_queue_stopped(dev))
+ if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
+ netif_wake_queue(dev);
+
+ if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
+ !dscc4_tx_done(dpriv))
+ dscc4_do_tx(dpriv, dev);
+ return;
+ }
+ loop++;
+ dpriv->iqtx[cur] = 0;
+ dpriv->iqtx_current++;
+
+ if (state_check(state, dpriv, dev, "Tx") < 0)
+ return;
+
+ if (state & SccEvt) {
+ if (state & Alls) {
+ struct net_device_stats *stats = hdlc_stats(dev);
+ struct sk_buff *skb;
+ struct TxFD *tx_fd;
+
+ if (debug > 2)
+ dscc4_tx_print(dev, dpriv, "Alls");
+ /*
+ * DataComplete can't be trusted for Tx completion.
+ * Cf errata DS5 p.8
+ */
+ cur = dpriv->tx_dirty%TX_RING_SIZE;
+ tx_fd = dpriv->tx_fd + cur;
+ skb = dpriv->tx_skbuff[cur];
+ if (skb) {
+ pci_unmap_single(ppriv->pdev, tx_fd->data,
+ skb->len, PCI_DMA_TODEVICE);
+ if (tx_fd->state & FrameEnd) {
+ stats->tx_packets++;
+ stats->tx_bytes += skb->len;
+ }
+ dev_kfree_skb_irq(skb);
+ dpriv->tx_skbuff[cur] = NULL;
+ ++dpriv->tx_dirty;
+ } else {
+ if (debug > 1)
+ printk(KERN_ERR "%s Tx: NULL skb %d\n",
+ dev->name, cur);
+ }
+ /*
+ * If the driver ends sending crap on the wire, it
+ * will be way easier to diagnose than the (not so)
+ * random freeze induced by null sized tx frames.
+ */
+ tx_fd->data = tx_fd->next;
+ tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
+ tx_fd->complete = 0x00000000;
+ tx_fd->jiffies = 0;
+
+ if (!(state &= ~Alls))
+ goto try;
+ }
+ /*
+ * Transmit Data Underrun
+ */
+ if (state & Xdu) {
+ printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
+ dpriv->flags = NeedIDT;
+ /* Tx reset */
+ writel(MTFi | Rdt,
+ dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
+ writel(Action, dpriv->base_addr + GCMDR);
+ return;
+ }
+ if (state & Cts) {
+ printk(KERN_INFO "%s: CTS transition\n", dev->name);
+ if (!(state &= ~Cts)) /* DEBUG */
+ goto try;
+ }
+ if (state & Xmr) {
+ /* Frame needs to be sent again - FIXME */
+ printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
+ if (!(state &= ~Xmr)) /* DEBUG */
+ goto try;
+ }
+ if (state & Xpr) {
+ void __iomem *scc_addr;
+ unsigned long ring;
+ int i;
+
+ /*
+ * - the busy condition happens (sometimes);
+ * - it doesn't seem to make the handler unreliable.
+ */
+ for (i = 1; i; i <<= 1) {
+ if (!(scc_readl_star(dpriv, dev) & SccBusy))
+ break;
+ }
+ if (!i)
+ printk(KERN_INFO "%s busy in irq\n", dev->name);
+
+ scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
+ /* Keep this order: IDT before IDR */
+ if (dpriv->flags & NeedIDT) {
+ if (debug > 2)
+ dscc4_tx_print(dev, dpriv, "Xpr");
+ ring = dpriv->tx_fd_dma +
+ (dpriv->tx_dirty%TX_RING_SIZE)*
+ sizeof(struct TxFD);
+ writel(ring, scc_addr + CH0BTDA);
+ dscc4_do_tx(dpriv, dev);
+ writel(MTFi | Idt, scc_addr + CH0CFG);
+ if (dscc4_do_action(dev, "IDT") < 0)
+ goto err_xpr;
+ dpriv->flags &= ~NeedIDT;
+ }
+ if (dpriv->flags & NeedIDR) {
+ ring = dpriv->rx_fd_dma +
+ (dpriv->rx_current%RX_RING_SIZE)*
+ sizeof(struct RxFD);
+ writel(ring, scc_addr + CH0BRDA);
+ dscc4_rx_update(dpriv, dev);
+ writel(MTFi | Idr, scc_addr + CH0CFG);
+ if (dscc4_do_action(dev, "IDR") < 0)
+ goto err_xpr;
+ dpriv->flags &= ~NeedIDR;
+ smp_wmb();
+ /* Activate receiver and misc */
+ scc_writel(0x08050008, dpriv, dev, CCR2);
+ }
+ err_xpr:
+ if (!(state &= ~Xpr))
+ goto try;
+ }
+ if (state & Cd) {
+ if (debug > 0)
+ printk(KERN_INFO "%s: CD transition\n", dev->name);
+ if (!(state &= ~Cd)) /* DEBUG */
+ goto try;
+ }
+ } else { /* ! SccEvt */
+ if (state & Hi) {
+#ifdef DSCC4_POLLING
+ while (!dscc4_tx_poll(dpriv, dev));
+#endif
+ printk(KERN_INFO "%s: Tx Hi\n", dev->name);
+ state &= ~Hi;
+ }
+ if (state & Err) {
+ printk(KERN_INFO "%s: Tx ERR\n", dev->name);
+ hdlc_stats(dev)->tx_errors++;
+ state &= ~Err;
+ }
+ }
+ goto try;
+}
+
+static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
+ struct dscc4_dev_priv *dpriv)
+{
+ struct net_device *dev = dscc4_to_dev(dpriv);
+ u32 state;
+ int cur;
+
+try:
+ cur = dpriv->iqrx_current%IRQ_RING_SIZE;
+ state = dpriv->iqrx[cur];
+ if (!state)
+ return;
+ dpriv->iqrx[cur] = 0;
+ dpriv->iqrx_current++;
+
+ if (state_check(state, dpriv, dev, "Rx") < 0)
+ return;
+
+ if (!(state & SccEvt)){
+ struct RxFD *rx_fd;
+
+ if (debug > 4)
+ printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
+ state);
+ state &= 0x00ffffff;
+ if (state & Err) { /* Hold or reset */
+ printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
+ cur = dpriv->rx_current%RX_RING_SIZE;
+ rx_fd = dpriv->rx_fd + cur;
+ /*
+ * Presume we're not facing a DMAC receiver reset.
+ * As We use the rx size-filtering feature of the
+ * DSCC4, the beginning of a new frame is waiting in
+ * the rx fifo. I bet a Receive Data Overflow will
+ * happen most of time but let's try and avoid it.
+ * Btw (as for RDO) if one experiences ERR whereas
+ * the system looks rather idle, there may be a
+ * problem with latency. In this case, increasing
+ * RX_RING_SIZE may help.
+ */
+ //while (dpriv->rx_needs_refill) {
+ while (!(rx_fd->state1 & Hold)) {
+ rx_fd++;
+ cur++;
+ if (!(cur = cur%RX_RING_SIZE))
+ rx_fd = dpriv->rx_fd;
+ }
+ //dpriv->rx_needs_refill--;
+ try_get_rx_skb(dpriv, dev);
+ if (!rx_fd->data)
+ goto try;
+ rx_fd->state1 &= ~Hold;
+ rx_fd->state2 = 0x00000000;
+ rx_fd->end = 0xbabeface;
+ //}
+ goto try;
+ }
+ if (state & Fi) {
+ dscc4_rx_skb(dpriv, dev);
+ goto try;
+ }
+ if (state & Hi ) { /* HI bit */
+ printk(KERN_INFO "%s: Rx Hi\n", dev->name);
+ state &= ~Hi;
+ goto try;
+ }
+ } else { /* SccEvt */
+ if (debug > 1) {
+ //FIXME: verifier la presence de tous les evenements
+ static struct {
+ u32 mask;
+ const char *irq_name;
+ } evts[] = {
+ { 0x00008000, "TIN"},
+ { 0x00000020, "RSC"},
+ { 0x00000010, "PCE"},
+ { 0x00000008, "PLLA"},
+ { 0, NULL}
+ }, *evt;
+
+ for (evt = evts; evt->irq_name; evt++) {
+ if (state & evt->mask) {
+ printk(KERN_DEBUG "%s: %s\n",
+ dev->name, evt->irq_name);
+ if (!(state &= ~evt->mask))
+ goto try;
+ }
+ }
+ } else {
+ if (!(state &= ~0x0000c03c))
+ goto try;
+ }
+ if (state & Cts) {
+ printk(KERN_INFO "%s: CTS transition\n", dev->name);
+ if (!(state &= ~Cts)) /* DEBUG */
+ goto try;
+ }
+ /*
+ * Receive Data Overflow (FIXME: fscked)
+ */
+ if (state & Rdo) {
+ struct RxFD *rx_fd;
+ void __iomem *scc_addr;
+ int cur;
+
+ //if (debug)
+ // dscc4_rx_dump(dpriv);
+ scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
+
+ scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
+ /*
+ * This has no effect. Why ?
+ * ORed with TxSccRes, one sees the CFG ack (for
+ * the TX part only).
+ */
+ scc_writel(RxSccRes, dpriv, dev, CMDR);
+ dpriv->flags |= RdoSet;
+
+ /*
+ * Let's try and save something in the received data.
+ * rx_current must be incremented at least once to
+ * avoid HOLD in the BRDA-to-be-pointed desc.
+ */
+ do {
+ cur = dpriv->rx_current++%RX_RING_SIZE;
+ rx_fd = dpriv->rx_fd + cur;
+ if (!(rx_fd->state2 & DataComplete))
+ break;
+ if (rx_fd->state2 & FrameAborted) {
+ hdlc_stats(dev)->rx_over_errors++;
+ rx_fd->state1 |= Hold;
+ rx_fd->state2 = 0x00000000;
+ rx_fd->end = 0xbabeface;
+ } else
+ dscc4_rx_skb(dpriv, dev);
+ } while (1);
+
+ if (debug > 0) {
+ if (dpriv->flags & RdoSet)
+ printk(KERN_DEBUG
+ "%s: no RDO in Rx data\n", DRV_NAME);
+ }
+#ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
+ /*
+ * FIXME: must the reset be this violent ?
+ */
+#warning "FIXME: CH0BRDA"
+ writel(dpriv->rx_fd_dma +
+ (dpriv->rx_current%RX_RING_SIZE)*
+ sizeof(struct RxFD), scc_addr + CH0BRDA);
+ writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
+ if (dscc4_do_action(dev, "RDR") < 0) {
+ printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
+ dev->name, "RDR");
+ goto rdo_end;
+ }
+ writel(MTFi|Idr, scc_addr + CH0CFG);
+ if (dscc4_do_action(dev, "IDR") < 0) {
+ printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
+ dev->name, "IDR");
+ goto rdo_end;
+ }
+ rdo_end:
+#endif
+ scc_patchl(0, RxActivate, dpriv, dev, CCR2);
+ goto try;
+ }
+ if (state & Cd) {
+ printk(KERN_INFO "%s: CD transition\n", dev->name);
+ if (!(state &= ~Cd)) /* DEBUG */
+ goto try;
+ }
+ if (state & Flex) {
+ printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
+ if (!(state &= ~Flex))
+ goto try;
+ }
+ }
+}
+
+/*
+ * I had expected the following to work for the first descriptor
+ * (tx_fd->state = 0xc0000000)
+ * - Hold=1 (don't try and branch to the next descripto);
+ * - No=0 (I want an empty data section, i.e. size=0);
+ * - Fe=1 (required by No=0 or we got an Err irq and must reset).
+ * It failed and locked solid. Thus the introduction of a dummy skb.
+ * Problem is acknowledged in errata sheet DS5. Joy :o/
+ */
+struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
+{
+ struct sk_buff *skb;
+
+ skb = dev_alloc_skb(DUMMY_SKB_SIZE);
+ if (skb) {
+ int last = dpriv->tx_dirty%TX_RING_SIZE;
+ struct TxFD *tx_fd = dpriv->tx_fd + last;
+
+ skb->len = DUMMY_SKB_SIZE;
+ memcpy(skb->data, version, strlen(version)%DUMMY_SKB_SIZE);
+ tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
+ tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
+ DUMMY_SKB_SIZE, PCI_DMA_TODEVICE);
+ dpriv->tx_skbuff[last] = skb;
+ }
+ return skb;
+}
+
+static int dscc4_init_ring(struct net_device *dev)
+{
+ struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
+ struct pci_dev *pdev = dpriv->pci_priv->pdev;
+ struct TxFD *tx_fd;
+ struct RxFD *rx_fd;
+ void *ring;
+ int i;
+
+ ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
+ if (!ring)
+ goto err_out;
+ dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
+
+ ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
+ if (!ring)
+ goto err_free_dma_rx;
+ dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
+
+ memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
+ dpriv->tx_dirty = 0xffffffff;
+ i = dpriv->tx_current = 0;
+ do {
+ tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
+ tx_fd->complete = 0x00000000;
+ /* FIXME: NULL should be ok - to be tried */
+ tx_fd->data = dpriv->tx_fd_dma;
+ (tx_fd++)->next = (u32)(dpriv->tx_fd_dma +
+ (++i%TX_RING_SIZE)*sizeof(*tx_fd));
+ } while (i < TX_RING_SIZE);
+
+ if (dscc4_init_dummy_skb(dpriv) < 0)
+ goto err_free_dma_tx;
+
+ memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
+ i = dpriv->rx_dirty = dpriv->rx_current = 0;
+ do {
+ /* size set by the host. Multiple of 4 bytes please */
+ rx_fd->state1 = HiDesc;
+ rx_fd->state2 = 0x00000000;
+ rx_fd->end = 0xbabeface;
+ rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
+ // FIXME: return value verifiee mais traitement suspect
+ if (try_get_rx_skb(dpriv, dev) >= 0)
+ dpriv->rx_dirty++;
+ (rx_fd++)->next = (u32)(dpriv->rx_fd_dma +
+ (++i%RX_RING_SIZE)*sizeof(*rx_fd));
+ } while (i < RX_RING_SIZE);
+
+ return 0;
+
+err_free_dma_tx:
+ pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
+err_free_dma_rx:
+ pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
+err_out:
+ return -ENOMEM;
+}
+
+static void __devexit dscc4_remove_one(struct pci_dev *pdev)
+{
+ struct dscc4_pci_priv *ppriv;
+ struct dscc4_dev_priv *root;
+ void __iomem *ioaddr;
+ int i;
+
+ ppriv = pci_get_drvdata(pdev);
+ root = ppriv->root;
+
+ ioaddr = root->base_addr;
+
+ dscc4_pci_reset(pdev, ioaddr);
+
+ free_irq(pdev->irq, root);
+ pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
+ ppriv->iqcfg_dma);
+ for (i = 0; i < dev_per_card; i++) {
+ struct dscc4_dev_priv *dpriv = root + i;
+
+ dscc4_release_ring(dpriv);
+ pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
+ dpriv->iqrx, dpriv->iqrx_dma);
+ pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
+ dpriv->iqtx, dpriv->iqtx_dma);
+ }
+
+ dscc4_free1(pdev);
+
+ iounmap(ioaddr);
+
+ pci_release_region(pdev, 1);
+ pci_release_region(pdev, 0);
+
+ pci_disable_device(pdev);
+}
+
+static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
+ unsigned short parity)
+{
+ struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
+
+ if (encoding != ENCODING_NRZ &&
+ encoding != ENCODING_NRZI &&
+ encoding != ENCODING_FM_MARK &&
+ encoding != ENCODING_FM_SPACE &&
+ encoding != ENCODING_MANCHESTER)
+ return -EINVAL;
+
+ if (parity != PARITY_NONE &&
+ parity != PARITY_CRC16_PR0_CCITT &&
+ parity != PARITY_CRC16_PR1_CCITT &&
+ parity != PARITY_CRC32_PR0_CCITT &&
+ parity != PARITY_CRC32_PR1_CCITT)
+ return -EINVAL;
+
+ dpriv->encoding = encoding;
+ dpriv->parity = parity;
+ return 0;
+}
+
+#ifndef MODULE
+static int __init dscc4_setup(char *str)
+{
+ int *args[] = { &debug, &quartz, NULL }, **p = args;
+
+ while (*p && (get_option(&str, *p) == 2))
+ p++;
+ return 1;
+}
+
+__setup("dscc4.setup=", dscc4_setup);
+#endif
+
+static struct pci_device_id dscc4_pci_tbl[] = {
+ { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
+ PCI_ANY_ID, PCI_ANY_ID, },
+ { 0,}
+};
+MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
+
+static struct pci_driver dscc4_driver = {
+ .name = DRV_NAME,
+ .id_table = dscc4_pci_tbl,
+ .probe = dscc4_init_one,
+ .remove = __devexit_p(dscc4_remove_one),
+};
+
+static int __init dscc4_init_module(void)
+{
+ return pci_module_init(&dscc4_driver);
+}
+
+static void __exit dscc4_cleanup_module(void)
+{
+ pci_unregister_driver(&dscc4_driver);
+}
+
+module_init(dscc4_init_module);
+module_exit(dscc4_cleanup_module);
diff --git a/drivers/net/wan/farsync.c b/drivers/net/wan/farsync.c
new file mode 100644
index 000000000000..7575b799ce53
--- /dev/null
+++ b/drivers/net/wan/farsync.c
@@ -0,0 +1,2712 @@
+/*
+ * FarSync WAN driver for Linux (2.6.x kernel version)
+ *
+ * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
+ *
+ * Copyright (C) 2001-2004 FarSite Communications Ltd.
+ * www.farsite.co.uk
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Author: R.J.Dunlop
+ * Maintainer: Kevin Curtis
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "farsync.h"
+
+/*
+ * Module info
+ */
+MODULE_AUTHOR("R.J.Dunlop ");
+MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
+MODULE_LICENSE("GPL");
+
+/* Driver configuration and global parameters
+ * ==========================================
+ */
+
+/* Number of ports (per card) and cards supported
+ */
+#define FST_MAX_PORTS 4
+#define FST_MAX_CARDS 32
+
+/* Default parameters for the link
+ */
+#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
+ * useful, the syncppp module forces
+ * this down assuming a slower line I
+ * guess.
+ */
+#define FST_TXQ_DEPTH 16 /* This one is for the buffering
+ * of frames on the way down to the card
+ * so that we can keep the card busy
+ * and maximise throughput
+ */
+#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
+ * network layer */
+#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
+ * control from network layer */
+#define FST_MAX_MTU 8000 /* Huge but possible */
+#define FST_DEF_MTU 1500 /* Common sane value */
+
+#define FST_TX_TIMEOUT (2*HZ)
+
+#ifdef ARPHRD_RAWHDLC
+#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
+#else
+#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
+#endif
+
+/*
+ * Modules parameters and associated varaibles
+ */
+int fst_txq_low = FST_LOW_WATER_MARK;
+int fst_txq_high = FST_HIGH_WATER_MARK;
+int fst_max_reads = 7;
+int fst_excluded_cards = 0;
+int fst_excluded_list[FST_MAX_CARDS];
+
+module_param(fst_txq_low, int, 0);
+module_param(fst_txq_high, int, 0);
+module_param(fst_max_reads, int, 0);
+module_param(fst_excluded_cards, int, 0);
+module_param_array(fst_excluded_list, int, NULL, 0);
+
+/* Card shared memory layout
+ * =========================
+ */
+#pragma pack(1)
+
+/* This information is derived in part from the FarSite FarSync Smc.h
+ * file. Unfortunately various name clashes and the non-portability of the
+ * bit field declarations in that file have meant that I have chosen to
+ * recreate the information here.
+ *
+ * The SMC (Shared Memory Configuration) has a version number that is
+ * incremented every time there is a significant change. This number can
+ * be used to check that we have not got out of step with the firmware
+ * contained in the .CDE files.
+ */
+#define SMC_VERSION 24
+
+#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
+
+#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
+ * configuration structure */
+#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
+ * buffers */
+
+#define LEN_TX_BUFFER 8192 /* Size of packet buffers */
+#define LEN_RX_BUFFER 8192
+
+#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
+#define LEN_SMALL_RX_BUFFER 256
+
+#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
+#define NUM_RX_BUFFER 8
+
+/* Interrupt retry time in milliseconds */
+#define INT_RETRY_TIME 2
+
+/* The Am186CH/CC processors support a SmartDMA mode using circular pools
+ * of buffer descriptors. The structure is almost identical to that used
+ * in the LANCE Ethernet controllers. Details available as PDF from the
+ * AMD web site: http://www.amd.com/products/epd/processors/\
+ * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
+ */
+struct txdesc { /* Transmit descriptor */
+ volatile u16 ladr; /* Low order address of packet. This is a
+ * linear address in the Am186 memory space
+ */
+ volatile u8 hadr; /* High order address. Low 4 bits only, high 4
+ * bits must be zero
+ */
+ volatile u8 bits; /* Status and config */
+ volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
+ * Transmit terminal count interrupt enable in
+ * top bit.
+ */
+ u16 unused; /* Not used in Tx */
+};
+
+struct rxdesc { /* Receive descriptor */
+ volatile u16 ladr; /* Low order address of packet */
+ volatile u8 hadr; /* High order address */
+ volatile u8 bits; /* Status and config */
+ volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
+ * Receive terminal count interrupt enable in
+ * top bit.
+ */
+ volatile u16 mcnt; /* Message byte count (15 bits) */
+};
+
+/* Convert a length into the 15 bit 2's complement */
+/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
+/* Since we need to set the high bit to enable the completion interrupt this
+ * can be made a lot simpler
+ */
+#define cnv_bcnt(len) (-(len))
+
+/* Status and config bits for the above */
+#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
+#define TX_STP 0x02 /* Tx: start of packet */
+#define TX_ENP 0x01 /* Tx: end of packet */
+#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
+#define RX_FRAM 0x20 /* Rx: framing error */
+#define RX_OFLO 0x10 /* Rx: overflow error */
+#define RX_CRC 0x08 /* Rx: CRC error */
+#define RX_HBUF 0x04 /* Rx: buffer error */
+#define RX_STP 0x02 /* Rx: start of packet */
+#define RX_ENP 0x01 /* Rx: end of packet */
+
+/* Interrupts from the card are caused by various events which are presented
+ * in a circular buffer as several events may be processed on one physical int
+ */
+#define MAX_CIRBUFF 32
+
+struct cirbuff {
+ u8 rdindex; /* read, then increment and wrap */
+ u8 wrindex; /* write, then increment and wrap */
+ u8 evntbuff[MAX_CIRBUFF];
+};
+
+/* Interrupt event codes.
+ * Where appropriate the two low order bits indicate the port number
+ */
+#define CTLA_CHG 0x18 /* Control signal changed */
+#define CTLB_CHG 0x19
+#define CTLC_CHG 0x1A
+#define CTLD_CHG 0x1B
+
+#define INIT_CPLT 0x20 /* Initialisation complete */
+#define INIT_FAIL 0x21 /* Initialisation failed */
+
+#define ABTA_SENT 0x24 /* Abort sent */
+#define ABTB_SENT 0x25
+#define ABTC_SENT 0x26
+#define ABTD_SENT 0x27
+
+#define TXA_UNDF 0x28 /* Transmission underflow */
+#define TXB_UNDF 0x29
+#define TXC_UNDF 0x2A
+#define TXD_UNDF 0x2B
+
+#define F56_INT 0x2C
+#define M32_INT 0x2D
+
+#define TE1_ALMA 0x30
+
+/* Port physical configuration. See farsync.h for field values */
+struct port_cfg {
+ u16 lineInterface; /* Physical interface type */
+ u8 x25op; /* Unused at present */
+ u8 internalClock; /* 1 => internal clock, 0 => external */
+ u8 transparentMode; /* 1 => on, 0 => off */
+ u8 invertClock; /* 0 => normal, 1 => inverted */
+ u8 padBytes[6]; /* Padding */
+ u32 lineSpeed; /* Speed in bps */
+};
+
+/* TE1 port physical configuration */
+struct su_config {
+ u32 dataRate;
+ u8 clocking;
+ u8 framing;
+ u8 structure;
+ u8 interface;
+ u8 coding;
+ u8 lineBuildOut;
+ u8 equalizer;
+ u8 transparentMode;
+ u8 loopMode;
+ u8 range;
+ u8 txBufferMode;
+ u8 rxBufferMode;
+ u8 startingSlot;
+ u8 losThreshold;
+ u8 enableIdleCode;
+ u8 idleCode;
+ u8 spare[44];
+};
+
+/* TE1 Status */
+struct su_status {
+ u32 receiveBufferDelay;
+ u32 framingErrorCount;
+ u32 codeViolationCount;
+ u32 crcErrorCount;
+ u32 lineAttenuation;
+ u8 portStarted;
+ u8 lossOfSignal;
+ u8 receiveRemoteAlarm;
+ u8 alarmIndicationSignal;
+ u8 spare[40];
+};
+
+/* Finally sling all the above together into the shared memory structure.
+ * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
+ * evolving under NT for some time so I guess we're stuck with it.
+ * The structure starts at offset SMC_BASE.
+ * See farsync.h for some field values.
+ */
+struct fst_shared {
+ /* DMA descriptor rings */
+ struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
+ struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
+
+ /* Obsolete small buffers */
+ u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
+ u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
+
+ u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
+ * 0xFF => halted
+ */
+
+ u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
+ * set to 0xEE by host to acknowledge interrupt
+ */
+
+ u16 smcVersion; /* Must match SMC_VERSION */
+
+ u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
+ * version, RR = revision and BB = build
+ */
+
+ u16 txa_done; /* Obsolete completion flags */
+ u16 rxa_done;
+ u16 txb_done;
+ u16 rxb_done;
+ u16 txc_done;
+ u16 rxc_done;
+ u16 txd_done;
+ u16 rxd_done;
+
+ u16 mailbox[4]; /* Diagnostics mailbox. Not used */
+
+ struct cirbuff interruptEvent; /* interrupt causes */
+
+ u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
+ u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
+
+ struct port_cfg portConfig[FST_MAX_PORTS];
+
+ u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
+
+ u16 cableStatus; /* lsb: 0=> present, 1=> absent */
+
+ u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
+ u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
+
+ u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
+ u16 cardMailbox[4]; /* Not used */
+
+ /* Number of times the card thinks the host has
+ * missed an interrupt by not acknowledging
+ * within 2mS (I guess NT has problems)
+ */
+ u32 interruptRetryCount;
+
+ /* Driver private data used as an ID. We'll not
+ * use this as I'd rather keep such things
+ * in main memory rather than on the PCI bus
+ */
+ u32 portHandle[FST_MAX_PORTS];
+
+ /* Count of Tx underflows for stats */
+ u32 transmitBufferUnderflow[FST_MAX_PORTS];
+
+ /* Debounced V.24 control input status */
+ u32 v24DebouncedSts[FST_MAX_PORTS];
+
+ /* Adapter debounce timers. Don't touch */
+ u32 ctsTimer[FST_MAX_PORTS];
+ u32 ctsTimerRun[FST_MAX_PORTS];
+ u32 dcdTimer[FST_MAX_PORTS];
+ u32 dcdTimerRun[FST_MAX_PORTS];
+
+ u32 numberOfPorts; /* Number of ports detected at startup */
+
+ u16 _reserved[64];
+
+ u16 cardMode; /* Bit-mask to enable features:
+ * Bit 0: 1 enables LED identify mode
+ */
+
+ u16 portScheduleOffset;
+
+ struct su_config suConfig; /* TE1 Bits */
+ struct su_status suStatus;
+
+ u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
+ * the structure and marks the end of shared
+ * memory. Adapter code initializes it as
+ * END_SIG.
+ */
+};
+
+/* endOfSmcSignature value */
+#define END_SIG 0x12345678
+
+/* Mailbox values. (portMailbox) */
+#define NOP 0 /* No operation */
+#define ACK 1 /* Positive acknowledgement to PC driver */
+#define NAK 2 /* Negative acknowledgement to PC driver */
+#define STARTPORT 3 /* Start an HDLC port */
+#define STOPPORT 4 /* Stop an HDLC port */
+#define ABORTTX 5 /* Abort the transmitter for a port */
+#define SETV24O 6 /* Set V24 outputs */
+
+/* PLX Chip Register Offsets */
+#define CNTRL_9052 0x50 /* Control Register */
+#define CNTRL_9054 0x6c /* Control Register */
+
+#define INTCSR_9052 0x4c /* Interrupt control/status register */
+#define INTCSR_9054 0x68 /* Interrupt control/status register */
+
+/* 9054 DMA Registers */
+/*
+ * Note that we will be using DMA Channel 0 for copying rx data
+ * and Channel 1 for copying tx data
+ */
+#define DMAMODE0 0x80
+#define DMAPADR0 0x84
+#define DMALADR0 0x88
+#define DMASIZ0 0x8c
+#define DMADPR0 0x90
+#define DMAMODE1 0x94
+#define DMAPADR1 0x98
+#define DMALADR1 0x9c
+#define DMASIZ1 0xa0
+#define DMADPR1 0xa4
+#define DMACSR0 0xa8
+#define DMACSR1 0xa9
+#define DMAARB 0xac
+#define DMATHR 0xb0
+#define DMADAC0 0xb4
+#define DMADAC1 0xb8
+#define DMAMARBR 0xac
+
+#define FST_MIN_DMA_LEN 64
+#define FST_RX_DMA_INT 0x01
+#define FST_TX_DMA_INT 0x02
+#define FST_CARD_INT 0x04
+
+/* Larger buffers are positioned in memory at offset BFM_BASE */
+struct buf_window {
+ u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
+ u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
+};
+
+/* Calculate offset of a buffer object within the shared memory window */
+#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
+
+#pragma pack()
+
+/* Device driver private information
+ * =================================
+ */
+/* Per port (line or channel) information
+ */
+struct fst_port_info {
+ struct net_device *dev; /* Device struct - must be first */
+ struct fst_card_info *card; /* Card we're associated with */
+ int index; /* Port index on the card */
+ int hwif; /* Line hardware (lineInterface copy) */
+ int run; /* Port is running */
+ int mode; /* Normal or FarSync raw */
+ int rxpos; /* Next Rx buffer to use */
+ int txpos; /* Next Tx buffer to use */
+ int txipos; /* Next Tx buffer to check for free */
+ int start; /* Indication of start/stop to network */
+ /*
+ * A sixteen entry transmit queue
+ */
+ int txqs; /* index to get next buffer to tx */
+ int txqe; /* index to queue next packet */
+ struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
+ int rxqdepth;
+};
+
+/* Per card information
+ */
+struct fst_card_info {
+ char __iomem *mem; /* Card memory mapped to kernel space */
+ char __iomem *ctlmem; /* Control memory for PCI cards */
+ unsigned int phys_mem; /* Physical memory window address */
+ unsigned int phys_ctlmem; /* Physical control memory address */
+ unsigned int irq; /* Interrupt request line number */
+ unsigned int nports; /* Number of serial ports */
+ unsigned int type; /* Type index of card */
+ unsigned int state; /* State of card */
+ spinlock_t card_lock; /* Lock for SMP access */
+ unsigned short pci_conf; /* PCI card config in I/O space */
+ /* Per port info */
+ struct fst_port_info ports[FST_MAX_PORTS];
+ struct pci_dev *device; /* Information about the pci device */
+ int card_no; /* Inst of the card on the system */
+ int family; /* TxP or TxU */
+ int dmarx_in_progress;
+ int dmatx_in_progress;
+ unsigned long int_count;
+ unsigned long int_time_ave;
+ void *rx_dma_handle_host;
+ dma_addr_t rx_dma_handle_card;
+ void *tx_dma_handle_host;
+ dma_addr_t tx_dma_handle_card;
+ struct sk_buff *dma_skb_rx;
+ struct fst_port_info *dma_port_rx;
+ struct fst_port_info *dma_port_tx;
+ int dma_len_rx;
+ int dma_len_tx;
+ int dma_txpos;
+ int dma_rxpos;
+};
+
+/* Convert an HDLC device pointer into a port info pointer and similar */
+#define dev_to_port(D) (dev_to_hdlc(D)->priv)
+#define port_to_dev(P) ((P)->dev)
+
+
+/*
+ * Shared memory window access macros
+ *
+ * We have a nice memory based structure above, which could be directly
+ * mapped on i386 but might not work on other architectures unless we use
+ * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
+ * physical offsets so we have to convert. The only saving grace is that
+ * this should all collapse back to a simple indirection eventually.
+ */
+#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
+
+#define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
+#define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
+#define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
+
+#define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
+#define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
+#define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
+
+/*
+ * Debug support
+ */
+#if FST_DEBUG
+
+static int fst_debug_mask = { FST_DEBUG };
+
+/* Most common debug activity is to print something if the corresponding bit
+ * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
+ * support variable numbers of macro parameters. The inverted if prevents us
+ * eating someone else's else clause.
+ */
+#define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \
+ ; \
+ else \
+ printk ( KERN_DEBUG FST_NAME ": " fmt, ## A )
+
+#else
+#define dbg(X...) /* NOP */
+#endif
+
+/* Printing short cuts
+ */
+#define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A )
+#define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A )
+#define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A )
+
+/*
+ * PCI ID lookup table
+ */
+static struct pci_device_id fst_pci_dev_id[] __devinitdata = {
+ {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
+ PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
+
+ {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
+ PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
+
+ {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
+ PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
+
+ {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
+ PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
+
+ {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
+ PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
+
+ {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
+ PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
+
+ {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
+ PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
+ {0,} /* End */
+};
+
+MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
+
+/*
+ * Device Driver Work Queues
+ *
+ * So that we don't spend too much time processing events in the
+ * Interrupt Service routine, we will declare a work queue per Card
+ * and make the ISR schedule a task in the queue for later execution.
+ * In the 2.4 Kernel we used to use the immediate queue for BH's
+ * Now that they are gone, tasklets seem to be much better than work
+ * queues.
+ */
+
+static void do_bottom_half_tx(struct fst_card_info *card);
+static void do_bottom_half_rx(struct fst_card_info *card);
+static void fst_process_tx_work_q(unsigned long work_q);
+static void fst_process_int_work_q(unsigned long work_q);
+
+DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
+DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
+
+struct fst_card_info *fst_card_array[FST_MAX_CARDS];
+spinlock_t fst_work_q_lock;
+u64 fst_work_txq;
+u64 fst_work_intq;
+
+static void
+fst_q_work_item(u64 * queue, int card_index)
+{
+ unsigned long flags;
+ u64 mask;
+
+ /*
+ * Grab the queue exclusively
+ */
+ spin_lock_irqsave(&fst_work_q_lock, flags);
+
+ /*
+ * Making an entry in the queue is simply a matter of setting
+ * a bit for the card indicating that there is work to do in the
+ * bottom half for the card. Note the limitation of 64 cards.
+ * That ought to be enough
+ */
+ mask = 1 << card_index;
+ *queue |= mask;
+ spin_unlock_irqrestore(&fst_work_q_lock, flags);
+}
+
+static void
+fst_process_tx_work_q(unsigned long /*void **/work_q)
+{
+ unsigned long flags;
+ u64 work_txq;
+ int i;
+
+ /*
+ * Grab the queue exclusively
+ */
+ dbg(DBG_TX, "fst_process_tx_work_q\n");
+ spin_lock_irqsave(&fst_work_q_lock, flags);
+ work_txq = fst_work_txq;
+ fst_work_txq = 0;
+ spin_unlock_irqrestore(&fst_work_q_lock, flags);
+
+ /*
+ * Call the bottom half for each card with work waiting
+ */
+ for (i = 0; i < FST_MAX_CARDS; i++) {
+ if (work_txq & 0x01) {
+ if (fst_card_array[i] != NULL) {
+ dbg(DBG_TX, "Calling tx bh for card %d\n", i);
+ do_bottom_half_tx(fst_card_array[i]);
+ }
+ }
+ work_txq = work_txq >> 1;
+ }
+}
+
+static void
+fst_process_int_work_q(unsigned long /*void **/work_q)
+{
+ unsigned long flags;
+ u64 work_intq;
+ int i;
+
+ /*
+ * Grab the queue exclusively
+ */
+ dbg(DBG_INTR, "fst_process_int_work_q\n");
+ spin_lock_irqsave(&fst_work_q_lock, flags);
+ work_intq = fst_work_intq;
+ fst_work_intq = 0;
+ spin_unlock_irqrestore(&fst_work_q_lock, flags);
+
+ /*
+ * Call the bottom half for each card with work waiting
+ */
+ for (i = 0; i < FST_MAX_CARDS; i++) {
+ if (work_intq & 0x01) {
+ if (fst_card_array[i] != NULL) {
+ dbg(DBG_INTR,
+ "Calling rx & tx bh for card %d\n", i);
+ do_bottom_half_rx(fst_card_array[i]);
+ do_bottom_half_tx(fst_card_array[i]);
+ }
+ }
+ work_intq = work_intq >> 1;
+ }
+}
+
+/* Card control functions
+ * ======================
+ */
+/* Place the processor in reset state
+ *
+ * Used to be a simple write to card control space but a glitch in the latest
+ * AMD Am186CH processor means that we now have to do it by asserting and de-
+ * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
+ * at offset 9052_CNTRL. Note the updates for the TXU.
+ */
+static inline void
+fst_cpureset(struct fst_card_info *card)
+{
+ unsigned char interrupt_line_register;
+ unsigned long j = jiffies + 1;
+ unsigned int regval;
+
+ if (card->family == FST_FAMILY_TXU) {
+ if (pci_read_config_byte
+ (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
+ dbg(DBG_ASS,
+ "Error in reading interrupt line register\n");
+ }
+ /*
+ * Assert PLX software reset and Am186 hardware reset
+ * and then deassert the PLX software reset but 186 still in reset
+ */
+ outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
+ outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
+ /*
+ * We are delaying here to allow the 9054 to reset itself
+ */
+ j = jiffies + 1;
+ while (jiffies < j)
+ /* Do nothing */ ;
+ outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
+ /*
+ * We are delaying here to allow the 9054 to reload its eeprom
+ */
+ j = jiffies + 1;
+ while (jiffies < j)
+ /* Do nothing */ ;
+ outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
+
+ if (pci_write_config_byte
+ (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
+ dbg(DBG_ASS,
+ "Error in writing interrupt line register\n");
+ }
+
+ } else {
+ regval = inl(card->pci_conf + CNTRL_9052);
+
+ outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
+ outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
+ }
+}
+
+/* Release the processor from reset
+ */
+static inline void
+fst_cpurelease(struct fst_card_info *card)
+{
+ if (card->family == FST_FAMILY_TXU) {
+ /*
+ * Force posted writes to complete
+ */
+ (void) readb(card->mem);
+
+ /*
+ * Release LRESET DO = 1
+ * Then release Local Hold, DO = 1
+ */
+ outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
+ outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
+ } else {
+ (void) readb(card->ctlmem);
+ }
+}
+
+/* Clear the cards interrupt flag
+ */
+static inline void
+fst_clear_intr(struct fst_card_info *card)
+{
+ if (card->family == FST_FAMILY_TXU) {
+ (void) readb(card->ctlmem);
+ } else {
+ /* Poke the appropriate PLX chip register (same as enabling interrupts)
+ */
+ outw(0x0543, card->pci_conf + INTCSR_9052);
+ }
+}
+
+/* Enable card interrupts
+ */
+static inline void
+fst_enable_intr(struct fst_card_info *card)
+{
+ if (card->family == FST_FAMILY_TXU) {
+ outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
+ } else {
+ outw(0x0543, card->pci_conf + INTCSR_9052);
+ }
+}
+
+/* Disable card interrupts
+ */
+static inline void
+fst_disable_intr(struct fst_card_info *card)
+{
+ if (card->family == FST_FAMILY_TXU) {
+ outl(0x00000000, card->pci_conf + INTCSR_9054);
+ } else {
+ outw(0x0000, card->pci_conf + INTCSR_9052);
+ }
+}
+
+/* Process the result of trying to pass a received frame up the stack
+ */
+static void
+fst_process_rx_status(int rx_status, char *name)
+{
+ switch (rx_status) {
+ case NET_RX_SUCCESS:
+ {
+ /*
+ * Nothing to do here
+ */
+ break;
+ }
+
+ case NET_RX_CN_LOW:
+ {
+ dbg(DBG_ASS, "%s: Receive Low Congestion\n", name);
+ break;
+ }
+
+ case NET_RX_CN_MOD:
+ {
+ dbg(DBG_ASS, "%s: Receive Moderate Congestion\n", name);
+ break;
+ }
+
+ case NET_RX_CN_HIGH:
+ {
+ dbg(DBG_ASS, "%s: Receive High Congestion\n", name);
+ break;
+ }
+
+ case NET_RX_DROP:
+ {
+ dbg(DBG_ASS, "%s: Received packet dropped\n", name);
+ break;
+ }
+ }
+}
+
+/* Initilaise DMA for PLX 9054
+ */
+static inline void
+fst_init_dma(struct fst_card_info *card)
+{
+ /*
+ * This is only required for the PLX 9054
+ */
+ if (card->family == FST_FAMILY_TXU) {
+ pci_set_master(card->device);
+ outl(0x00020441, card->pci_conf + DMAMODE0);
+ outl(0x00020441, card->pci_conf + DMAMODE1);
+ outl(0x0, card->pci_conf + DMATHR);
+ }
+}
+
+/* Tx dma complete interrupt
+ */
+static void
+fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
+ int len, int txpos)
+{
+ struct net_device *dev = port_to_dev(port);
+ struct net_device_stats *stats = hdlc_stats(dev);
+
+ /*
+ * Everything is now set, just tell the card to go
+ */
+ dbg(DBG_TX, "fst_tx_dma_complete\n");
+ FST_WRB(card, txDescrRing[port->index][txpos].bits,
+ DMA_OWN | TX_STP | TX_ENP);
+ stats->tx_packets++;
+ stats->tx_bytes += len;
+ dev->trans_start = jiffies;
+}
+
+/*
+ * Mark it for our own raw sockets interface
+ */
+static unsigned short farsync_type_trans(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ skb->dev = dev;
+ skb->mac.raw = skb->data;
+ skb->pkt_type = PACKET_HOST;
+ return htons(ETH_P_CUST);
+}
+
+/* Rx dma complete interrupt
+ */
+static void
+fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
+ int len, struct sk_buff *skb, int rxp)
+{
+ struct net_device *dev = port_to_dev(port);
+ struct net_device_stats *stats = hdlc_stats(dev);
+ int pi;
+ int rx_status;
+
+ dbg(DBG_TX, "fst_rx_dma_complete\n");
+ pi = port->index;
+ memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
+
+ /* Reset buffer descriptor */
+ FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
+
+ /* Update stats */
+ stats->rx_packets++;
+ stats->rx_bytes += len;
+
+ /* Push upstream */
+ dbg(DBG_RX, "Pushing the frame up the stack\n");
+ if (port->mode == FST_RAW)
+ skb->protocol = farsync_type_trans(skb, dev);
+ else
+ skb->protocol = hdlc_type_trans(skb, dev);
+ rx_status = netif_rx(skb);
+ fst_process_rx_status(rx_status, port_to_dev(port)->name);
+ if (rx_status == NET_RX_DROP)
+ stats->rx_dropped++;
+ dev->last_rx = jiffies;
+}
+
+/*
+ * Receive a frame through the DMA
+ */
+static inline void
+fst_rx_dma(struct fst_card_info *card, unsigned char *skb,
+ unsigned char *mem, int len)
+{
+ /*
+ * This routine will setup the DMA and start it
+ */
+
+ dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len);
+ if (card->dmarx_in_progress) {
+ dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
+ }
+
+ outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */
+ outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */
+ outl(len, card->pci_conf + DMASIZ0); /* for this length */
+ outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
+
+ /*
+ * We use the dmarx_in_progress flag to flag the channel as busy
+ */
+ card->dmarx_in_progress = 1;
+ outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
+}
+
+/*
+ * Send a frame through the DMA
+ */
+static inline void
+fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
+ unsigned char *mem, int len)
+{
+ /*
+ * This routine will setup the DMA and start it.
+ */
+
+ dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
+ if (card->dmatx_in_progress) {
+ dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
+ }
+
+ outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
+ outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
+ outl(len, card->pci_conf + DMASIZ1); /* for this length */
+ outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
+
+ /*
+ * We use the dmatx_in_progress to flag the channel as busy
+ */
+ card->dmatx_in_progress = 1;
+ outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
+}
+
+/* Issue a Mailbox command for a port.
+ * Note we issue them on a fire and forget basis, not expecting to see an
+ * error and not waiting for completion.
+ */
+static void
+fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
+{
+ struct fst_card_info *card;
+ unsigned short mbval;
+ unsigned long flags;
+ int safety;
+
+ card = port->card;
+ spin_lock_irqsave(&card->card_lock, flags);
+ mbval = FST_RDW(card, portMailbox[port->index][0]);
+
+ safety = 0;
+ /* Wait for any previous command to complete */
+ while (mbval > NAK) {
+ spin_unlock_irqrestore(&card->card_lock, flags);
+ schedule_timeout(1);
+ spin_lock_irqsave(&card->card_lock, flags);
+
+ if (++safety > 2000) {
+ printk_err("Mailbox safety timeout\n");
+ break;
+ }
+
+ mbval = FST_RDW(card, portMailbox[port->index][0]);
+ }
+ if (safety > 0) {
+ dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
+ }
+ if (mbval == NAK) {
+ dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
+ }
+
+ FST_WRW(card, portMailbox[port->index][0], cmd);
+
+ if (cmd == ABORTTX || cmd == STARTPORT) {
+ port->txpos = 0;
+ port->txipos = 0;
+ port->start = 0;
+ }
+
+ spin_unlock_irqrestore(&card->card_lock, flags);
+}
+
+/* Port output signals control
+ */
+static inline void
+fst_op_raise(struct fst_port_info *port, unsigned int outputs)
+{
+ outputs |= FST_RDL(port->card, v24OpSts[port->index]);
+ FST_WRL(port->card, v24OpSts[port->index], outputs);
+
+ if (port->run)
+ fst_issue_cmd(port, SETV24O);
+}
+
+static inline void
+fst_op_lower(struct fst_port_info *port, unsigned int outputs)
+{
+ outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
+ FST_WRL(port->card, v24OpSts[port->index], outputs);
+
+ if (port->run)
+ fst_issue_cmd(port, SETV24O);
+}
+
+/*
+ * Setup port Rx buffers
+ */
+static void
+fst_rx_config(struct fst_port_info *port)
+{
+ int i;
+ int pi;
+ unsigned int offset;
+ unsigned long flags;
+ struct fst_card_info *card;
+
+ pi = port->index;
+ card = port->card;
+ spin_lock_irqsave(&card->card_lock, flags);
+ for (i = 0; i < NUM_RX_BUFFER; i++) {
+ offset = BUF_OFFSET(rxBuffer[pi][i][0]);
+
+ FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
+ FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
+ FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
+ FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
+ FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
+ }
+ port->rxpos = 0;
+ spin_unlock_irqrestore(&card->card_lock, flags);
+}
+
+/*
+ * Setup port Tx buffers
+ */
+static void
+fst_tx_config(struct fst_port_info *port)
+{
+ int i;
+ int pi;
+ unsigned int offset;
+ unsigned long flags;
+ struct fst_card_info *card;
+
+ pi = port->index;
+ card = port->card;
+ spin_lock_irqsave(&card->card_lock, flags);
+ for (i = 0; i < NUM_TX_BUFFER; i++) {
+ offset = BUF_OFFSET(txBuffer[pi][i][0]);
+
+ FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
+ FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
+ FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
+ FST_WRB(card, txDescrRing[pi][i].bits, 0);
+ }
+ port->txpos = 0;
+ port->txipos = 0;
+ port->start = 0;
+ spin_unlock_irqrestore(&card->card_lock, flags);
+}
+
+/* TE1 Alarm change interrupt event
+ */
+static void
+fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
+{
+ u8 los;
+ u8 rra;
+ u8 ais;
+
+ los = FST_RDB(card, suStatus.lossOfSignal);
+ rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
+ ais = FST_RDB(card, suStatus.alarmIndicationSignal);
+
+ if (los) {
+ /*
+ * Lost the link
+ */
+ if (netif_carrier_ok(port_to_dev(port))) {
+ dbg(DBG_INTR, "Net carrier off\n");
+ netif_carrier_off(port_to_dev(port));
+ }
+ } else {
+ /*
+ * Link available
+ */
+ if (!netif_carrier_ok(port_to_dev(port))) {
+ dbg(DBG_INTR, "Net carrier on\n");
+ netif_carrier_on(port_to_dev(port));
+ }
+ }
+
+ if (los)
+ dbg(DBG_INTR, "Assert LOS Alarm\n");
+ else
+ dbg(DBG_INTR, "De-assert LOS Alarm\n");
+ if (rra)
+ dbg(DBG_INTR, "Assert RRA Alarm\n");
+ else
+ dbg(DBG_INTR, "De-assert RRA Alarm\n");
+
+ if (ais)
+ dbg(DBG_INTR, "Assert AIS Alarm\n");
+ else
+ dbg(DBG_INTR, "De-assert AIS Alarm\n");
+}
+
+/* Control signal change interrupt event
+ */
+static void
+fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
+{
+ int signals;
+
+ signals = FST_RDL(card, v24DebouncedSts[port->index]);
+
+ if (signals & (((port->hwif == X21) || (port->hwif == X21D))
+ ? IPSTS_INDICATE : IPSTS_DCD)) {
+ if (!netif_carrier_ok(port_to_dev(port))) {
+ dbg(DBG_INTR, "DCD active\n");
+ netif_carrier_on(port_to_dev(port));
+ }
+ } else {
+ if (netif_carrier_ok(port_to_dev(port))) {
+ dbg(DBG_INTR, "DCD lost\n");
+ netif_carrier_off(port_to_dev(port));
+ }
+ }
+}
+
+/* Log Rx Errors
+ */
+static void
+fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
+ unsigned char dmabits, int rxp, unsigned short len)
+{
+ struct net_device *dev = port_to_dev(port);
+ struct net_device_stats *stats = hdlc_stats(dev);
+
+ /*
+ * Increment the appropriate error counter
+ */
+ stats->rx_errors++;
+ if (dmabits & RX_OFLO) {
+ stats->rx_fifo_errors++;
+ dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
+ card->card_no, port->index, rxp);
+ }
+ if (dmabits & RX_CRC) {
+ stats->rx_crc_errors++;
+ dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
+ card->card_no, port->index);
+ }
+ if (dmabits & RX_FRAM) {
+ stats->rx_frame_errors++;
+ dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
+ card->card_no, port->index);
+ }
+ if (dmabits == (RX_STP | RX_ENP)) {
+ stats->rx_length_errors++;
+ dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
+ len, card->card_no, port->index);
+ }
+}
+
+/* Rx Error Recovery
+ */
+static void
+fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
+ unsigned char dmabits, int rxp, unsigned short len)
+{
+ int i;
+ int pi;
+
+ pi = port->index;
+ /*
+ * Discard buffer descriptors until we see the start of the
+ * next frame. Note that for long frames this could be in
+ * a subsequent interrupt.
+ */
+ i = 0;
+ while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
+ FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
+ rxp = (rxp+1) % NUM_RX_BUFFER;
+ if (++i > NUM_RX_BUFFER) {
+ dbg(DBG_ASS, "intr_rx: Discarding more bufs"
+ " than we have\n");
+ break;
+ }
+ dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
+ dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
+ }
+ dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
+
+ /* Discard the terminal buffer */
+ if (!(dmabits & DMA_OWN)) {
+ FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
+ rxp = (rxp+1) % NUM_RX_BUFFER;
+ }
+ port->rxpos = rxp;
+ return;
+
+}
+
+/* Rx complete interrupt
+ */
+static void
+fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
+{
+ unsigned char dmabits;
+ int pi;
+ int rxp;
+ int rx_status;
+ unsigned short len;
+ struct sk_buff *skb;
+ struct net_device *dev = port_to_dev(port);
+ struct net_device_stats *stats = hdlc_stats(dev);
+
+ /* Check we have a buffer to process */
+ pi = port->index;
+ rxp = port->rxpos;
+ dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
+ if (dmabits & DMA_OWN) {
+ dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
+ pi, rxp);
+ return;
+ }
+ if (card->dmarx_in_progress) {
+ return;
+ }
+
+ /* Get buffer length */
+ len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
+ /* Discard the CRC */
+ len -= 2;
+ if (len == 0) {
+ /*
+ * This seems to happen on the TE1 interface sometimes
+ * so throw the frame away and log the event.
+ */
+ printk_err("Frame received with 0 length. Card %d Port %d\n",
+ card->card_no, port->index);
+ /* Return descriptor to card */
+ FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
+
+ rxp = (rxp+1) % NUM_RX_BUFFER;
+ port->rxpos = rxp;
+ return;
+ }
+
+ /* Check buffer length and for other errors. We insist on one packet
+ * in one buffer. This simplifies things greatly and since we've
+ * allocated 8K it shouldn't be a real world limitation
+ */
+ dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
+ if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
+ fst_log_rx_error(card, port, dmabits, rxp, len);
+ fst_recover_rx_error(card, port, dmabits, rxp, len);
+ return;
+ }
+
+ /* Allocate SKB */
+ if ((skb = dev_alloc_skb(len)) == NULL) {
+ dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
+
+ stats->rx_dropped++;
+
+ /* Return descriptor to card */
+ FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
+
+ rxp = (rxp+1) % NUM_RX_BUFFER;
+ port->rxpos = rxp;
+ return;
+ }
+
+ /*
+ * We know the length we need to receive, len.
+ * It's not worth using the DMA for reads of less than
+ * FST_MIN_DMA_LEN
+ */
+
+ if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
+ memcpy_fromio(skb_put(skb, len),
+ card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
+ len);
+
+ /* Reset buffer descriptor */
+ FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
+
+ /* Update stats */
+ stats->rx_packets++;
+ stats->rx_bytes += len;
+
+ /* Push upstream */
+ dbg(DBG_RX, "Pushing frame up the stack\n");
+ if (port->mode == FST_RAW)
+ skb->protocol = farsync_type_trans(skb, dev);
+ else
+ skb->protocol = hdlc_type_trans(skb, dev);
+ rx_status = netif_rx(skb);
+ fst_process_rx_status(rx_status, port_to_dev(port)->name);
+ if (rx_status == NET_RX_DROP) {
+ stats->rx_dropped++;
+ }
+ dev->last_rx = jiffies;
+ } else {
+ card->dma_skb_rx = skb;
+ card->dma_port_rx = port;
+ card->dma_len_rx = len;
+ card->dma_rxpos = rxp;
+ fst_rx_dma(card, (char *) card->rx_dma_handle_card,
+ (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
+ }
+ if (rxp != port->rxpos) {
+ dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
+ dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
+ }
+ rxp = (rxp+1) % NUM_RX_BUFFER;
+ port->rxpos = rxp;
+}
+
+/*
+ * The bottom halfs to the ISR
+ *
+ */
+
+static void
+do_bottom_half_tx(struct fst_card_info *card)
+{
+ struct fst_port_info *port;
+ int pi;
+ int txq_length;
+ struct sk_buff *skb;
+ unsigned long flags;
+ struct net_device *dev;
+ struct net_device_stats *stats;
+
+ /*
+ * Find a free buffer for the transmit
+ * Step through each port on this card
+ */
+
+ dbg(DBG_TX, "do_bottom_half_tx\n");
+ for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
+ if (!port->run)
+ continue;
+
+ dev = port_to_dev(port);
+ stats = hdlc_stats(dev);
+ while (!
+ (FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
+ DMA_OWN)
+ && !(card->dmatx_in_progress)) {
+ /*
+ * There doesn't seem to be a txdone event per-se
+ * We seem to have to deduce it, by checking the DMA_OWN
+ * bit on the next buffer we think we can use
+ */
+ spin_lock_irqsave(&card->card_lock, flags);
+ if ((txq_length = port->txqe - port->txqs) < 0) {
+ /*
+ * This is the case where one has wrapped and the
+ * maths gives us a negative number
+ */
+ txq_length = txq_length + FST_TXQ_DEPTH;
+ }
+ spin_unlock_irqrestore(&card->card_lock, flags);
+ if (txq_length > 0) {
+ /*
+ * There is something to send
+ */
+ spin_lock_irqsave(&card->card_lock, flags);
+ skb = port->txq[port->txqs];
+ port->txqs++;
+ if (port->txqs == FST_TXQ_DEPTH) {
+ port->txqs = 0;
+ }
+ spin_unlock_irqrestore(&card->card_lock, flags);
+ /*
+ * copy the data and set the required indicators on the
+ * card.
+ */
+ FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
+ cnv_bcnt(skb->len));
+ if ((skb->len < FST_MIN_DMA_LEN)
+ || (card->family == FST_FAMILY_TXP)) {
+ /* Enqueue the packet with normal io */
+ memcpy_toio(card->mem +
+ BUF_OFFSET(txBuffer[pi]
+ [port->
+ txpos][0]),
+ skb->data, skb->len);
+ FST_WRB(card,
+ txDescrRing[pi][port->txpos].
+ bits,
+ DMA_OWN | TX_STP | TX_ENP);
+ stats->tx_packets++;
+ stats->tx_bytes += skb->len;
+ dev->trans_start = jiffies;
+ } else {
+ /* Or do it through dma */
+ memcpy(card->tx_dma_handle_host,
+ skb->data, skb->len);
+ card->dma_port_tx = port;
+ card->dma_len_tx = skb->len;
+ card->dma_txpos = port->txpos;
+ fst_tx_dma(card,
+ (char *) card->
+ tx_dma_handle_card,
+ (char *)
+ BUF_OFFSET(txBuffer[pi]
+ [port->txpos][0]),
+ skb->len);
+ }
+ if (++port->txpos >= NUM_TX_BUFFER)
+ port->txpos = 0;
+ /*
+ * If we have flow control on, can we now release it?
+ */
+ if (port->start) {
+ if (txq_length < fst_txq_low) {
+ netif_wake_queue(port_to_dev
+ (port));
+ port->start = 0;
+ }
+ }
+ dev_kfree_skb(skb);
+ } else {
+ /*
+ * Nothing to send so break out of the while loop
+ */
+ break;
+ }
+ }
+ }
+}
+
+static void
+do_bottom_half_rx(struct fst_card_info *card)
+{
+ struct fst_port_info *port;
+ int pi;
+ int rx_count = 0;
+
+ /* Check for rx completions on all ports on this card */
+ dbg(DBG_RX, "do_bottom_half_rx\n");
+ for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
+ if (!port->run)
+ continue;
+
+ while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
+ & DMA_OWN) && !(card->dmarx_in_progress)) {
+ if (rx_count > fst_max_reads) {
+ /*
+ * Don't spend forever in receive processing
+ * Schedule another event
+ */
+ fst_q_work_item(&fst_work_intq, card->card_no);
+ tasklet_schedule(&fst_int_task);
+ break; /* Leave the loop */
+ }
+ fst_intr_rx(card, port);
+ rx_count++;
+ }
+ }
+}
+
+/*
+ * The interrupt service routine
+ * Dev_id is our fst_card_info pointer
+ */
+irqreturn_t
+fst_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct fst_card_info *card;
+ struct fst_port_info *port;
+ int rdidx; /* Event buffer indices */
+ int wridx;
+ int event; /* Actual event for processing */
+ unsigned int dma_intcsr = 0;
+ unsigned int do_card_interrupt;
+ unsigned int int_retry_count;
+
+ if ((card = dev_id) == NULL) {
+ dbg(DBG_INTR, "intr: spurious %d\n", irq);
+ return IRQ_NONE;
+ }
+
+ /*
+ * Check to see if the interrupt was for this card
+ * return if not
+ * Note that the call to clear the interrupt is important
+ */
+ dbg(DBG_INTR, "intr: %d %p\n", irq, card);
+ if (card->state != FST_RUNNING) {
+ printk_err
+ ("Interrupt received for card %d in a non running state (%d)\n",
+ card->card_no, card->state);
+
+ /*
+ * It is possible to really be running, i.e. we have re-loaded
+ * a running card
+ * Clear and reprime the interrupt source
+ */
+ fst_clear_intr(card);
+ return IRQ_HANDLED;
+ }
+
+ /* Clear and reprime the interrupt source */
+ fst_clear_intr(card);
+
+ /*
+ * Is the interrupt for this card (handshake == 1)
+ */
+ do_card_interrupt = 0;
+ if (FST_RDB(card, interruptHandshake) == 1) {
+ do_card_interrupt += FST_CARD_INT;
+ /* Set the software acknowledge */
+ FST_WRB(card, interruptHandshake, 0xEE);
+ }
+ if (card->family == FST_FAMILY_TXU) {
+ /*
+ * Is it a DMA Interrupt
+ */
+ dma_intcsr = inl(card->pci_conf + INTCSR_9054);
+ if (dma_intcsr & 0x00200000) {
+ /*
+ * DMA Channel 0 (Rx transfer complete)
+ */
+ dbg(DBG_RX, "DMA Rx xfer complete\n");
+ outb(0x8, card->pci_conf + DMACSR0);
+ fst_rx_dma_complete(card, card->dma_port_rx,
+ card->dma_len_rx, card->dma_skb_rx,
+ card->dma_rxpos);
+ card->dmarx_in_progress = 0;
+ do_card_interrupt += FST_RX_DMA_INT;
+ }
+ if (dma_intcsr & 0x00400000) {
+ /*
+ * DMA Channel 1 (Tx transfer complete)
+ */
+ dbg(DBG_TX, "DMA Tx xfer complete\n");
+ outb(0x8, card->pci_conf + DMACSR1);
+ fst_tx_dma_complete(card, card->dma_port_tx,
+ card->dma_len_tx, card->dma_txpos);
+ card->dmatx_in_progress = 0;
+ do_card_interrupt += FST_TX_DMA_INT;
+ }
+ }
+
+ /*
+ * Have we been missing Interrupts
+ */
+ int_retry_count = FST_RDL(card, interruptRetryCount);
+ if (int_retry_count) {
+ dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
+ card->card_no, int_retry_count);
+ FST_WRL(card, interruptRetryCount, 0);
+ }
+
+ if (!do_card_interrupt) {
+ return IRQ_HANDLED;
+ }
+
+ /* Scehdule the bottom half of the ISR */
+ fst_q_work_item(&fst_work_intq, card->card_no);
+ tasklet_schedule(&fst_int_task);
+
+ /* Drain the event queue */
+ rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
+ wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
+ while (rdidx != wridx) {
+ event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
+ port = &card->ports[event & 0x03];
+
+ dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
+
+ switch (event) {
+ case TE1_ALMA:
+ dbg(DBG_INTR, "TE1 Alarm intr\n");
+ if (port->run)
+ fst_intr_te1_alarm(card, port);
+ break;
+
+ case CTLA_CHG:
+ case CTLB_CHG:
+ case CTLC_CHG:
+ case CTLD_CHG:
+ if (port->run)
+ fst_intr_ctlchg(card, port);
+ break;
+
+ case ABTA_SENT:
+ case ABTB_SENT:
+ case ABTC_SENT:
+ case ABTD_SENT:
+ dbg(DBG_TX, "Abort complete port %d\n", port->index);
+ break;
+
+ case TXA_UNDF:
+ case TXB_UNDF:
+ case TXC_UNDF:
+ case TXD_UNDF:
+ /* Difficult to see how we'd get this given that we
+ * always load up the entire packet for DMA.
+ */
+ dbg(DBG_TX, "Tx underflow port %d\n", port->index);
+ hdlc_stats(port_to_dev(port))->tx_errors++;
+ hdlc_stats(port_to_dev(port))->tx_fifo_errors++;
+ dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
+ card->card_no, port->index);
+ break;
+
+ case INIT_CPLT:
+ dbg(DBG_INIT, "Card init OK intr\n");
+ break;
+
+ case INIT_FAIL:
+ dbg(DBG_INIT, "Card init FAILED intr\n");
+ card->state = FST_IFAILED;
+ break;
+
+ default:
+ printk_err("intr: unknown card event %d. ignored\n",
+ event);
+ break;
+ }
+
+ /* Bump and wrap the index */
+ if (++rdidx >= MAX_CIRBUFF)
+ rdidx = 0;
+ }
+ FST_WRB(card, interruptEvent.rdindex, rdidx);
+ return IRQ_HANDLED;
+}
+
+/* Check that the shared memory configuration is one that we can handle
+ * and that some basic parameters are correct
+ */
+static void
+check_started_ok(struct fst_card_info *card)
+{
+ int i;
+
+ /* Check structure version and end marker */
+ if (FST_RDW(card, smcVersion) != SMC_VERSION) {
+ printk_err("Bad shared memory version %d expected %d\n",
+ FST_RDW(card, smcVersion), SMC_VERSION);
+ card->state = FST_BADVERSION;
+ return;
+ }
+ if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
+ printk_err("Missing shared memory signature\n");
+ card->state = FST_BADVERSION;
+ return;
+ }
+ /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
+ if ((i = FST_RDB(card, taskStatus)) == 0x01) {
+ card->state = FST_RUNNING;
+ } else if (i == 0xFF) {
+ printk_err("Firmware initialisation failed. Card halted\n");
+ card->state = FST_HALTED;
+ return;
+ } else if (i != 0x00) {
+ printk_err("Unknown firmware status 0x%x\n", i);
+ card->state = FST_HALTED;
+ return;
+ }
+
+ /* Finally check the number of ports reported by firmware against the
+ * number we assumed at card detection. Should never happen with
+ * existing firmware etc so we just report it for the moment.
+ */
+ if (FST_RDL(card, numberOfPorts) != card->nports) {
+ printk_warn("Port count mismatch on card %d."
+ " Firmware thinks %d we say %d\n", card->card_no,
+ FST_RDL(card, numberOfPorts), card->nports);
+ }
+}
+
+static int
+set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
+ struct fstioc_info *info)
+{
+ int err;
+ unsigned char my_framing;
+
+ /* Set things according to the user set valid flags
+ * Several of the old options have been invalidated/replaced by the
+ * generic hdlc package.
+ */
+ err = 0;
+ if (info->valid & FSTVAL_PROTO) {
+ if (info->proto == FST_RAW)
+ port->mode = FST_RAW;
+ else
+ port->mode = FST_GEN_HDLC;
+ }
+
+ if (info->valid & FSTVAL_CABLE)
+ err = -EINVAL;
+
+ if (info->valid & FSTVAL_SPEED)
+ err = -EINVAL;
+
+ if (info->valid & FSTVAL_PHASE)
+ FST_WRB(card, portConfig[port->index].invertClock,
+ info->invertClock);
+ if (info->valid & FSTVAL_MODE)
+ FST_WRW(card, cardMode, info->cardMode);
+ if (info->valid & FSTVAL_TE1) {
+ FST_WRL(card, suConfig.dataRate, info->lineSpeed);
+ FST_WRB(card, suConfig.clocking, info->clockSource);
+ my_framing = FRAMING_E1;
+ if (info->framing == E1)
+ my_framing = FRAMING_E1;
+ if (info->framing == T1)
+ my_framing = FRAMING_T1;
+ if (info->framing == J1)
+ my_framing = FRAMING_J1;
+ FST_WRB(card, suConfig.framing, my_framing);
+ FST_WRB(card, suConfig.structure, info->structure);
+ FST_WRB(card, suConfig.interface, info->interface);
+ FST_WRB(card, suConfig.coding, info->coding);
+ FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
+ FST_WRB(card, suConfig.equalizer, info->equalizer);
+ FST_WRB(card, suConfig.transparentMode, info->transparentMode);
+ FST_WRB(card, suConfig.loopMode, info->loopMode);
+ FST_WRB(card, suConfig.range, info->range);
+ FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
+ FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
+ FST_WRB(card, suConfig.startingSlot, info->startingSlot);
+ FST_WRB(card, suConfig.losThreshold, info->losThreshold);
+ if (info->idleCode)
+ FST_WRB(card, suConfig.enableIdleCode, 1);
+ else
+ FST_WRB(card, suConfig.enableIdleCode, 0);
+ FST_WRB(card, suConfig.idleCode, info->idleCode);
+#if FST_DEBUG
+ if (info->valid & FSTVAL_TE1) {
+ printk("Setting TE1 data\n");
+ printk("Line Speed = %d\n", info->lineSpeed);
+ printk("Start slot = %d\n", info->startingSlot);
+ printk("Clock source = %d\n", info->clockSource);
+ printk("Framing = %d\n", my_framing);
+ printk("Structure = %d\n", info->structure);
+ printk("interface = %d\n", info->interface);
+ printk("Coding = %d\n", info->coding);
+ printk("Line build out = %d\n", info->lineBuildOut);
+ printk("Equaliser = %d\n", info->equalizer);
+ printk("Transparent mode = %d\n",
+ info->transparentMode);
+ printk("Loop mode = %d\n", info->loopMode);
+ printk("Range = %d\n", info->range);
+ printk("Tx Buffer mode = %d\n", info->txBufferMode);
+ printk("Rx Buffer mode = %d\n", info->rxBufferMode);
+ printk("LOS Threshold = %d\n", info->losThreshold);
+ printk("Idle Code = %d\n", info->idleCode);
+ }
+#endif
+ }
+#if FST_DEBUG
+ if (info->valid & FSTVAL_DEBUG) {
+ fst_debug_mask = info->debug;
+ }
+#endif
+
+ return err;
+}
+
+static void
+gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
+ struct fstioc_info *info)
+{
+ int i;
+
+ memset(info, 0, sizeof (struct fstioc_info));
+
+ i = port->index;
+ info->kernelVersion = LINUX_VERSION_CODE;
+ info->nports = card->nports;
+ info->type = card->type;
+ info->state = card->state;
+ info->proto = FST_GEN_HDLC;
+ info->index = i;
+#if FST_DEBUG
+ info->debug = fst_debug_mask;
+#endif
+
+ /* Only mark information as valid if card is running.
+ * Copy the data anyway in case it is useful for diagnostics
+ */
+ info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
+#if FST_DEBUG
+ | FSTVAL_DEBUG
+#endif
+ ;
+
+ info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
+ info->internalClock = FST_RDB(card, portConfig[i].internalClock);
+ info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
+ info->invertClock = FST_RDB(card, portConfig[i].invertClock);
+ info->v24IpSts = FST_RDL(card, v24IpSts[i]);
+ info->v24OpSts = FST_RDL(card, v24OpSts[i]);
+ info->clockStatus = FST_RDW(card, clockStatus[i]);
+ info->cableStatus = FST_RDW(card, cableStatus);
+ info->cardMode = FST_RDW(card, cardMode);
+ info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
+
+ /*
+ * The T2U can report cable presence for both A or B
+ * in bits 0 and 1 of cableStatus. See which port we are and
+ * do the mapping.
+ */
+ if (card->family == FST_FAMILY_TXU) {
+ if (port->index == 0) {
+ /*
+ * Port A
+ */
+ info->cableStatus = info->cableStatus & 1;
+ } else {
+ /*
+ * Port B
+ */
+ info->cableStatus = info->cableStatus >> 1;
+ info->cableStatus = info->cableStatus & 1;
+ }
+ }
+ /*
+ * Some additional bits if we are TE1
+ */
+ if (card->type == FST_TYPE_TE1) {
+ info->lineSpeed = FST_RDL(card, suConfig.dataRate);
+ info->clockSource = FST_RDB(card, suConfig.clocking);
+ info->framing = FST_RDB(card, suConfig.framing);
+ info->structure = FST_RDB(card, suConfig.structure);
+ info->interface = FST_RDB(card, suConfig.interface);
+ info->coding = FST_RDB(card, suConfig.coding);
+ info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
+ info->equalizer = FST_RDB(card, suConfig.equalizer);
+ info->loopMode = FST_RDB(card, suConfig.loopMode);
+ info->range = FST_RDB(card, suConfig.range);
+ info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
+ info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
+ info->startingSlot = FST_RDB(card, suConfig.startingSlot);
+ info->losThreshold = FST_RDB(card, suConfig.losThreshold);
+ if (FST_RDB(card, suConfig.enableIdleCode))
+ info->idleCode = FST_RDB(card, suConfig.idleCode);
+ else
+ info->idleCode = 0;
+ info->receiveBufferDelay =
+ FST_RDL(card, suStatus.receiveBufferDelay);
+ info->framingErrorCount =
+ FST_RDL(card, suStatus.framingErrorCount);
+ info->codeViolationCount =
+ FST_RDL(card, suStatus.codeViolationCount);
+ info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
+ info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
+ info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
+ info->receiveRemoteAlarm =
+ FST_RDB(card, suStatus.receiveRemoteAlarm);
+ info->alarmIndicationSignal =
+ FST_RDB(card, suStatus.alarmIndicationSignal);
+ }
+}
+
+static int
+fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
+ struct ifreq *ifr)
+{
+ sync_serial_settings sync;
+ int i;
+
+ if (ifr->ifr_settings.size != sizeof (sync)) {
+ return -ENOMEM;
+ }
+
+ if (copy_from_user
+ (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
+ return -EFAULT;
+ }
+
+ if (sync.loopback)
+ return -EINVAL;
+
+ i = port->index;
+
+ switch (ifr->ifr_settings.type) {
+ case IF_IFACE_V35:
+ FST_WRW(card, portConfig[i].lineInterface, V35);
+ port->hwif = V35;
+ break;
+
+ case IF_IFACE_V24:
+ FST_WRW(card, portConfig[i].lineInterface, V24);
+ port->hwif = V24;
+ break;
+
+ case IF_IFACE_X21:
+ FST_WRW(card, portConfig[i].lineInterface, X21);
+ port->hwif = X21;
+ break;
+
+ case IF_IFACE_X21D:
+ FST_WRW(card, portConfig[i].lineInterface, X21D);
+ port->hwif = X21D;
+ break;
+
+ case IF_IFACE_T1:
+ FST_WRW(card, portConfig[i].lineInterface, T1);
+ port->hwif = T1;
+ break;
+
+ case IF_IFACE_E1:
+ FST_WRW(card, portConfig[i].lineInterface, E1);
+ port->hwif = E1;
+ break;
+
+ case IF_IFACE_SYNC_SERIAL:
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ switch (sync.clock_type) {
+ case CLOCK_EXT:
+ FST_WRB(card, portConfig[i].internalClock, EXTCLK);
+ break;
+
+ case CLOCK_INT:
+ FST_WRB(card, portConfig[i].internalClock, INTCLK);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
+ return 0;
+}
+
+static int
+fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
+ struct ifreq *ifr)
+{
+ sync_serial_settings sync;
+ int i;
+
+ /* First check what line type is set, we'll default to reporting X.21
+ * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
+ * changed
+ */
+ switch (port->hwif) {
+ case E1:
+ ifr->ifr_settings.type = IF_IFACE_E1;
+ break;
+ case T1:
+ ifr->ifr_settings.type = IF_IFACE_T1;
+ break;
+ case V35:
+ ifr->ifr_settings.type = IF_IFACE_V35;
+ break;
+ case V24:
+ ifr->ifr_settings.type = IF_IFACE_V24;
+ break;
+ case X21D:
+ ifr->ifr_settings.type = IF_IFACE_X21D;
+ break;
+ case X21:
+ default:
+ ifr->ifr_settings.type = IF_IFACE_X21;
+ break;
+ }
+ if (ifr->ifr_settings.size == 0) {
+ return 0; /* only type requested */
+ }
+ if (ifr->ifr_settings.size < sizeof (sync)) {
+ return -ENOMEM;
+ }
+
+ i = port->index;
+ sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
+ /* Lucky card and linux use same encoding here */
+ sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
+ INTCLK ? CLOCK_INT : CLOCK_EXT;
+ sync.loopback = 0;
+
+ if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
+ return -EFAULT;
+ }
+
+ ifr->ifr_settings.size = sizeof (sync);
+ return 0;
+}
+
+static int
+fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ struct fst_card_info *card;
+ struct fst_port_info *port;
+ struct fstioc_write wrthdr;
+ struct fstioc_info info;
+ unsigned long flags;
+
+ dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
+
+ port = dev_to_port(dev);
+ card = port->card;
+
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ switch (cmd) {
+ case FSTCPURESET:
+ fst_cpureset(card);
+ card->state = FST_RESET;
+ return 0;
+
+ case FSTCPURELEASE:
+ fst_cpurelease(card);
+ card->state = FST_STARTING;
+ return 0;
+
+ case FSTWRITE: /* Code write (download) */
+
+ /* First copy in the header with the length and offset of data
+ * to write
+ */
+ if (ifr->ifr_data == NULL) {
+ return -EINVAL;
+ }
+ if (copy_from_user(&wrthdr, ifr->ifr_data,
+ sizeof (struct fstioc_write))) {
+ return -EFAULT;
+ }
+
+ /* Sanity check the parameters. We don't support partial writes
+ * when going over the top
+ */
+ if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE
+ || wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
+ return -ENXIO;
+ }
+
+ /* Now copy the data to the card.
+ * This will probably break on some architectures.
+ * I'll fix it when I have something to test on.
+ */
+ if (copy_from_user(card->mem + wrthdr.offset,
+ ifr->ifr_data + sizeof (struct fstioc_write),
+ wrthdr.size)) {
+ return -EFAULT;
+ }
+
+ /* Writes to the memory of a card in the reset state constitute
+ * a download
+ */
+ if (card->state == FST_RESET) {
+ card->state = FST_DOWNLOAD;
+ }
+ return 0;
+
+ case FSTGETCONF:
+
+ /* If card has just been started check the shared memory config
+ * version and marker
+ */
+ if (card->state == FST_STARTING) {
+ check_started_ok(card);
+
+ /* If everything checked out enable card interrupts */
+ if (card->state == FST_RUNNING) {
+ spin_lock_irqsave(&card->card_lock, flags);
+ fst_enable_intr(card);
+ FST_WRB(card, interruptHandshake, 0xEE);
+ spin_unlock_irqrestore(&card->card_lock, flags);
+ }
+ }
+
+ if (ifr->ifr_data == NULL) {
+ return -EINVAL;
+ }
+
+ gather_conf_info(card, port, &info);
+
+ if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
+ return -EFAULT;
+ }
+ return 0;
+
+ case FSTSETCONF:
+
+ /*
+ * Most of the settings have been moved to the generic ioctls
+ * this just covers debug and board ident now
+ */
+
+ if (card->state != FST_RUNNING) {
+ printk_err
+ ("Attempt to configure card %d in non-running state (%d)\n",
+ card->card_no, card->state);
+ return -EIO;
+ }
+ if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
+ return -EFAULT;
+ }
+
+ return set_conf_from_info(card, port, &info);
+
+ case SIOCWANDEV:
+ switch (ifr->ifr_settings.type) {
+ case IF_GET_IFACE:
+ return fst_get_iface(card, port, ifr);
+
+ case IF_IFACE_SYNC_SERIAL:
+ case IF_IFACE_V35:
+ case IF_IFACE_V24:
+ case IF_IFACE_X21:
+ case IF_IFACE_X21D:
+ case IF_IFACE_T1:
+ case IF_IFACE_E1:
+ return fst_set_iface(card, port, ifr);
+
+ case IF_PROTO_RAW:
+ port->mode = FST_RAW;
+ return 0;
+
+ case IF_GET_PROTO:
+ if (port->mode == FST_RAW) {
+ ifr->ifr_settings.type = IF_PROTO_RAW;
+ return 0;
+ }
+ return hdlc_ioctl(dev, ifr, cmd);
+
+ default:
+ port->mode = FST_GEN_HDLC;
+ dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
+ ifr->ifr_settings.type);
+ return hdlc_ioctl(dev, ifr, cmd);
+ }
+
+ default:
+ /* Not one of ours. Pass through to HDLC package */
+ return hdlc_ioctl(dev, ifr, cmd);
+ }
+}
+
+static void
+fst_openport(struct fst_port_info *port)
+{
+ int signals;
+ int txq_length;
+
+ /* Only init things if card is actually running. This allows open to
+ * succeed for downloads etc.
+ */
+ if (port->card->state == FST_RUNNING) {
+ if (port->run) {
+ dbg(DBG_OPEN, "open: found port already running\n");
+
+ fst_issue_cmd(port, STOPPORT);
+ port->run = 0;
+ }
+
+ fst_rx_config(port);
+ fst_tx_config(port);
+ fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
+
+ fst_issue_cmd(port, STARTPORT);
+ port->run = 1;
+
+ signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
+ if (signals & (((port->hwif == X21) || (port->hwif == X21D))
+ ? IPSTS_INDICATE : IPSTS_DCD))
+ netif_carrier_on(port_to_dev(port));
+ else
+ netif_carrier_off(port_to_dev(port));
+
+ txq_length = port->txqe - port->txqs;
+ port->txqe = 0;
+ port->txqs = 0;
+ }
+
+}
+
+static void
+fst_closeport(struct fst_port_info *port)
+{
+ if (port->card->state == FST_RUNNING) {
+ if (port->run) {
+ port->run = 0;
+ fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
+
+ fst_issue_cmd(port, STOPPORT);
+ } else {
+ dbg(DBG_OPEN, "close: port not running\n");
+ }
+ }
+}
+
+static int
+fst_open(struct net_device *dev)
+{
+ int err;
+ struct fst_port_info *port;
+
+ port = dev_to_port(dev);
+ if (!try_module_get(THIS_MODULE))
+ return -EBUSY;
+
+ if (port->mode != FST_RAW) {
+ err = hdlc_open(dev);
+ if (err)
+ return err;
+ }
+
+ fst_openport(port);
+ netif_wake_queue(dev);
+ return 0;
+}
+
+static int
+fst_close(struct net_device *dev)
+{
+ struct fst_port_info *port;
+ struct fst_card_info *card;
+ unsigned char tx_dma_done;
+ unsigned char rx_dma_done;
+
+ port = dev_to_port(dev);
+ card = port->card;
+
+ tx_dma_done = inb(card->pci_conf + DMACSR1);
+ rx_dma_done = inb(card->pci_conf + DMACSR0);
+ dbg(DBG_OPEN,
+ "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
+ card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
+ rx_dma_done);
+
+ netif_stop_queue(dev);
+ fst_closeport(dev_to_port(dev));
+ if (port->mode != FST_RAW) {
+ hdlc_close(dev);
+ }
+ module_put(THIS_MODULE);
+ return 0;
+}
+
+static int
+fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
+{
+ /*
+ * Setting currently fixed in FarSync card so we check and forget
+ */
+ if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
+ return -EINVAL;
+ return 0;
+}
+
+static void
+fst_tx_timeout(struct net_device *dev)
+{
+ struct fst_port_info *port;
+ struct fst_card_info *card;
+ struct net_device_stats *stats = hdlc_stats(dev);
+
+ port = dev_to_port(dev);
+ card = port->card;
+ stats->tx_errors++;
+ stats->tx_aborted_errors++;
+ dbg(DBG_ASS, "Tx timeout card %d port %d\n",
+ card->card_no, port->index);
+ fst_issue_cmd(port, ABORTTX);
+
+ dev->trans_start = jiffies;
+ netif_wake_queue(dev);
+ port->start = 0;
+}
+
+static int
+fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct fst_card_info *card;
+ struct fst_port_info *port;
+ struct net_device_stats *stats = hdlc_stats(dev);
+ unsigned long flags;
+ int txq_length;
+
+ port = dev_to_port(dev);
+ card = port->card;
+ dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
+
+ /* Drop packet with error if we don't have carrier */
+ if (!netif_carrier_ok(dev)) {
+ dev_kfree_skb(skb);
+ stats->tx_errors++;
+ stats->tx_carrier_errors++;
+ dbg(DBG_ASS,
+ "Tried to transmit but no carrier on card %d port %d\n",
+ card->card_no, port->index);
+ return 0;
+ }
+
+ /* Drop it if it's too big! MTU failure ? */
+ if (skb->len > LEN_TX_BUFFER) {
+ dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
+ LEN_TX_BUFFER);
+ dev_kfree_skb(skb);
+ stats->tx_errors++;
+ return 0;
+ }
+
+ /*
+ * We are always going to queue the packet
+ * so that the bottom half is the only place we tx from
+ * Check there is room in the port txq
+ */
+ spin_lock_irqsave(&card->card_lock, flags);
+ if ((txq_length = port->txqe - port->txqs) < 0) {
+ /*
+ * This is the case where the next free has wrapped but the
+ * last used hasn't
+ */
+ txq_length = txq_length + FST_TXQ_DEPTH;
+ }
+ spin_unlock_irqrestore(&card->card_lock, flags);
+ if (txq_length > fst_txq_high) {
+ /*
+ * We have got enough buffers in the pipeline. Ask the network
+ * layer to stop sending frames down
+ */
+ netif_stop_queue(dev);
+ port->start = 1; /* I'm using this to signal stop sent up */
+ }
+
+ if (txq_length == FST_TXQ_DEPTH - 1) {
+ /*
+ * This shouldn't have happened but such is life
+ */
+ dev_kfree_skb(skb);
+ stats->tx_errors++;
+ dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
+ card->card_no, port->index);
+ return 0;
+ }
+
+ /*
+ * queue the buffer
+ */
+ spin_lock_irqsave(&card->card_lock, flags);
+ port->txq[port->txqe] = skb;
+ port->txqe++;
+ if (port->txqe == FST_TXQ_DEPTH)
+ port->txqe = 0;
+ spin_unlock_irqrestore(&card->card_lock, flags);
+
+ /* Scehdule the bottom half which now does transmit processing */
+ fst_q_work_item(&fst_work_txq, card->card_no);
+ tasklet_schedule(&fst_tx_task);
+
+ return 0;
+}
+
+/*
+ * Card setup having checked hardware resources.
+ * Should be pretty bizarre if we get an error here (kernel memory
+ * exhaustion is one possibility). If we do see a problem we report it
+ * via a printk and leave the corresponding interface and all that follow
+ * disabled.
+ */
+static char *type_strings[] __devinitdata = {
+ "no hardware", /* Should never be seen */
+ "FarSync T2P",
+ "FarSync T4P",
+ "FarSync T1U",
+ "FarSync T2U",
+ "FarSync T4U",
+ "FarSync TE1"
+};
+
+static void __devinit
+fst_init_card(struct fst_card_info *card)
+{
+ int i;
+ int err;
+
+ /* We're working on a number of ports based on the card ID. If the
+ * firmware detects something different later (should never happen)
+ * we'll have to revise it in some way then.
+ */
+ for (i = 0; i < card->nports; i++) {
+ err = register_hdlc_device(card->ports[i].dev);
+ if (err < 0) {
+ int j;
+ printk_err ("Cannot register HDLC device for port %d"
+ " (errno %d)\n", i, -err );
+ for (j = i; j < card->nports; j++) {
+ free_netdev(card->ports[j].dev);
+ card->ports[j].dev = NULL;
+ }
+ card->nports = i;
+ break;
+ }
+ }
+
+ printk_info("%s-%s: %s IRQ%d, %d ports\n",
+ port_to_dev(&card->ports[0])->name,
+ port_to_dev(&card->ports[card->nports - 1])->name,
+ type_strings[card->type], card->irq, card->nports);
+}
+
+/*
+ * Initialise card when detected.
+ * Returns 0 to indicate success, or errno otherwise.
+ */
+static int __devinit
+fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ static int firsttime_done = 0;
+ static int no_of_cards_added = 0;
+ struct fst_card_info *card;
+ int err = 0;
+ int i;
+
+ if (!firsttime_done) {
+ printk_info("FarSync WAN driver " FST_USER_VERSION
+ " (c) 2001-2004 FarSite Communications Ltd.\n");
+ firsttime_done = 1;
+ dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
+ }
+
+ /*
+ * We are going to be clever and allow certain cards not to be
+ * configured. An exclude list can be provided in /etc/modules.conf
+ */
+ if (fst_excluded_cards != 0) {
+ /*
+ * There are cards to exclude
+ *
+ */
+ for (i = 0; i < fst_excluded_cards; i++) {
+ if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
+ printk_info("FarSync PCI device %d not assigned\n",
+ (pdev->devfn) >> 3);
+ return -EBUSY;
+ }
+ }
+ }
+
+ /* Allocate driver private data */
+ card = kmalloc(sizeof (struct fst_card_info), GFP_KERNEL);
+ if (card == NULL) {
+ printk_err("FarSync card found but insufficient memory for"
+ " driver storage\n");
+ return -ENOMEM;
+ }
+ memset(card, 0, sizeof (struct fst_card_info));
+
+ /* Try to enable the device */
+ if ((err = pci_enable_device(pdev)) != 0) {
+ printk_err("Failed to enable card. Err %d\n", -err);
+ kfree(card);
+ return err;
+ }
+
+ if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
+ printk_err("Failed to allocate regions. Err %d\n", -err);
+ pci_disable_device(pdev);
+ kfree(card);
+ return err;
+ }
+
+ /* Get virtual addresses of memory regions */
+ card->pci_conf = pci_resource_start(pdev, 1);
+ card->phys_mem = pci_resource_start(pdev, 2);
+ card->phys_ctlmem = pci_resource_start(pdev, 3);
+ if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
+ printk_err("Physical memory remap failed\n");
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ kfree(card);
+ return -ENODEV;
+ }
+ if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
+ printk_err("Control memory remap failed\n");
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ kfree(card);
+ return -ENODEV;
+ }
+ dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
+
+ /* Register the interrupt handler */
+ if (request_irq(pdev->irq, fst_intr, SA_SHIRQ, FST_DEV_NAME, card)) {
+ printk_err("Unable to register interrupt %d\n", card->irq);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ iounmap(card->ctlmem);
+ iounmap(card->mem);
+ kfree(card);
+ return -ENODEV;
+ }
+
+ /* Record info we need */
+ card->irq = pdev->irq;
+ card->type = ent->driver_data;
+ card->family = ((ent->driver_data == FST_TYPE_T2P) ||
+ (ent->driver_data == FST_TYPE_T4P))
+ ? FST_FAMILY_TXP : FST_FAMILY_TXU;
+ if ((ent->driver_data == FST_TYPE_T1U) ||
+ (ent->driver_data == FST_TYPE_TE1))
+ card->nports = 1;
+ else
+ card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
+ (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
+
+ card->state = FST_UNINIT;
+ spin_lock_init ( &card->card_lock );
+
+ for ( i = 0 ; i < card->nports ; i++ ) {
+ struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
+ hdlc_device *hdlc;
+ if (!dev) {
+ while (i--)
+ free_netdev(card->ports[i].dev);
+ printk_err ("FarSync: out of memory\n");
+ free_irq(card->irq, card);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ iounmap(card->ctlmem);
+ iounmap(card->mem);
+ kfree(card);
+ return -ENODEV;
+ }
+ card->ports[i].dev = dev;
+ card->ports[i].card = card;
+ card->ports[i].index = i;
+ card->ports[i].run = 0;
+
+ hdlc = dev_to_hdlc(dev);
+
+ /* Fill in the net device info */
+ /* Since this is a PCI setup this is purely
+ * informational. Give them the buffer addresses
+ * and basic card I/O.
+ */
+ dev->mem_start = card->phys_mem
+ + BUF_OFFSET ( txBuffer[i][0][0]);
+ dev->mem_end = card->phys_mem
+ + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]);
+ dev->base_addr = card->pci_conf;
+ dev->irq = card->irq;
+
+ dev->tx_queue_len = FST_TX_QUEUE_LEN;
+ dev->open = fst_open;
+ dev->stop = fst_close;
+ dev->do_ioctl = fst_ioctl;
+ dev->watchdog_timeo = FST_TX_TIMEOUT;
+ dev->tx_timeout = fst_tx_timeout;
+ hdlc->attach = fst_attach;
+ hdlc->xmit = fst_start_xmit;
+ }
+
+ card->device = pdev;
+
+ dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
+ card->nports, card->irq);
+ dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
+ card->pci_conf, card->phys_mem, card->phys_ctlmem);
+
+ /* Reset the card's processor */
+ fst_cpureset(card);
+ card->state = FST_RESET;
+
+ /* Initialise DMA (if required) */
+ fst_init_dma(card);
+
+ /* Record driver data for later use */
+ pci_set_drvdata(pdev, card);
+
+ /* Remainder of card setup */
+ fst_card_array[no_of_cards_added] = card;
+ card->card_no = no_of_cards_added++; /* Record instance and bump it */
+ fst_init_card(card);
+ if (card->family == FST_FAMILY_TXU) {
+ /*
+ * Allocate a dma buffer for transmit and receives
+ */
+ card->rx_dma_handle_host =
+ pci_alloc_consistent(card->device, FST_MAX_MTU,
+ &card->rx_dma_handle_card);
+ if (card->rx_dma_handle_host == NULL) {
+ printk_err("Could not allocate rx dma buffer\n");
+ fst_disable_intr(card);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ iounmap(card->ctlmem);
+ iounmap(card->mem);
+ kfree(card);
+ return -ENOMEM;
+ }
+ card->tx_dma_handle_host =
+ pci_alloc_consistent(card->device, FST_MAX_MTU,
+ &card->tx_dma_handle_card);
+ if (card->tx_dma_handle_host == NULL) {
+ printk_err("Could not allocate tx dma buffer\n");
+ fst_disable_intr(card);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ iounmap(card->ctlmem);
+ iounmap(card->mem);
+ kfree(card);
+ return -ENOMEM;
+ }
+ }
+ return 0; /* Success */
+}
+
+/*
+ * Cleanup and close down a card
+ */
+static void __devexit
+fst_remove_one(struct pci_dev *pdev)
+{
+ struct fst_card_info *card;
+ int i;
+
+ card = pci_get_drvdata(pdev);
+
+ for (i = 0; i < card->nports; i++) {
+ struct net_device *dev = port_to_dev(&card->ports[i]);
+ unregister_hdlc_device(dev);
+ }
+
+ fst_disable_intr(card);
+ free_irq(card->irq, card);
+
+ iounmap(card->ctlmem);
+ iounmap(card->mem);
+ pci_release_regions(pdev);
+ if (card->family == FST_FAMILY_TXU) {
+ /*
+ * Free dma buffers
+ */
+ pci_free_consistent(card->device, FST_MAX_MTU,
+ card->rx_dma_handle_host,
+ card->rx_dma_handle_card);
+ pci_free_consistent(card->device, FST_MAX_MTU,
+ card->tx_dma_handle_host,
+ card->tx_dma_handle_card);
+ }
+ fst_card_array[card->card_no] = NULL;
+}
+
+static struct pci_driver fst_driver = {
+ .name = FST_NAME,
+ .id_table = fst_pci_dev_id,
+ .probe = fst_add_one,
+ .remove = __devexit_p(fst_remove_one),
+ .suspend = NULL,
+ .resume = NULL,
+};
+
+static int __init
+fst_init(void)
+{
+ int i;
+
+ for (i = 0; i < FST_MAX_CARDS; i++)
+ fst_card_array[i] = NULL;
+ spin_lock_init(&fst_work_q_lock);
+ return pci_module_init(&fst_driver);
+}
+
+static void __exit
+fst_cleanup_module(void)
+{
+ printk_info("FarSync WAN driver unloading\n");
+ pci_unregister_driver(&fst_driver);
+}
+
+module_init(fst_init);
+module_exit(fst_cleanup_module);
diff --git a/drivers/net/wan/farsync.h b/drivers/net/wan/farsync.h
new file mode 100644
index 000000000000..d871dafa87a1
--- /dev/null
+++ b/drivers/net/wan/farsync.h
@@ -0,0 +1,357 @@
+/*
+ * FarSync X21 driver for Linux
+ *
+ * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
+ *
+ * Copyright (C) 2001 FarSite Communications Ltd.
+ * www.farsite.co.uk
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Author: R.J.Dunlop
+ *
+ * For the most part this file only contains structures and information
+ * that is visible to applications outside the driver. Shared memory
+ * layout etc is internal to the driver and described within farsync.c.
+ * Overlap exists in that the values used for some fields within the
+ * ioctl interface extend into the cards firmware interface so values in
+ * this file may not be changed arbitrarily.
+ */
+
+/* What's in a name
+ *
+ * The project name for this driver is Oscar. The driver is intended to be
+ * used with the FarSite T-Series cards (T2P & T4P) running in the high
+ * speed frame shifter mode. This is sometimes referred to as X.21 mode
+ * which is a complete misnomer as the card continues to support V.24 and
+ * V.35 as well as X.21.
+ *
+ * A short common prefix is useful for routines within the driver to avoid
+ * conflict with other similar drivers and I chosen to use "fst_" for this
+ * purpose (FarSite T-series).
+ *
+ * Finally the device driver needs a short network interface name. Since
+ * "hdlc" is already in use I've chosen the even less informative "sync"
+ * for the present.
+ */
+#define FST_NAME "fst" /* In debug/info etc */
+#define FST_NDEV_NAME "sync" /* For net interface */
+#define FST_DEV_NAME "farsync" /* For misc interfaces */
+
+
+/* User version number
+ *
+ * This version number is incremented with each official release of the
+ * package and is a simplified number for normal user reference.
+ * Individual files are tracked by the version control system and may
+ * have individual versions (or IDs) that move much faster than the
+ * the release version as individual updates are tracked.
+ */
+#define FST_USER_VERSION "1.04"
+
+
+/* Ioctl call command values
+ *
+ * The first three private ioctls are used by the sync-PPP module,
+ * allowing a little room for expansion we start our numbering at 10.
+ */
+#define FSTWRITE (SIOCDEVPRIVATE+10)
+#define FSTCPURESET (SIOCDEVPRIVATE+11)
+#define FSTCPURELEASE (SIOCDEVPRIVATE+12)
+#define FSTGETCONF (SIOCDEVPRIVATE+13)
+#define FSTSETCONF (SIOCDEVPRIVATE+14)
+
+
+/* FSTWRITE
+ *
+ * Used to write a block of data (firmware etc) before the card is running
+ */
+struct fstioc_write {
+ unsigned int size;
+ unsigned int offset;
+ unsigned char data[0];
+};
+
+
+/* FSTCPURESET and FSTCPURELEASE
+ *
+ * These take no additional data.
+ * FSTCPURESET forces the cards CPU into a reset state and holds it there.
+ * FSTCPURELEASE releases the CPU from this reset state allowing it to run,
+ * the reset vector should be setup before this ioctl is run.
+ */
+
+/* FSTGETCONF and FSTSETCONF
+ *
+ * Get and set a card/ports configuration.
+ * In order to allow selective setting of items and for the kernel to
+ * indicate a partial status response the first field "valid" is a bitmask
+ * indicating which other fields in the structure are valid.
+ * Many of the field names in this structure match those used in the
+ * firmware shared memory configuration interface and come originally from
+ * the NT header file Smc.h
+ *
+ * When used with FSTGETCONF this structure should be zeroed before use.
+ * This is to allow for possible future expansion when some of the fields
+ * might be used to indicate a different (expanded) structure.
+ */
+struct fstioc_info {
+ unsigned int valid; /* Bits of structure that are valid */
+ unsigned int nports; /* Number of serial ports */
+ unsigned int type; /* Type index of card */
+ unsigned int state; /* State of card */
+ unsigned int index; /* Index of port ioctl was issued on */
+ unsigned int smcFirmwareVersion;
+ unsigned long kernelVersion; /* What Kernel version we are working with */
+ unsigned short lineInterface; /* Physical interface type */
+ unsigned char proto; /* Line protocol */
+ unsigned char internalClock; /* 1 => internal clock, 0 => external */
+ unsigned int lineSpeed; /* Speed in bps */
+ unsigned int v24IpSts; /* V.24 control input status */
+ unsigned int v24OpSts; /* V.24 control output status */
+ unsigned short clockStatus; /* lsb: 0=> present, 1=> absent */
+ unsigned short cableStatus; /* lsb: 0=> present, 1=> absent */
+ unsigned short cardMode; /* lsb: LED id mode */
+ unsigned short debug; /* Debug flags */
+ unsigned char transparentMode; /* Not used always 0 */
+ unsigned char invertClock; /* Invert clock feature for syncing */
+ unsigned char startingSlot; /* Time slot to use for start of tx */
+ unsigned char clockSource; /* External or internal */
+ unsigned char framing; /* E1, T1 or J1 */
+ unsigned char structure; /* unframed, double, crc4, f4, f12, */
+ /* f24 f72 */
+ unsigned char interface; /* rj48c or bnc */
+ unsigned char coding; /* hdb3 b8zs */
+ unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */
+ unsigned char equalizer; /* short or lon haul settings */
+ unsigned char loopMode; /* various loopbacks */
+ unsigned char range; /* cable lengths */
+ unsigned char txBufferMode; /* tx elastic buffer depth */
+ unsigned char rxBufferMode; /* rx elastic buffer depth */
+ unsigned char losThreshold; /* Attenuation on LOS signal */
+ unsigned char idleCode; /* Value to send as idle timeslot */
+ unsigned int receiveBufferDelay; /* delay thro rx buffer timeslots */
+ unsigned int framingErrorCount; /* framing errors */
+ unsigned int codeViolationCount; /* code violations */
+ unsigned int crcErrorCount; /* CRC errors */
+ int lineAttenuation; /* in dB*/
+ unsigned short lossOfSignal;
+ unsigned short receiveRemoteAlarm;
+ unsigned short alarmIndicationSignal;
+};
+
+/* "valid" bitmask */
+#define FSTVAL_NONE 0x00000000 /* Nothing valid (firmware not running).
+ * Slight misnomer. In fact nports,
+ * type, state and index will be set
+ * based on hardware detected.
+ */
+#define FSTVAL_OMODEM 0x0000001F /* First 5 bits correspond to the
+ * output status bits defined for
+ * v24OpSts
+ */
+#define FSTVAL_SPEED 0x00000020 /* internalClock, lineSpeed, clockStatus
+ */
+#define FSTVAL_CABLE 0x00000040 /* lineInterface, cableStatus */
+#define FSTVAL_IMODEM 0x00000080 /* v24IpSts */
+#define FSTVAL_CARD 0x00000100 /* nports, type, state, index,
+ * smcFirmwareVersion
+ */
+#define FSTVAL_PROTO 0x00000200 /* proto */
+#define FSTVAL_MODE 0x00000400 /* cardMode */
+#define FSTVAL_PHASE 0x00000800 /* Clock phase */
+#define FSTVAL_TE1 0x00001000 /* T1E1 Configuration */
+#define FSTVAL_DEBUG 0x80000000 /* debug */
+#define FSTVAL_ALL 0x00001FFF /* Note: does not include DEBUG flag */
+
+/* "type" */
+#define FST_TYPE_NONE 0 /* Probably should never happen */
+#define FST_TYPE_T2P 1 /* T2P X21 2 port card */
+#define FST_TYPE_T4P 2 /* T4P X21 4 port card */
+#define FST_TYPE_T1U 3 /* T1U X21 1 port card */
+#define FST_TYPE_T2U 4 /* T2U X21 2 port card */
+#define FST_TYPE_T4U 5 /* T4U X21 4 port card */
+#define FST_TYPE_TE1 6 /* T1E1 X21 1 port card */
+
+/* "family" */
+#define FST_FAMILY_TXP 0 /* T2P or T4P */
+#define FST_FAMILY_TXU 1 /* T1U or T2U or T4U */
+
+/* "state" */
+#define FST_UNINIT 0 /* Raw uninitialised state following
+ * system startup */
+#define FST_RESET 1 /* Processor held in reset state */
+#define FST_DOWNLOAD 2 /* Card being downloaded */
+#define FST_STARTING 3 /* Released following download */
+#define FST_RUNNING 4 /* Processor running */
+#define FST_BADVERSION 5 /* Bad shared memory version detected */
+#define FST_HALTED 6 /* Processor flagged a halt */
+#define FST_IFAILED 7 /* Firmware issued initialisation failed
+ * interrupt
+ */
+/* "lineInterface" */
+#define V24 1
+#define X21 2
+#define V35 3
+#define X21D 4
+#define T1 5
+#define E1 6
+#define J1 7
+
+/* "proto" */
+#define FST_HDLC 1 /* Cisco compatible HDLC */
+#define FST_PPP 2 /* Sync PPP */
+#define FST_MONITOR 3 /* Monitor only (raw packet reception) */
+#define FST_RAW 4 /* Two way raw packets */
+#define FST_GEN_HDLC 5 /* Using "Generic HDLC" module */
+
+/* "internalClock" */
+#define INTCLK 1
+#define EXTCLK 0
+
+/* "v24IpSts" bitmask */
+#define IPSTS_CTS 0x00000001 /* Clear To Send (Indicate for X.21) */
+#define IPSTS_INDICATE IPSTS_CTS
+#define IPSTS_DSR 0x00000002 /* Data Set Ready (T2P Port A) */
+#define IPSTS_DCD 0x00000004 /* Data Carrier Detect */
+#define IPSTS_RI 0x00000008 /* Ring Indicator (T2P Port A) */
+#define IPSTS_TMI 0x00000010 /* Test Mode Indicator (Not Supported)*/
+
+/* "v24OpSts" bitmask */
+#define OPSTS_RTS 0x00000001 /* Request To Send (Control for X.21) */
+#define OPSTS_CONTROL OPSTS_RTS
+#define OPSTS_DTR 0x00000002 /* Data Terminal Ready */
+#define OPSTS_DSRS 0x00000004 /* Data Signalling Rate Select (Not
+ * Supported) */
+#define OPSTS_SS 0x00000008 /* Select Standby (Not Supported) */
+#define OPSTS_LL 0x00000010 /* Maintenance Test (Not Supported) */
+
+/* "cardMode" bitmask */
+#define CARD_MODE_IDENTIFY 0x0001
+
+/*
+ * Constants for T1/E1 configuration
+ */
+
+/*
+ * Clock source
+ */
+#define CLOCKING_SLAVE 0
+#define CLOCKING_MASTER 1
+
+/*
+ * Framing
+ */
+#define FRAMING_E1 0
+#define FRAMING_J1 1
+#define FRAMING_T1 2
+
+/*
+ * Structure
+ */
+#define STRUCTURE_UNFRAMED 0
+#define STRUCTURE_E1_DOUBLE 1
+#define STRUCTURE_E1_CRC4 2
+#define STRUCTURE_E1_CRC4M 3
+#define STRUCTURE_T1_4 4
+#define STRUCTURE_T1_12 5
+#define STRUCTURE_T1_24 6
+#define STRUCTURE_T1_72 7
+
+/*
+ * Interface
+ */
+#define INTERFACE_RJ48C 0
+#define INTERFACE_BNC 1
+
+/*
+ * Coding
+ */
+
+#define CODING_HDB3 0
+#define CODING_NRZ 1
+#define CODING_CMI 2
+#define CODING_CMI_HDB3 3
+#define CODING_CMI_B8ZS 4
+#define CODING_AMI 5
+#define CODING_AMI_ZCS 6
+#define CODING_B8ZS 7
+
+/*
+ * Line Build Out
+ */
+#define LBO_0dB 0
+#define LBO_7dB5 1
+#define LBO_15dB 2
+#define LBO_22dB5 3
+
+/*
+ * Range for long haul t1 > 655ft
+ */
+#define RANGE_0_133_FT 0
+#define RANGE_0_40_M RANGE_0_133_FT
+#define RANGE_133_266_FT 1
+#define RANGE_40_81_M RANGE_133_266_FT
+#define RANGE_266_399_FT 2
+#define RANGE_81_122_M RANGE_266_399_FT
+#define RANGE_399_533_FT 3
+#define RANGE_122_162_M RANGE_399_533_FT
+#define RANGE_533_655_FT 4
+#define RANGE_162_200_M RANGE_533_655_FT
+/*
+ * Receive Equaliser
+ */
+#define EQUALIZER_SHORT 0
+#define EQUALIZER_LONG 1
+
+/*
+ * Loop modes
+ */
+#define LOOP_NONE 0
+#define LOOP_LOCAL 1
+#define LOOP_PAYLOAD_EXC_TS0 2
+#define LOOP_PAYLOAD_INC_TS0 3
+#define LOOP_REMOTE 4
+
+/*
+ * Buffer modes
+ */
+#define BUFFER_2_FRAME 0
+#define BUFFER_1_FRAME 1
+#define BUFFER_96_BIT 2
+#define BUFFER_NONE 3
+
+/* Debug support
+ *
+ * These should only be enabled for development kernels, production code
+ * should define FST_DEBUG=0 in order to exclude the code.
+ * Setting FST_DEBUG=1 will include all the debug code but in a disabled
+ * state, use the FSTSETCONF ioctl to enable specific debug actions, or
+ * FST_DEBUG can be set to prime the debug selection.
+ */
+#define FST_DEBUG 0x0000
+#if FST_DEBUG
+
+extern int fst_debug_mask; /* Bit mask of actions to debug, bits
+ * listed below. Note: Bit 0 is used
+ * to trigger the inclusion of this
+ * code, without enabling any actions.
+ */
+#define DBG_INIT 0x0002 /* Card detection and initialisation */
+#define DBG_OPEN 0x0004 /* Open and close sequences */
+#define DBG_PCI 0x0008 /* PCI config operations */
+#define DBG_IOCTL 0x0010 /* Ioctls and other config */
+#define DBG_INTR 0x0020 /* Interrupt routines (be careful) */
+#define DBG_TX 0x0040 /* Packet transmission */
+#define DBG_RX 0x0080 /* Packet reception */
+#define DBG_CMD 0x0100 /* Port command issuing */
+
+#define DBG_ASS 0xFFFF /* Assert like statements. Code that
+ * should never be reached, if you see
+ * one of these then I've been an ass
+ */
+#endif /* FST_DEBUG */
+
diff --git a/drivers/net/wan/hd64570.h b/drivers/net/wan/hd64570.h
new file mode 100644
index 000000000000..3839662ff201
--- /dev/null
+++ b/drivers/net/wan/hd64570.h
@@ -0,0 +1,241 @@
+#ifndef __HD64570_H
+#define __HD64570_H
+
+/* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
+ and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.
+
+ Source: HD64570 SCA User's Manual
+*/
+
+
+
+/* SCA Control Registers */
+#define LPR 0x00 /* Low Power */
+
+/* Wait controller registers */
+#define PABR0 0x02 /* Physical Address Boundary 0 */
+#define PABR1 0x03 /* Physical Address Boundary 1 */
+#define WCRL 0x04 /* Wait Control L */
+#define WCRM 0x05 /* Wait Control M */
+#define WCRH 0x06 /* Wait Control H */
+
+#define PCR 0x08 /* DMA Priority Control */
+#define DMER 0x09 /* DMA Master Enable */
+
+
+/* Interrupt registers */
+#define ISR0 0x10 /* Interrupt Status 0 */
+#define ISR1 0x11 /* Interrupt Status 1 */
+#define ISR2 0x12 /* Interrupt Status 2 */
+
+#define IER0 0x14 /* Interrupt Enable 0 */
+#define IER1 0x15 /* Interrupt Enable 1 */
+#define IER2 0x16 /* Interrupt Enable 2 */
+
+#define ITCR 0x18 /* Interrupt Control */
+#define IVR 0x1A /* Interrupt Vector */
+#define IMVR 0x1C /* Interrupt Modified Vector */
+
+
+
+/* MSCI channel (port) 0 registers - offset 0x20
+ MSCI channel (port) 1 registers - offset 0x40 */
+
+#define MSCI0_OFFSET 0x20
+#define MSCI1_OFFSET 0x40
+
+#define TRBL 0x00 /* TX/RX buffer L */
+#define TRBH 0x01 /* TX/RX buffer H */
+#define ST0 0x02 /* Status 0 */
+#define ST1 0x03 /* Status 1 */
+#define ST2 0x04 /* Status 2 */
+#define ST3 0x05 /* Status 3 */
+#define FST 0x06 /* Frame Status */
+#define IE0 0x08 /* Interrupt Enable 0 */
+#define IE1 0x09 /* Interrupt Enable 1 */
+#define IE2 0x0A /* Interrupt Enable 2 */
+#define FIE 0x0B /* Frame Interrupt Enable */
+#define CMD 0x0C /* Command */
+#define MD0 0x0E /* Mode 0 */
+#define MD1 0x0F /* Mode 1 */
+#define MD2 0x10 /* Mode 2 */
+#define CTL 0x11 /* Control */
+#define SA0 0x12 /* Sync/Address 0 */
+#define SA1 0x13 /* Sync/Address 1 */
+#define IDL 0x14 /* Idle Pattern */
+#define TMC 0x15 /* Time Constant */
+#define RXS 0x16 /* RX Clock Source */
+#define TXS 0x17 /* TX Clock Source */
+#define TRC0 0x18 /* TX Ready Control 0 */
+#define TRC1 0x19 /* TX Ready Control 1 */
+#define RRC 0x1A /* RX Ready Control */
+#define CST0 0x1C /* Current Status 0 */
+#define CST1 0x1D /* Current Status 1 */
+
+
+/* Timer channel 0 (port 0 RX) registers - offset 0x60
+ Timer channel 1 (port 0 TX) registers - offset 0x68
+ Timer channel 2 (port 1 RX) registers - offset 0x70
+ Timer channel 3 (port 1 TX) registers - offset 0x78
+*/
+
+#define TIMER0RX_OFFSET 0x60
+#define TIMER0TX_OFFSET 0x68
+#define TIMER1RX_OFFSET 0x70
+#define TIMER1TX_OFFSET 0x78
+
+#define TCNTL 0x00 /* Up-counter L */
+#define TCNTH 0x01 /* Up-counter H */
+#define TCONRL 0x02 /* Constant L */
+#define TCONRH 0x03 /* Constant H */
+#define TCSR 0x04 /* Control/Status */
+#define TEPR 0x05 /* Expand Prescale */
+
+
+
+/* DMA channel 0 (port 0 RX) registers - offset 0x80
+ DMA channel 1 (port 0 TX) registers - offset 0xA0
+ DMA channel 2 (port 1 RX) registers - offset 0xC0
+ DMA channel 3 (port 1 TX) registers - offset 0xE0
+*/
+
+#define DMAC0RX_OFFSET 0x80
+#define DMAC0TX_OFFSET 0xA0
+#define DMAC1RX_OFFSET 0xC0
+#define DMAC1TX_OFFSET 0xE0
+
+#define BARL 0x00 /* Buffer Address L (chained block) */
+#define BARH 0x01 /* Buffer Address H (chained block) */
+#define BARB 0x02 /* Buffer Address B (chained block) */
+
+#define DARL 0x00 /* RX Destination Addr L (single block) */
+#define DARH 0x01 /* RX Destination Addr H (single block) */
+#define DARB 0x02 /* RX Destination Addr B (single block) */
+
+#define SARL 0x04 /* TX Source Address L (single block) */
+#define SARH 0x05 /* TX Source Address H (single block) */
+#define SARB 0x06 /* TX Source Address B (single block) */
+
+#define CPB 0x06 /* Chain Pointer Base (chained block) */
+
+#define CDAL 0x08 /* Current Descriptor Addr L (chained block) */
+#define CDAH 0x09 /* Current Descriptor Addr H (chained block) */
+#define EDAL 0x0A /* Error Descriptor Addr L (chained block) */
+#define EDAH 0x0B /* Error Descriptor Addr H (chained block) */
+#define BFLL 0x0C /* RX Receive Buffer Length L (chained block)*/
+#define BFLH 0x0D /* RX Receive Buffer Length H (chained block)*/
+#define BCRL 0x0E /* Byte Count L */
+#define BCRH 0x0F /* Byte Count H */
+#define DSR 0x10 /* DMA Status */
+#define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
+#define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
+#define DMR 0x11 /* DMA Mode */
+#define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
+#define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
+#define FCT 0x13 /* Frame End Interrupt Counter */
+#define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
+#define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
+#define DIR 0x14 /* DMA Interrupt Enable */
+#define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
+#define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
+#define DCR 0x15 /* DMA Command */
+#define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
+#define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
+
+
+
+
+/* Descriptor Structure */
+
+typedef struct {
+ u16 cp; /* Chain Pointer */
+ u32 bp; /* Buffer Pointer (24 bits) */
+ u16 len; /* Data Length */
+ u8 stat; /* Status */
+ u8 unused; /* pads to 2-byte boundary */
+}__attribute__ ((packed)) pkt_desc;
+
+
+/* Packet Descriptor Status bits */
+
+#define ST_TX_EOM 0x80 /* End of frame */
+#define ST_TX_EOT 0x01 /* End of transmition */
+
+#define ST_RX_EOM 0x80 /* End of frame */
+#define ST_RX_SHORT 0x40 /* Short frame */
+#define ST_RX_ABORT 0x20 /* Abort */
+#define ST_RX_RESBIT 0x10 /* Residual bit */
+#define ST_RX_OVERRUN 0x08 /* Overrun */
+#define ST_RX_CRC 0x04 /* CRC */
+
+#define ST_ERROR_MASK 0x7C
+
+#define DIR_EOTE 0x80 /* Transfer completed */
+#define DIR_EOME 0x40 /* Frame Transfer Completed (chained-block) */
+#define DIR_BOFE 0x20 /* Buffer Overflow/Underflow (chained-block)*/
+#define DIR_COFE 0x10 /* Counter Overflow (chained-block) */
+
+
+#define DSR_EOT 0x80 /* Transfer completed */
+#define DSR_EOM 0x40 /* Frame Transfer Completed (chained-block) */
+#define DSR_BOF 0x20 /* Buffer Overflow/Underflow (chained-block)*/
+#define DSR_COF 0x10 /* Counter Overflow (chained-block) */
+#define DSR_DE 0x02 /* DMA Enable */
+#define DSR_DWE 0x01 /* DMA Write Disable */
+
+/* DMA Master Enable Register (DMER) bits */
+#define DMER_DME 0x80 /* DMA Master Enable */
+
+
+#define CMD_RESET 0x21 /* Reset Channel */
+#define CMD_TX_ENABLE 0x02 /* Start transmitter */
+#define CMD_RX_ENABLE 0x12 /* Start receiver */
+
+#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
+#define MD0_CRC_ENA 0x04 /* Enable CRC code calculation */
+#define MD0_CRC_CCITT 0x02 /* CCITT CRC instead of CRC-16 */
+#define MD0_CRC_PR1 0x01 /* Initial all-ones instead of all-zeros */
+
+#define MD0_CRC_NONE 0x00
+#define MD0_CRC_16_0 0x04
+#define MD0_CRC_16 0x05
+#define MD0_CRC_ITU_0 0x06
+#define MD0_CRC_ITU 0x07
+
+#define MD2_NRZ 0x00
+#define MD2_NRZI 0x20
+#define MD2_MANCHESTER 0x80
+#define MD2_FM_MARK 0xA0
+#define MD2_FM_SPACE 0xC0
+#define MD2_LOOPBACK 0x03 /* Local data Loopback */
+
+#define CTL_NORTS 0x01
+#define CTL_IDLE 0x10 /* Transmit an idle pattern */
+#define CTL_UDRNC 0x20 /* Idle after CRC or FCS+flag transmition */
+
+#define ST0_TXRDY 0x02 /* TX ready */
+#define ST0_RXRDY 0x01 /* RX ready */
+
+#define ST1_UDRN 0x80 /* MSCI TX underrun */
+#define ST1_CDCD 0x04 /* DCD level changed */
+
+#define ST3_CTS 0x08 /* modem input - /CTS */
+#define ST3_DCD 0x04 /* modem input - /DCD */
+
+#define IE0_TXINT 0x80 /* TX INT MSCI interrupt enable */
+#define IE0_RXINTA 0x40 /* RX INT A MSCI interrupt enable */
+#define IE1_UDRN 0x80 /* TX underrun MSCI interrupt enable */
+#define IE1_CDCD 0x04 /* DCD level changed */
+
+#define DCR_ABORT 0x01 /* Software abort command */
+#define DCR_CLEAR_EOF 0x02 /* Clear EOF interrupt */
+
+/* TX and RX Clock Source - RXS and TXS */
+#define CLK_BRG_MASK 0x0F
+#define CLK_LINE_RX 0x00 /* TX/RX clock line input */
+#define CLK_LINE_TX 0x00 /* TX/RX line input */
+#define CLK_BRG_RX 0x40 /* internal baud rate generator */
+#define CLK_BRG_TX 0x40 /* internal baud rate generator */
+#define CLK_RXCLK_TX 0x60 /* TX clock from RX clock */
+
+#endif
diff --git a/drivers/net/wan/hd64572.h b/drivers/net/wan/hd64572.h
new file mode 100644
index 000000000000..96567c2dc4db
--- /dev/null
+++ b/drivers/net/wan/hd64572.h
@@ -0,0 +1,527 @@
+/*
+ * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
+ * CPU modes 0 & 2.
+ *
+ * Author: Ivan Passos
+ *
+ * Copyright: (c) 2000-2001 Cyclades Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * $Log: hd64572.h,v $
+ * Revision 3.1 2001/06/15 12:41:10 regina
+ * upping major version number
+ *
+ * Revision 1.1.1.1 2001/06/13 20:24:49 daniela
+ * PC300 initial CVS version (3.4.0-pre1)
+ *
+ * Revision 1.0 2000/01/25 ivan
+ * Initial version.
+ *
+ */
+
+#ifndef __HD64572_H
+#define __HD64572_H
+
+/* Illegal Access Register */
+#define ILAR 0x00
+
+/* Wait Controller Registers */
+#define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */
+#define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */
+#define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */
+#define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */
+#define WCRL 0x24 /* Wait Control Register L */
+#define WCRM 0x25 /* Wait Control Register M */
+#define WCRH 0x26 /* Wait Control Register H */
+
+/* Interrupt Registers */
+#define IVR 0x60 /* Interrupt Vector Register */
+#define IMVR 0x64 /* Interrupt Modified Vector Register */
+#define ITCR 0x68 /* Interrupt Control Register */
+#define ISR0 0x6c /* Interrupt Status Register 0 */
+#define ISR1 0x70 /* Interrupt Status Register 1 */
+#define IER0 0x74 /* Interrupt Enable Register 0 */
+#define IER1 0x78 /* Interrupt Enable Register 1 */
+
+/* Register Access Macros (chan is 0 or 1 in _any_ case) */
+#define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */
+#define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */
+#define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */
+#define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */
+#define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */
+#define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */
+#define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */
+#define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */
+#define IR0_M(val, chan) ((val)<<(8*(chan))) /* Int MSCI */
+
+/* MSCI Channel Registers */
+#define MSCI0_OFFSET 0x00
+#define MSCI1_OFFSET 0x80
+
+#define MD0 0x138 /* Mode reg 0 */
+#define MD1 0x139 /* Mode reg 1 */
+#define MD2 0x13a /* Mode reg 2 */
+#define MD3 0x13b /* Mode reg 3 */
+#define CTL 0x130 /* Control reg */
+#define RXS 0x13c /* RX clock source */
+#define TXS 0x13d /* TX clock source */
+#define EXS 0x13e /* External clock input selection */
+#define TMCT 0x144 /* Time constant (Tx) */
+#define TMCR 0x145 /* Time constant (Rx) */
+#define CMD 0x128 /* Command reg */
+#define ST0 0x118 /* Status reg 0 */
+#define ST1 0x119 /* Status reg 1 */
+#define ST2 0x11a /* Status reg 2 */
+#define ST3 0x11b /* Status reg 3 */
+#define ST4 0x11c /* Status reg 4 */
+#define FST 0x11d /* frame Status reg */
+#define IE0 0x120 /* Interrupt enable reg 0 */
+#define IE1 0x121 /* Interrupt enable reg 1 */
+#define IE2 0x122 /* Interrupt enable reg 2 */
+#define IE4 0x124 /* Interrupt enable reg 4 */
+#define FIE 0x125 /* Frame Interrupt enable reg */
+#define SA0 0x140 /* Syn Address reg 0 */
+#define SA1 0x141 /* Syn Address reg 1 */
+#define IDL 0x142 /* Idle register */
+#define TRBL 0x100 /* TX/RX buffer reg L */
+#define TRBK 0x101 /* TX/RX buffer reg K */
+#define TRBJ 0x102 /* TX/RX buffer reg J */
+#define TRBH 0x103 /* TX/RX buffer reg H */
+#define TRC0 0x148 /* TX Ready control reg 0 */
+#define TRC1 0x149 /* TX Ready control reg 1 */
+#define RRC 0x14a /* RX Ready control reg */
+#define CST0 0x108 /* Current Status Register 0 */
+#define CST1 0x109 /* Current Status Register 1 */
+#define CST2 0x10a /* Current Status Register 2 */
+#define CST3 0x10b /* Current Status Register 3 */
+#define GPO 0x131 /* General Purpose Output Pin Ctl Reg */
+#define TFS 0x14b /* Tx Start Threshold Ctl Reg */
+#define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */
+#define TBN 0x110 /* Tx Buffer Number Reg */
+#define RBN 0x111 /* Rx Buffer Number Reg */
+#define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */
+#define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */
+#define TCR 0x152 /* Tx DMA Critical Request Reg */
+#define RNR 0x154 /* Rx DMA Request Ctl Reg */
+#define RCR 0x156 /* Rx DMA Critical Request Reg */
+
+/* Timer Registers */
+#define TIMER0RX_OFFSET 0x00
+#define TIMER0TX_OFFSET 0x10
+#define TIMER1RX_OFFSET 0x20
+#define TIMER1TX_OFFSET 0x30
+
+#define TCNTL 0x200 /* Timer Upcounter L */
+#define TCNTH 0x201 /* Timer Upcounter H */
+#define TCONRL 0x204 /* Timer Constant Register L */
+#define TCONRH 0x205 /* Timer Constant Register H */
+#define TCSR 0x206 /* Timer Control/Status Register */
+#define TEPR 0x207 /* Timer Expand Prescale Register */
+
+/* DMA registers */
+#define PCR 0x40 /* DMA priority control reg */
+#define DRR 0x44 /* DMA reset reg */
+#define DMER 0x07 /* DMA Master Enable reg */
+#define BTCR 0x08 /* Burst Tx Ctl Reg */
+#define BOLR 0x0c /* Back-off Length Reg */
+#define DSR_RX(chan) (0x48 + 2*chan) /* DMA Status Reg (Rx) */
+#define DSR_TX(chan) (0x49 + 2*chan) /* DMA Status Reg (Tx) */
+#define DIR_RX(chan) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */
+#define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */
+#define FCT_RX(chan) (0x50 + 2*chan) /* Frame End Interrupt Counter (Rx) */
+#define FCT_TX(chan) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */
+#define DMR_RX(chan) (0x54 + 2*chan) /* DMA Mode Reg (Rx) */
+#define DMR_TX(chan) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */
+#define DCR_RX(chan) (0x58 + 2*chan) /* DMA Command Reg (Rx) */
+#define DCR_TX(chan) (0x59 + 2*chan) /* DMA Command Reg (Tx) */
+
+/* DMA Channel Registers */
+#define DMAC0RX_OFFSET 0x00
+#define DMAC0TX_OFFSET 0x20
+#define DMAC1RX_OFFSET 0x40
+#define DMAC1TX_OFFSET 0x60
+
+#define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */
+#define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */
+#define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */
+#define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */
+#define SARL 0x80 /* Source Addr Register L (single-block, TX only) */
+#define SARH 0x81 /* Source Addr Register H (single-block, TX only) */
+#define SARB 0x82 /* Source Addr Register B (single-block, TX only) */
+#define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */
+#define BARL 0x80 /* Buffer Addr Register L (chained-block) */
+#define BARH 0x81 /* Buffer Addr Register H (chained-block) */
+#define BARB 0x82 /* Buffer Addr Register B (chained-block) */
+#define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */
+#define CDAL 0x84 /* Current Descriptor Addr Register L */
+#define CDAH 0x85 /* Current Descriptor Addr Register H */
+#define CDAB 0x86 /* Current Descriptor Addr Register B */
+#define CDABH 0x87 /* Current Descriptor Addr Register BH */
+#define EDAL 0x88 /* Error Descriptor Addr Register L */
+#define EDAH 0x89 /* Error Descriptor Addr Register H */
+#define EDAB 0x8a /* Error Descriptor Addr Register B */
+#define EDABH 0x8b /* Error Descriptor Addr Register BH */
+#define BFLL 0x90 /* RX Buffer Length L (only RX) */
+#define BFLH 0x91 /* RX Buffer Length H (only RX) */
+#define BCRL 0x8c /* Byte Count Register L */
+#define BCRH 0x8d /* Byte Count Register H */
+
+/* Block Descriptor Structure */
+typedef struct {
+ unsigned long next; /* pointer to next block descriptor */
+ unsigned long ptbuf; /* buffer pointer */
+ unsigned short len; /* data length */
+ unsigned char status; /* status */
+ unsigned char filler[5]; /* alignment filler (16 bytes) */
+} pcsca_bd_t;
+
+/* Block Descriptor Structure */
+typedef struct {
+ u32 cp; /* pointer to next block descriptor */
+ u32 bp; /* buffer pointer */
+ u16 len; /* data length */
+ u8 stat; /* status */
+ u8 unused; /* pads to 4-byte boundary */
+}pkt_desc;
+
+
+/*
+ Descriptor Status definitions:
+
+ Bit Transmission Reception
+
+ 7 EOM EOM
+ 6 - Short Frame
+ 5 - Abort
+ 4 - Residual bit
+ 3 Underrun Overrun
+ 2 - CRC
+ 1 Ownership Ownership
+ 0 EOT -
+*/
+#define DST_EOT 0x01 /* End of transmit command */
+#define DST_OSB 0x02 /* Ownership bit */
+#define DST_CRC 0x04 /* CRC Error */
+#define DST_OVR 0x08 /* Overrun */
+#define DST_UDR 0x08 /* Underrun */
+#define DST_RBIT 0x10 /* Residual bit */
+#define DST_ABT 0x20 /* Abort */
+#define DST_SHRT 0x40 /* Short Frame */
+#define DST_EOM 0x80 /* End of Message */
+
+/* Packet Descriptor Status bits */
+
+#define ST_TX_EOM 0x80 /* End of frame */
+#define ST_TX_UNDRRUN 0x08
+#define ST_TX_OWNRSHP 0x02
+#define ST_TX_EOT 0x01 /* End of transmition */
+
+#define ST_RX_EOM 0x80 /* End of frame */
+#define ST_RX_SHORT 0x40 /* Short frame */
+#define ST_RX_ABORT 0x20 /* Abort */
+#define ST_RX_RESBIT 0x10 /* Residual bit */
+#define ST_RX_OVERRUN 0x08 /* Overrun */
+#define ST_RX_CRC 0x04 /* CRC */
+#define ST_RX_OWNRSHP 0x02
+
+#define ST_ERROR_MASK 0x7C
+
+/* Status Counter Registers */
+#define CMCR 0x158 /* Counter Master Ctl Reg */
+#define TECNTL 0x160 /* Tx EOM Counter L */
+#define TECNTM 0x161 /* Tx EOM Counter M */
+#define TECNTH 0x162 /* Tx EOM Counter H */
+#define TECCR 0x163 /* Tx EOM Counter Ctl Reg */
+#define URCNTL 0x164 /* Underrun Counter L */
+#define URCNTH 0x165 /* Underrun Counter H */
+#define URCCR 0x167 /* Underrun Counter Ctl Reg */
+#define RECNTL 0x168 /* Rx EOM Counter L */
+#define RECNTM 0x169 /* Rx EOM Counter M */
+#define RECNTH 0x16a /* Rx EOM Counter H */
+#define RECCR 0x16b /* Rx EOM Counter Ctl Reg */
+#define ORCNTL 0x16c /* Overrun Counter L */
+#define ORCNTH 0x16d /* Overrun Counter H */
+#define ORCCR 0x16f /* Overrun Counter Ctl Reg */
+#define CECNTL 0x170 /* CRC Counter L */
+#define CECNTH 0x171 /* CRC Counter H */
+#define CECCR 0x173 /* CRC Counter Ctl Reg */
+#define ABCNTL 0x174 /* Abort frame Counter L */
+#define ABCNTH 0x175 /* Abort frame Counter H */
+#define ABCCR 0x177 /* Abort frame Counter Ctl Reg */
+#define SHCNTL 0x178 /* Short frame Counter L */
+#define SHCNTH 0x179 /* Short frame Counter H */
+#define SHCCR 0x17b /* Short frame Counter Ctl Reg */
+#define RSCNTL 0x17c /* Residual bit Counter L */
+#define RSCNTH 0x17d /* Residual bit Counter H */
+#define RSCCR 0x17f /* Residual bit Counter Ctl Reg */
+
+/* Register Programming Constants */
+
+#define IR0_DMIC 0x00000001
+#define IR0_DMIB 0x00000002
+#define IR0_DMIA 0x00000004
+#define IR0_EFT 0x00000008
+#define IR0_DMAREQ 0x00010000
+#define IR0_TXINT 0x00020000
+#define IR0_RXINTB 0x00040000
+#define IR0_RXINTA 0x00080000
+#define IR0_TXRDY 0x00100000
+#define IR0_RXRDY 0x00200000
+
+#define MD0_CRC16_0 0x00
+#define MD0_CRC16_1 0x01
+#define MD0_CRC32 0x02
+#define MD0_CRC_CCITT 0x03
+#define MD0_CRCC0 0x04
+#define MD0_CRCC1 0x08
+#define MD0_AUTO_ENA 0x10
+#define MD0_ASYNC 0x00
+#define MD0_BY_MSYNC 0x20
+#define MD0_BY_BISYNC 0x40
+#define MD0_BY_EXT 0x60
+#define MD0_BIT_SYNC 0x80
+#define MD0_TRANSP 0xc0
+
+#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
+
+#define MD0_CRC_NONE 0x00
+#define MD0_CRC_16_0 0x04
+#define MD0_CRC_16 0x05
+#define MD0_CRC_ITU32 0x06
+#define MD0_CRC_ITU 0x07
+
+#define MD1_NOADDR 0x00
+#define MD1_SADDR1 0x40
+#define MD1_SADDR2 0x80
+#define MD1_DADDR 0xc0
+
+#define MD2_NRZI_IEEE 0x40
+#define MD2_MANCHESTER 0x80
+#define MD2_FM_MARK 0xA0
+#define MD2_FM_SPACE 0xC0
+#define MD2_LOOPBACK 0x03 /* Local data Loopback */
+
+#define MD2_F_DUPLEX 0x00
+#define MD2_AUTO_ECHO 0x01
+#define MD2_LOOP_HI_Z 0x02
+#define MD2_LOOP_MIR 0x03
+#define MD2_ADPLL_X8 0x00
+#define MD2_ADPLL_X16 0x08
+#define MD2_ADPLL_X32 0x10
+#define MD2_NRZ 0x00
+#define MD2_NRZI 0x20
+#define MD2_NRZ_IEEE 0x40
+#define MD2_MANCH 0x00
+#define MD2_FM1 0x20
+#define MD2_FM0 0x40
+#define MD2_FM 0x80
+
+#define CTL_RTS 0x01
+#define CTL_DTR 0x02
+#define CTL_SYN 0x04
+#define CTL_IDLC 0x10
+#define CTL_UDRNC 0x20
+#define CTL_URSKP 0x40
+#define CTL_URCT 0x80
+
+#define CTL_NORTS 0x01
+#define CTL_NODTR 0x02
+#define CTL_IDLE 0x10
+
+#define RXS_BR0 0x01
+#define RXS_BR1 0x02
+#define RXS_BR2 0x04
+#define RXS_BR3 0x08
+#define RXS_ECLK 0x00
+#define RXS_ECLK_NS 0x20
+#define RXS_IBRG 0x40
+#define RXS_PLL1 0x50
+#define RXS_PLL2 0x60
+#define RXS_PLL3 0x70
+#define RXS_DRTXC 0x80
+
+#define TXS_BR0 0x01
+#define TXS_BR1 0x02
+#define TXS_BR2 0x04
+#define TXS_BR3 0x08
+#define TXS_ECLK 0x00
+#define TXS_IBRG 0x40
+#define TXS_RCLK 0x60
+#define TXS_DTRXC 0x80
+
+#define EXS_RES0 0x01
+#define EXS_RES1 0x02
+#define EXS_RES2 0x04
+#define EXS_TES0 0x10
+#define EXS_TES1 0x20
+#define EXS_TES2 0x40
+
+#define CLK_BRG_MASK 0x0F
+#define CLK_PIN_OUT 0x80
+#define CLK_LINE 0x00 /* clock line input */
+#define CLK_BRG 0x40 /* internal baud rate generator */
+#define CLK_TX_RXCLK 0x60 /* TX clock from RX clock */
+
+#define CMD_RX_RST 0x11
+#define CMD_RX_ENA 0x12
+#define CMD_RX_DIS 0x13
+#define CMD_RX_CRC_INIT 0x14
+#define CMD_RX_MSG_REJ 0x15
+#define CMD_RX_MP_SRCH 0x16
+#define CMD_RX_CRC_EXC 0x17
+#define CMD_RX_CRC_FRC 0x18
+#define CMD_TX_RST 0x01
+#define CMD_TX_ENA 0x02
+#define CMD_TX_DISA 0x03
+#define CMD_TX_CRC_INIT 0x04
+#define CMD_TX_CRC_EXC 0x05
+#define CMD_TX_EOM 0x06
+#define CMD_TX_ABORT 0x07
+#define CMD_TX_MP_ON 0x08
+#define CMD_TX_BUF_CLR 0x09
+#define CMD_TX_DISB 0x0b
+#define CMD_CH_RST 0x21
+#define CMD_SRCH_MODE 0x31
+#define CMD_NOP 0x00
+
+#define CMD_RESET 0x21
+#define CMD_TX_ENABLE 0x02
+#define CMD_RX_ENABLE 0x12
+
+#define ST0_RXRDY 0x01
+#define ST0_TXRDY 0x02
+#define ST0_RXINTB 0x20
+#define ST0_RXINTA 0x40
+#define ST0_TXINT 0x80
+
+#define ST1_IDLE 0x01
+#define ST1_ABORT 0x02
+#define ST1_CDCD 0x04
+#define ST1_CCTS 0x08
+#define ST1_SYN_FLAG 0x10
+#define ST1_CLMD 0x20
+#define ST1_TXIDLE 0x40
+#define ST1_UDRN 0x80
+
+#define ST2_CRCE 0x04
+#define ST2_ONRN 0x08
+#define ST2_RBIT 0x10
+#define ST2_ABORT 0x20
+#define ST2_SHORT 0x40
+#define ST2_EOM 0x80
+
+#define ST3_RX_ENA 0x01
+#define ST3_TX_ENA 0x02
+#define ST3_DCD 0x04
+#define ST3_CTS 0x08
+#define ST3_SRCH_MODE 0x10
+#define ST3_SLOOP 0x20
+#define ST3_GPI 0x80
+
+#define ST4_RDNR 0x01
+#define ST4_RDCR 0x02
+#define ST4_TDNR 0x04
+#define ST4_TDCR 0x08
+#define ST4_OCLM 0x20
+#define ST4_CFT 0x40
+#define ST4_CGPI 0x80
+
+#define FST_CRCEF 0x04
+#define FST_OVRNF 0x08
+#define FST_RBIF 0x10
+#define FST_ABTF 0x20
+#define FST_SHRTF 0x40
+#define FST_EOMF 0x80
+
+#define IE0_RXRDY 0x01
+#define IE0_TXRDY 0x02
+#define IE0_RXINTB 0x20
+#define IE0_RXINTA 0x40
+#define IE0_TXINT 0x80
+#define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */
+#define IE0_CDCD 0x00000400 /* CD level change interrupt enable */
+
+#define IE1_IDLD 0x01
+#define IE1_ABTD 0x02
+#define IE1_CDCD 0x04
+#define IE1_CCTS 0x08
+#define IE1_SYNCD 0x10
+#define IE1_CLMD 0x20
+#define IE1_IDL 0x40
+#define IE1_UDRN 0x80
+
+#define IE2_CRCE 0x04
+#define IE2_OVRN 0x08
+#define IE2_RBIT 0x10
+#define IE2_ABT 0x20
+#define IE2_SHRT 0x40
+#define IE2_EOM 0x80
+
+#define IE4_RDNR 0x01
+#define IE4_RDCR 0x02
+#define IE4_TDNR 0x04
+#define IE4_TDCR 0x08
+#define IE4_OCLM 0x20
+#define IE4_CFT 0x40
+#define IE4_CGPI 0x80
+
+#define FIE_CRCEF 0x04
+#define FIE_OVRNF 0x08
+#define FIE_RBIF 0x10
+#define FIE_ABTF 0x20
+#define FIE_SHRTF 0x40
+#define FIE_EOMF 0x80
+
+#define DSR_DWE 0x01
+#define DSR_DE 0x02
+#define DSR_REF 0x04
+#define DSR_UDRF 0x04
+#define DSR_COA 0x08
+#define DSR_COF 0x10
+#define DSR_BOF 0x20
+#define DSR_EOM 0x40
+#define DSR_EOT 0x80
+
+#define DIR_REF 0x04
+#define DIR_UDRF 0x04
+#define DIR_COA 0x08
+#define DIR_COF 0x10
+#define DIR_BOF 0x20
+#define DIR_EOM 0x40
+#define DIR_EOT 0x80
+
+#define DIR_REFE 0x04
+#define DIR_UDRFE 0x04
+#define DIR_COAE 0x08
+#define DIR_COFE 0x10
+#define DIR_BOFE 0x20
+#define DIR_EOME 0x40
+#define DIR_EOTE 0x80
+
+#define DMR_CNTE 0x02
+#define DMR_NF 0x04
+#define DMR_SEOME 0x08
+#define DMR_TMOD 0x10
+
+#define DMER_DME 0x80 /* DMA Master Enable */
+
+#define DCR_SW_ABT 0x01
+#define DCR_FCT_CLR 0x02
+
+#define DCR_ABORT 0x01
+#define DCR_CLEAR_EOF 0x02
+
+#define PCR_COTE 0x80
+#define PCR_PR0 0x01
+#define PCR_PR1 0x02
+#define PCR_PR2 0x04
+#define PCR_CCC 0x08
+#define PCR_BRC 0x10
+#define PCR_OSB 0x40
+#define PCR_BURST 0x80
+
+#endif /* (__HD64572_H) */
diff --git a/drivers/net/wan/hd6457x.c b/drivers/net/wan/hd6457x.c
new file mode 100644
index 000000000000..d3743321a977
--- /dev/null
+++ b/drivers/net/wan/hd6457x.c
@@ -0,0 +1,853 @@
+/*
+ * Hitachi SCA HD64570 and HD64572 common driver for Linux
+ *
+ * Copyright (C) 1998-2003 Krzysztof Halasa
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * Sources of information:
+ * Hitachi HD64570 SCA User's Manual
+ * Hitachi HD64572 SCA-II User's Manual
+ *
+ * We use the following SCA memory map:
+ *
+ * Packet buffer descriptor rings - starting from winbase or win0base:
+ * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
+ * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
+ * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
+ * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
+ *
+ * Packet data buffers - starting from winbase + buff_offset:
+ * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
+ * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
+ * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
+ * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+#if (!defined (__HD64570_H) && !defined (__HD64572_H)) || \
+ (defined (__HD64570_H) && defined (__HD64572_H))
+#error Either hd64570.h or hd64572.h must be included
+#endif
+
+#define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
+#define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
+#define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
+
+#define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
+#define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
+#define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
+
+#ifdef __HD64570_H /* HD64570 */
+#define sca_outa(value, reg, card) sca_outw(value, reg, card)
+#define sca_ina(reg, card) sca_inw(reg, card)
+#define writea(value, ptr) writew(value, ptr)
+
+#else /* HD64572 */
+#define sca_outa(value, reg, card) sca_outl(value, reg, card)
+#define sca_ina(reg, card) sca_inl(reg, card)
+#define writea(value, ptr) writel(value, ptr)
+#endif
+
+static inline struct net_device *port_to_dev(port_t *port)
+{
+ return port->dev;
+}
+
+static inline int sca_intr_status(card_t *card)
+{
+ u8 result = 0;
+
+#ifdef __HD64570_H /* HD64570 */
+ u8 isr0 = sca_in(ISR0, card);
+ u8 isr1 = sca_in(ISR1, card);
+
+ if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
+ if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
+ if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
+ if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
+ if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
+ if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
+
+#else /* HD64572 */
+ u32 isr0 = sca_inl(ISR0, card);
+
+ if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0);
+ if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0);
+ if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1);
+ if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1);
+ if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0);
+ if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1);
+
+#endif /* HD64570 vs HD64572 */
+
+ if (!(result & SCA_INTR_DMAC_TX(0)))
+ if (sca_in(DSR_TX(0), card) & DSR_EOM)
+ result |= SCA_INTR_DMAC_TX(0);
+ if (!(result & SCA_INTR_DMAC_TX(1)))
+ if (sca_in(DSR_TX(1), card) & DSR_EOM)
+ result |= SCA_INTR_DMAC_TX(1);
+
+ return result;
+}
+
+static inline port_t* dev_to_port(struct net_device *dev)
+{
+ return dev_to_hdlc(dev)->priv;
+}
+
+static inline u16 next_desc(port_t *port, u16 desc, int transmit)
+{
+ return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
+ : port_to_card(port)->rx_ring_buffers);
+}
+
+
+
+static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
+{
+ u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
+ u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
+
+ desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
+ return log_node(port) * (rx_buffs + tx_buffs) +
+ transmit * rx_buffs + desc;
+}
+
+
+
+static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
+{
+ /* Descriptor offset always fits in 16 bytes */
+ return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
+}
+
+
+
+static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, int transmit)
+{
+#ifdef PAGE0_ALWAYS_MAPPED
+ return (pkt_desc __iomem *)(win0base(port_to_card(port))
+ + desc_offset(port, desc, transmit));
+#else
+ return (pkt_desc __iomem *)(winbase(port_to_card(port))
+ + desc_offset(port, desc, transmit));
+#endif
+}
+
+
+
+static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
+{
+ return port_to_card(port)->buff_offset +
+ desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
+}
+
+
+
+static void sca_init_sync_port(port_t *port)
+{
+ card_t *card = port_to_card(port);
+ int transmit, i;
+
+ port->rxin = 0;
+ port->txin = 0;
+ port->txlast = 0;
+
+#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
+ openwin(card, 0);
+#endif
+
+ for (transmit = 0; transmit < 2; transmit++) {
+ u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
+ u16 buffs = transmit ? card->tx_ring_buffers
+ : card->rx_ring_buffers;
+
+ for (i = 0; i < buffs; i++) {
+ pkt_desc __iomem *desc = desc_address(port, i, transmit);
+ u16 chain_off = desc_offset(port, i + 1, transmit);
+ u32 buff_off = buffer_offset(port, i, transmit);
+
+ writea(chain_off, &desc->cp);
+ writel(buff_off, &desc->bp);
+ writew(0, &desc->len);
+ writeb(0, &desc->stat);
+ }
+
+ /* DMA disable - to halt state */
+ sca_out(0, transmit ? DSR_TX(phy_node(port)) :
+ DSR_RX(phy_node(port)), card);
+ /* software ABORT - to initial state */
+ sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
+ DCR_RX(phy_node(port)), card);
+
+#ifdef __HD64570_H
+ sca_out(0, dmac + CPB, card); /* pointer base */
+#endif
+ /* current desc addr */
+ sca_outa(desc_offset(port, 0, transmit), dmac + CDAL, card);
+ if (!transmit)
+ sca_outa(desc_offset(port, buffs - 1, transmit),
+ dmac + EDAL, card);
+ else
+ sca_outa(desc_offset(port, 0, transmit), dmac + EDAL,
+ card);
+
+ /* clear frame end interrupt counter */
+ sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
+ DCR_RX(phy_node(port)), card);
+
+ if (!transmit) { /* Receive */
+ /* set buffer length */
+ sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
+ /* Chain mode, Multi-frame */
+ sca_out(0x14, DMR_RX(phy_node(port)), card);
+ sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
+ card);
+ /* DMA enable */
+ sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
+ } else { /* Transmit */
+ /* Chain mode, Multi-frame */
+ sca_out(0x14, DMR_TX(phy_node(port)), card);
+ /* enable underflow interrupts */
+ sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
+ }
+ }
+
+ hdlc_set_carrier(!(sca_in(get_msci(port) + ST3, card) & ST3_DCD),
+ port_to_dev(port));
+}
+
+
+
+#ifdef NEED_SCA_MSCI_INTR
+/* MSCI interrupt service */
+static inline void sca_msci_intr(port_t *port)
+{
+ u16 msci = get_msci(port);
+ card_t* card = port_to_card(port);
+ u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
+
+ /* Reset MSCI TX underrun and CDCD status bit */
+ sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
+
+ if (stat & ST1_UDRN) {
+ struct net_device_stats *stats = hdlc_stats(port_to_dev(port));
+ stats->tx_errors++; /* TX Underrun error detected */
+ stats->tx_fifo_errors++;
+ }
+
+ if (stat & ST1_CDCD)
+ hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD),
+ port_to_dev(port));
+}
+#endif
+
+
+
+static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, u16 rxin)
+{
+ struct net_device *dev = port_to_dev(port);
+ struct net_device_stats *stats = hdlc_stats(dev);
+ struct sk_buff *skb;
+ u16 len;
+ u32 buff;
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ u32 maxlen;
+ u8 page;
+#endif
+
+ len = readw(&desc->len);
+ skb = dev_alloc_skb(len);
+ if (!skb) {
+ stats->rx_dropped++;
+ return;
+ }
+
+ buff = buffer_offset(port, rxin, 0);
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ page = buff / winsize(card);
+ buff = buff % winsize(card);
+ maxlen = winsize(card) - buff;
+
+ openwin(card, page);
+
+ if (len > maxlen) {
+ memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
+ openwin(card, page + 1);
+ memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
+ } else
+#endif
+ memcpy_fromio(skb->data, winbase(card) + buff, len);
+
+#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
+ /* select pkt_desc table page back */
+ openwin(card, 0);
+#endif
+ skb_put(skb, len);
+#ifdef DEBUG_PKT
+ printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
+ debug_frame(skb);
+#endif
+ stats->rx_packets++;
+ stats->rx_bytes += skb->len;
+ dev->last_rx = jiffies;
+ skb->protocol = hdlc_type_trans(skb, dev);
+ netif_rx(skb);
+}
+
+
+
+/* Receive DMA interrupt service */
+static inline void sca_rx_intr(port_t *port)
+{
+ u16 dmac = get_dmac_rx(port);
+ card_t *card = port_to_card(port);
+ u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
+ struct net_device_stats *stats = hdlc_stats(port_to_dev(port));
+
+ /* Reset DSR status bits */
+ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
+ DSR_RX(phy_node(port)), card);
+
+ if (stat & DSR_BOF)
+ stats->rx_over_errors++; /* Dropped one or more frames */
+
+ while (1) {
+ u32 desc_off = desc_offset(port, port->rxin, 0);
+ pkt_desc __iomem *desc;
+ u32 cda = sca_ina(dmac + CDAL, card);
+
+ if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
+ break; /* No frame received */
+
+ desc = desc_address(port, port->rxin, 0);
+ stat = readb(&desc->stat);
+ if (!(stat & ST_RX_EOM))
+ port->rxpart = 1; /* partial frame received */
+ else if ((stat & ST_ERROR_MASK) || port->rxpart) {
+ stats->rx_errors++;
+ if (stat & ST_RX_OVERRUN) stats->rx_fifo_errors++;
+ else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
+ ST_RX_RESBIT)) || port->rxpart)
+ stats->rx_frame_errors++;
+ else if (stat & ST_RX_CRC) stats->rx_crc_errors++;
+ if (stat & ST_RX_EOM)
+ port->rxpart = 0; /* received last fragment */
+ } else
+ sca_rx(card, port, desc, port->rxin);
+
+ /* Set new error descriptor address */
+ sca_outa(desc_off, dmac + EDAL, card);
+ port->rxin = next_desc(port, port->rxin, 0);
+ }
+
+ /* make sure RX DMA is enabled */
+ sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
+}
+
+
+
+/* Transmit DMA interrupt service */
+static inline void sca_tx_intr(port_t *port)
+{
+ struct net_device *dev = port_to_dev(port);
+ struct net_device_stats *stats = hdlc_stats(dev);
+ u16 dmac = get_dmac_tx(port);
+ card_t* card = port_to_card(port);
+ u8 stat;
+
+ spin_lock(&port->lock);
+
+ stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
+
+ /* Reset DSR status bits */
+ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
+ DSR_TX(phy_node(port)), card);
+
+ while (1) {
+ pkt_desc __iomem *desc;
+
+ u32 desc_off = desc_offset(port, port->txlast, 1);
+ u32 cda = sca_ina(dmac + CDAL, card);
+ if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
+ break; /* Transmitter is/will_be sending this frame */
+
+ desc = desc_address(port, port->txlast, 1);
+ stats->tx_packets++;
+ stats->tx_bytes += readw(&desc->len);
+ writeb(0, &desc->stat); /* Free descriptor */
+ port->txlast = next_desc(port, port->txlast, 1);
+ }
+
+ netif_wake_queue(dev);
+ spin_unlock(&port->lock);
+}
+
+
+
+static irqreturn_t sca_intr(int irq, void* dev_id, struct pt_regs *regs)
+{
+ card_t *card = dev_id;
+ int i;
+ u8 stat;
+ int handled = 0;
+
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ u8 page = sca_get_page(card);
+#endif
+
+ while((stat = sca_intr_status(card)) != 0) {
+ handled = 1;
+ for (i = 0; i < 2; i++) {
+ port_t *port = get_port(card, i);
+ if (port) {
+ if (stat & SCA_INTR_MSCI(i))
+ sca_msci_intr(port);
+
+ if (stat & SCA_INTR_DMAC_RX(i))
+ sca_rx_intr(port);
+
+ if (stat & SCA_INTR_DMAC_TX(i))
+ sca_tx_intr(port);
+ }
+ }
+ }
+
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ openwin(card, page); /* Restore original page */
+#endif
+ return IRQ_RETVAL(handled);
+}
+
+
+
+static void sca_set_port(port_t *port)
+{
+ card_t* card = port_to_card(port);
+ u16 msci = get_msci(port);
+ u8 md2 = sca_in(msci + MD2, card);
+ unsigned int tmc, br = 10, brv = 1024;
+
+
+ if (port->settings.clock_rate > 0) {
+ /* Try lower br for better accuracy*/
+ do {
+ br--;
+ brv >>= 1; /* brv = 2^9 = 512 max in specs */
+
+ /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
+ tmc = CLOCK_BASE / brv / port->settings.clock_rate;
+ }while (br > 1 && tmc <= 128);
+
+ if (tmc < 1) {
+ tmc = 1;
+ br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
+ brv = 1;
+ } else if (tmc > 255)
+ tmc = 256; /* tmc=0 means 256 - low baud rates */
+
+ port->settings.clock_rate = CLOCK_BASE / brv / tmc;
+ } else {
+ br = 9; /* Minimum clock rate */
+ tmc = 256; /* 8bit = 0 */
+ port->settings.clock_rate = CLOCK_BASE / (256 * 512);
+ }
+
+ port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
+ port->txs = (port->txs & ~CLK_BRG_MASK) | br;
+ port->tmc = tmc;
+
+ /* baud divisor - time constant*/
+#ifdef __HD64570_H
+ sca_out(port->tmc, msci + TMC, card);
+#else
+ sca_out(port->tmc, msci + TMCR, card);
+ sca_out(port->tmc, msci + TMCT, card);
+#endif
+
+ /* Set BRG bits */
+ sca_out(port->rxs, msci + RXS, card);
+ sca_out(port->txs, msci + TXS, card);
+
+ if (port->settings.loopback)
+ md2 |= MD2_LOOPBACK;
+ else
+ md2 &= ~MD2_LOOPBACK;
+
+ sca_out(md2, msci + MD2, card);
+
+}
+
+
+
+static void sca_open(struct net_device *dev)
+{
+ port_t *port = dev_to_port(dev);
+ card_t* card = port_to_card(port);
+ u16 msci = get_msci(port);
+ u8 md0, md2;
+
+ switch(port->encoding) {
+ case ENCODING_NRZ: md2 = MD2_NRZ; break;
+ case ENCODING_NRZI: md2 = MD2_NRZI; break;
+ case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
+ case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
+ default: md2 = MD2_MANCHESTER;
+ }
+
+ if (port->settings.loopback)
+ md2 |= MD2_LOOPBACK;
+
+ switch(port->parity) {
+ case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
+ case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
+#ifdef __HD64570_H
+ case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
+#else
+ case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
+#endif
+ case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
+ default: md0 = MD0_HDLC | MD0_CRC_NONE;
+ }
+
+ sca_out(CMD_RESET, msci + CMD, card);
+ sca_out(md0, msci + MD0, card);
+ sca_out(0x00, msci + MD1, card); /* no address field check */
+ sca_out(md2, msci + MD2, card);
+ sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
+#ifdef __HD64570_H
+ sca_out(CTL_IDLE, msci + CTL, card);
+#else
+ /* Skip the rest of underrun frame */
+ sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
+#endif
+
+#ifdef __HD64570_H
+ /* Allow at least 8 bytes before requesting RX DMA operation */
+ /* TX with higher priority and possibly with shorter transfers */
+ sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
+ sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
+ sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
+#else
+ sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
+ sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
+ sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
+ sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
+ sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
+#endif
+
+/* We're using the following interrupts:
+ - TXINT (DMAC completed all transmisions, underrun or DCD change)
+ - all DMA interrupts
+*/
+
+ hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD), dev);
+
+#ifdef __HD64570_H
+ /* MSCI TX INT and RX INT A IRQ enable */
+ sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
+ sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
+ sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
+ IER0, card); /* TXINT and RXINT */
+ /* enable DMA IRQ */
+ sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
+ IER1, card);
+#else
+ /* MSCI TXINT and RXINTA interrupt enable */
+ sca_outl(IE0_TXINT | IE0_RXINTA | IE0_UDRN | IE0_CDCD, msci + IE0,
+ card);
+ /* DMA & MSCI IRQ enable */
+ sca_outl(sca_inl(IER0, card) |
+ (phy_node(port) ? 0x0A006600 : 0x000A0066), IER0, card);
+#endif
+
+#ifdef __HD64570_H
+ sca_out(port->tmc, msci + TMC, card); /* Restore registers */
+#else
+ sca_out(port->tmc, msci + TMCR, card);
+ sca_out(port->tmc, msci + TMCT, card);
+#endif
+ sca_out(port->rxs, msci + RXS, card);
+ sca_out(port->txs, msci + TXS, card);
+ sca_out(CMD_TX_ENABLE, msci + CMD, card);
+ sca_out(CMD_RX_ENABLE, msci + CMD, card);
+
+ netif_start_queue(dev);
+}
+
+
+
+static void sca_close(struct net_device *dev)
+{
+ port_t *port = dev_to_port(dev);
+ card_t* card = port_to_card(port);
+
+ /* reset channel */
+ sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
+#ifdef __HD64570_H
+ /* disable MSCI interrupts */
+ sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
+ IER0, card);
+ /* disable DMA interrupts */
+ sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
+ IER1, card);
+#else
+ /* disable DMA & MSCI IRQ */
+ sca_outl(sca_inl(IER0, card) &
+ (phy_node(port) ? 0x00FF00FF : 0xFF00FF00), IER0, card);
+#endif
+ netif_stop_queue(dev);
+}
+
+
+
+static int sca_attach(struct net_device *dev, unsigned short encoding,
+ unsigned short parity)
+{
+ if (encoding != ENCODING_NRZ &&
+ encoding != ENCODING_NRZI &&
+ encoding != ENCODING_FM_MARK &&
+ encoding != ENCODING_FM_SPACE &&
+ encoding != ENCODING_MANCHESTER)
+ return -EINVAL;
+
+ if (parity != PARITY_NONE &&
+ parity != PARITY_CRC16_PR0 &&
+ parity != PARITY_CRC16_PR1 &&
+#ifdef __HD64570_H
+ parity != PARITY_CRC16_PR0_CCITT &&
+#else
+ parity != PARITY_CRC32_PR1_CCITT &&
+#endif
+ parity != PARITY_CRC16_PR1_CCITT)
+ return -EINVAL;
+
+ dev_to_port(dev)->encoding = encoding;
+ dev_to_port(dev)->parity = parity;
+ return 0;
+}
+
+
+
+#ifdef DEBUG_RINGS
+static void sca_dump_rings(struct net_device *dev)
+{
+ port_t *port = dev_to_port(dev);
+ card_t *card = port_to_card(port);
+ u16 cnt;
+#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
+ u8 page;
+#endif
+
+#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
+ page = sca_get_page(card);
+ openwin(card, 0);
+#endif
+
+ printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
+ sca_ina(get_dmac_rx(port) + CDAL, card),
+ sca_ina(get_dmac_rx(port) + EDAL, card),
+ sca_in(DSR_RX(phy_node(port)), card), port->rxin,
+ sca_in(DSR_RX(phy_node(port)), card) & DSR_DE?"":"in");
+ for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
+ printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
+
+ printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
+ "last=%u %sactive",
+ sca_ina(get_dmac_tx(port) + CDAL, card),
+ sca_ina(get_dmac_tx(port) + EDAL, card),
+ sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
+ sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
+
+ for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
+ printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
+ printk("\n");
+
+ printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, "
+ "ST: %02x %02x %02x %02x"
+#ifdef __HD64572_H
+ " %02x"
+#endif
+ ", FST: %02x CST: %02x %02x\n",
+ sca_in(get_msci(port) + MD0, card),
+ sca_in(get_msci(port) + MD1, card),
+ sca_in(get_msci(port) + MD2, card),
+ sca_in(get_msci(port) + ST0, card),
+ sca_in(get_msci(port) + ST1, card),
+ sca_in(get_msci(port) + ST2, card),
+ sca_in(get_msci(port) + ST3, card),
+#ifdef __HD64572_H
+ sca_in(get_msci(port) + ST4, card),
+#endif
+ sca_in(get_msci(port) + FST, card),
+ sca_in(get_msci(port) + CST0, card),
+ sca_in(get_msci(port) + CST1, card));
+
+#ifdef __HD64572_H
+ printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
+ sca_inl(ISR0, card), sca_inl(ISR1, card));
+#else
+ printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
+ sca_in(ISR1, card), sca_in(ISR2, card));
+#endif
+
+#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
+ openwin(card, page); /* Restore original page */
+#endif
+}
+#endif /* DEBUG_RINGS */
+
+
+
+static int sca_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ port_t *port = dev_to_port(dev);
+ card_t *card = port_to_card(port);
+ pkt_desc __iomem *desc;
+ u32 buff, len;
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ u8 page;
+ u32 maxlen;
+#endif
+
+ spin_lock_irq(&port->lock);
+
+ desc = desc_address(port, port->txin + 1, 1);
+ if (readb(&desc->stat)) { /* allow 1 packet gap */
+ /* should never happen - previous xmit should stop queue */
+#ifdef DEBUG_PKT
+ printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
+#endif
+ netif_stop_queue(dev);
+ spin_unlock_irq(&port->lock);
+ return 1; /* request packet to be queued */
+ }
+
+#ifdef DEBUG_PKT
+ printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
+ debug_frame(skb);
+#endif
+
+ desc = desc_address(port, port->txin, 1);
+ buff = buffer_offset(port, port->txin, 1);
+ len = skb->len;
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ page = buff / winsize(card);
+ buff = buff % winsize(card);
+ maxlen = winsize(card) - buff;
+
+ openwin(card, page);
+ if (len > maxlen) {
+ memcpy_toio(winbase(card) + buff, skb->data, maxlen);
+ openwin(card, page + 1);
+ memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
+ }
+ else
+#endif
+ memcpy_toio(winbase(card) + buff, skb->data, len);
+
+#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
+ openwin(card, 0); /* select pkt_desc table page back */
+#endif
+ writew(len, &desc->len);
+ writeb(ST_TX_EOM, &desc->stat);
+ dev->trans_start = jiffies;
+
+ port->txin = next_desc(port, port->txin, 1);
+ sca_outa(desc_offset(port, port->txin, 1),
+ get_dmac_tx(port) + EDAL, card);
+
+ sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
+
+ desc = desc_address(port, port->txin + 1, 1);
+ if (readb(&desc->stat)) /* allow 1 packet gap */
+ netif_stop_queue(dev);
+
+ spin_unlock_irq(&port->lock);
+
+ dev_kfree_skb(skb);
+ return 0;
+}
+
+
+
+#ifdef NEED_DETECT_RAM
+static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize)
+{
+ /* Round RAM size to 32 bits, fill from end to start */
+ u32 i = ramsize &= ~3;
+
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ u32 size = winsize(card);
+
+ openwin(card, (i - 4) / size); /* select last window */
+#endif
+ do {
+ i -= 4;
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ if ((i + 4) % size == 0)
+ openwin(card, i / size);
+ writel(i ^ 0x12345678, rambase + i % size);
+#else
+ writel(i ^ 0x12345678, rambase + i);
+#endif
+ }while (i > 0);
+
+ for (i = 0; i < ramsize ; i += 4) {
+#ifndef ALL_PAGES_ALWAYS_MAPPED
+ if (i % size == 0)
+ openwin(card, i / size);
+
+ if (readl(rambase + i % size) != (i ^ 0x12345678))
+ break;
+#else
+ if (readl(rambase + i) != (i ^ 0x12345678))
+ break;
+#endif
+ }
+
+ return i;
+}
+#endif /* NEED_DETECT_RAM */
+
+
+
+static void __devinit sca_init(card_t *card, int wait_states)
+{
+ sca_out(wait_states, WCRL, card); /* Wait Control */
+ sca_out(wait_states, WCRM, card);
+ sca_out(wait_states, WCRH, card);
+
+ sca_out(0, DMER, card); /* DMA Master disable */
+ sca_out(0x03, PCR, card); /* DMA priority */
+ sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
+ sca_out(0, DSR_TX(0), card);
+ sca_out(0, DSR_RX(1), card);
+ sca_out(0, DSR_TX(1), card);
+ sca_out(DMER_DME, DMER, card); /* DMA Master enable */
+}
diff --git a/drivers/net/wan/hdlc_cisco.c b/drivers/net/wan/hdlc_cisco.c
new file mode 100644
index 000000000000..c1b6896d7007
--- /dev/null
+++ b/drivers/net/wan/hdlc_cisco.c
@@ -0,0 +1,330 @@
+/*
+ * Generic HDLC support routines for Linux
+ * Cisco HDLC support
+ *
+ * Copyright (C) 2000 - 2003 Krzysztof Halasa
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#undef DEBUG_HARD_HEADER
+
+#define CISCO_MULTICAST 0x8F /* Cisco multicast address */
+#define CISCO_UNICAST 0x0F /* Cisco unicast address */
+#define CISCO_KEEPALIVE 0x8035 /* Cisco keepalive protocol */
+#define CISCO_SYS_INFO 0x2000 /* Cisco interface/system info */
+#define CISCO_ADDR_REQ 0 /* Cisco address request */
+#define CISCO_ADDR_REPLY 1 /* Cisco address reply */
+#define CISCO_KEEPALIVE_REQ 2 /* Cisco keepalive request */
+
+
+static int cisco_hard_header(struct sk_buff *skb, struct net_device *dev,
+ u16 type, void *daddr, void *saddr,
+ unsigned int len)
+{
+ hdlc_header *data;
+#ifdef DEBUG_HARD_HEADER
+ printk(KERN_DEBUG "%s: cisco_hard_header called\n", dev->name);
+#endif
+
+ skb_push(skb, sizeof(hdlc_header));
+ data = (hdlc_header*)skb->data;
+ if (type == CISCO_KEEPALIVE)
+ data->address = CISCO_MULTICAST;
+ else
+ data->address = CISCO_UNICAST;
+ data->control = 0;
+ data->protocol = htons(type);
+
+ return sizeof(hdlc_header);
+}
+
+
+
+static void cisco_keepalive_send(struct net_device *dev, u32 type,
+ u32 par1, u32 par2)
+{
+ struct sk_buff *skb;
+ cisco_packet *data;
+
+ skb = dev_alloc_skb(sizeof(hdlc_header) + sizeof(cisco_packet));
+ if (!skb) {
+ printk(KERN_WARNING
+ "%s: Memory squeeze on cisco_keepalive_send()\n",
+ dev->name);
+ return;
+ }
+ skb_reserve(skb, 4);
+ cisco_hard_header(skb, dev, CISCO_KEEPALIVE, NULL, NULL, 0);
+ data = (cisco_packet*)skb->tail;
+
+ data->type = htonl(type);
+ data->par1 = htonl(par1);
+ data->par2 = htonl(par2);
+ data->rel = 0xFFFF;
+ /* we will need do_div here if 1000 % HZ != 0 */
+ data->time = htonl((jiffies - INITIAL_JIFFIES) * (1000 / HZ));
+
+ skb_put(skb, sizeof(cisco_packet));
+ skb->priority = TC_PRIO_CONTROL;
+ skb->dev = dev;
+ skb->nh.raw = skb->data;
+
+ dev_queue_xmit(skb);
+}
+
+
+
+static unsigned short cisco_type_trans(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ hdlc_header *data = (hdlc_header*)skb->data;
+
+ if (skb->len < sizeof(hdlc_header))
+ return __constant_htons(ETH_P_HDLC);
+
+ if (data->address != CISCO_MULTICAST &&
+ data->address != CISCO_UNICAST)
+ return __constant_htons(ETH_P_HDLC);
+
+ switch(data->protocol) {
+ case __constant_htons(ETH_P_IP):
+ case __constant_htons(ETH_P_IPX):
+ case __constant_htons(ETH_P_IPV6):
+ skb_pull(skb, sizeof(hdlc_header));
+ return data->protocol;
+ default:
+ return __constant_htons(ETH_P_HDLC);
+ }
+}
+
+
+static int cisco_rx(struct sk_buff *skb)
+{
+ struct net_device *dev = skb->dev;
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ hdlc_header *data = (hdlc_header*)skb->data;
+ cisco_packet *cisco_data;
+ struct in_device *in_dev;
+ u32 addr, mask;
+
+ if (skb->len < sizeof(hdlc_header))
+ goto rx_error;
+
+ if (data->address != CISCO_MULTICAST &&
+ data->address != CISCO_UNICAST)
+ goto rx_error;
+
+ switch(ntohs(data->protocol)) {
+ case CISCO_SYS_INFO:
+ /* Packet is not needed, drop it. */
+ dev_kfree_skb_any(skb);
+ return NET_RX_SUCCESS;
+
+ case CISCO_KEEPALIVE:
+ if (skb->len != sizeof(hdlc_header) + CISCO_PACKET_LEN &&
+ skb->len != sizeof(hdlc_header) + CISCO_BIG_PACKET_LEN) {
+ printk(KERN_INFO "%s: Invalid length of Cisco "
+ "control packet (%d bytes)\n",
+ dev->name, skb->len);
+ goto rx_error;
+ }
+
+ cisco_data = (cisco_packet*)(skb->data + sizeof(hdlc_header));
+
+ switch(ntohl (cisco_data->type)) {
+ case CISCO_ADDR_REQ: /* Stolen from syncppp.c :-) */
+ in_dev = dev->ip_ptr;
+ addr = 0;
+ mask = ~0; /* is the mask correct? */
+
+ if (in_dev != NULL) {
+ struct in_ifaddr **ifap = &in_dev->ifa_list;
+
+ while (*ifap != NULL) {
+ if (strcmp(dev->name,
+ (*ifap)->ifa_label) == 0) {
+ addr = (*ifap)->ifa_local;
+ mask = (*ifap)->ifa_mask;
+ break;
+ }
+ ifap = &(*ifap)->ifa_next;
+ }
+
+ cisco_keepalive_send(dev, CISCO_ADDR_REPLY,
+ addr, mask);
+ }
+ dev_kfree_skb_any(skb);
+ return NET_RX_SUCCESS;
+
+ case CISCO_ADDR_REPLY:
+ printk(KERN_INFO "%s: Unexpected Cisco IP address "
+ "reply\n", dev->name);
+ goto rx_error;
+
+ case CISCO_KEEPALIVE_REQ:
+ hdlc->state.cisco.rxseq = ntohl(cisco_data->par1);
+ if (hdlc->state.cisco.request_sent &&
+ ntohl(cisco_data->par2)==hdlc->state.cisco.txseq) {
+ hdlc->state.cisco.last_poll = jiffies;
+ if (!hdlc->state.cisco.up) {
+ u32 sec, min, hrs, days;
+ sec = ntohl(cisco_data->time) / 1000;
+ min = sec / 60; sec -= min * 60;
+ hrs = min / 60; min -= hrs * 60;
+ days = hrs / 24; hrs -= days * 24;
+ printk(KERN_INFO "%s: Link up (peer "
+ "uptime %ud%uh%um%us)\n",
+ dev->name, days, hrs,
+ min, sec);
+ netif_carrier_on(dev);
+ hdlc->state.cisco.up = 1;
+ }
+ }
+
+ dev_kfree_skb_any(skb);
+ return NET_RX_SUCCESS;
+ } /* switch(keepalive type) */
+ } /* switch(protocol) */
+
+ printk(KERN_INFO "%s: Unsupported protocol %x\n", dev->name,
+ data->protocol);
+ dev_kfree_skb_any(skb);
+ return NET_RX_DROP;
+
+ rx_error:
+ hdlc->stats.rx_errors++; /* Mark error */
+ dev_kfree_skb_any(skb);
+ return NET_RX_DROP;
+}
+
+
+
+static void cisco_timer(unsigned long arg)
+{
+ struct net_device *dev = (struct net_device *)arg;
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+
+ if (hdlc->state.cisco.up &&
+ time_after(jiffies, hdlc->state.cisco.last_poll +
+ hdlc->state.cisco.settings.timeout * HZ)) {
+ hdlc->state.cisco.up = 0;
+ printk(KERN_INFO "%s: Link down\n", dev->name);
+ netif_carrier_off(dev);
+ }
+
+ cisco_keepalive_send(dev, CISCO_KEEPALIVE_REQ,
+ ++hdlc->state.cisco.txseq,
+ hdlc->state.cisco.rxseq);
+ hdlc->state.cisco.request_sent = 1;
+ hdlc->state.cisco.timer.expires = jiffies +
+ hdlc->state.cisco.settings.interval * HZ;
+ hdlc->state.cisco.timer.function = cisco_timer;
+ hdlc->state.cisco.timer.data = arg;
+ add_timer(&hdlc->state.cisco.timer);
+}
+
+
+
+static void cisco_start(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ hdlc->state.cisco.up = 0;
+ hdlc->state.cisco.request_sent = 0;
+ hdlc->state.cisco.txseq = hdlc->state.cisco.rxseq = 0;
+
+ init_timer(&hdlc->state.cisco.timer);
+ hdlc->state.cisco.timer.expires = jiffies + HZ; /*First poll after 1s*/
+ hdlc->state.cisco.timer.function = cisco_timer;
+ hdlc->state.cisco.timer.data = (unsigned long)dev;
+ add_timer(&hdlc->state.cisco.timer);
+}
+
+
+
+static void cisco_stop(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ del_timer_sync(&hdlc->state.cisco.timer);
+ if (netif_carrier_ok(dev))
+ netif_carrier_off(dev);
+ hdlc->state.cisco.up = 0;
+ hdlc->state.cisco.request_sent = 0;
+}
+
+
+
+int hdlc_cisco_ioctl(struct net_device *dev, struct ifreq *ifr)
+{
+ cisco_proto __user *cisco_s = ifr->ifr_settings.ifs_ifsu.cisco;
+ const size_t size = sizeof(cisco_proto);
+ cisco_proto new_settings;
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ int result;
+
+ switch (ifr->ifr_settings.type) {
+ case IF_GET_PROTO:
+ ifr->ifr_settings.type = IF_PROTO_CISCO;
+ if (ifr->ifr_settings.size < size) {
+ ifr->ifr_settings.size = size; /* data size wanted */
+ return -ENOBUFS;
+ }
+ if (copy_to_user(cisco_s, &hdlc->state.cisco.settings, size))
+ return -EFAULT;
+ return 0;
+
+ case IF_PROTO_CISCO:
+ if(!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ if(dev->flags & IFF_UP)
+ return -EBUSY;
+
+ if (copy_from_user(&new_settings, cisco_s, size))
+ return -EFAULT;
+
+ if (new_settings.interval < 1 ||
+ new_settings.timeout < 2)
+ return -EINVAL;
+
+ result=hdlc->attach(dev, ENCODING_NRZ,PARITY_CRC16_PR1_CCITT);
+
+ if (result)
+ return result;
+
+ hdlc_proto_detach(hdlc);
+ memcpy(&hdlc->state.cisco.settings, &new_settings, size);
+ memset(&hdlc->proto, 0, sizeof(hdlc->proto));
+
+ hdlc->proto.start = cisco_start;
+ hdlc->proto.stop = cisco_stop;
+ hdlc->proto.netif_rx = cisco_rx;
+ hdlc->proto.type_trans = cisco_type_trans;
+ hdlc->proto.id = IF_PROTO_CISCO;
+ dev->hard_start_xmit = hdlc->xmit;
+ dev->hard_header = cisco_hard_header;
+ dev->hard_header_cache = NULL;
+ dev->type = ARPHRD_CISCO;
+ dev->flags = IFF_POINTOPOINT | IFF_NOARP;
+ dev->addr_len = 0;
+ return 0;
+ }
+
+ return -EINVAL;
+}
diff --git a/drivers/net/wan/hdlc_fr.c b/drivers/net/wan/hdlc_fr.c
new file mode 100644
index 000000000000..7f450b51a6cb
--- /dev/null
+++ b/drivers/net/wan/hdlc_fr.c
@@ -0,0 +1,1237 @@
+/*
+ * Generic HDLC support routines for Linux
+ * Frame Relay support
+ *
+ * Copyright (C) 1999 - 2003 Krzysztof Halasa
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+
+ Theory of PVC state
+
+ DCE mode:
+
+ (exist,new) -> 0,0 when "PVC create" or if "link unreliable"
+ 0,x -> 1,1 if "link reliable" when sending FULL STATUS
+ 1,1 -> 1,0 if received FULL STATUS ACK
+
+ (active) -> 0 when "ifconfig PVC down" or "link unreliable" or "PVC create"
+ -> 1 when "PVC up" and (exist,new) = 1,0
+
+ DTE mode:
+ (exist,new,active) = FULL STATUS if "link reliable"
+ = 0, 0, 0 if "link unreliable"
+ No LMI:
+ active = open and "link reliable"
+ exist = new = not used
+
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#undef DEBUG_PKT
+#undef DEBUG_ECN
+#undef DEBUG_LINK
+
+#define MAXLEN_LMISTAT 20 /* max size of status enquiry frame */
+
+#define PVC_STATE_NEW 0x01
+#define PVC_STATE_ACTIVE 0x02
+#define PVC_STATE_FECN 0x08 /* FECN condition */
+#define PVC_STATE_BECN 0x10 /* BECN condition */
+
+
+#define FR_UI 0x03
+#define FR_PAD 0x00
+
+#define NLPID_IP 0xCC
+#define NLPID_IPV6 0x8E
+#define NLPID_SNAP 0x80
+#define NLPID_PAD 0x00
+#define NLPID_Q933 0x08
+
+
+#define LMI_DLCI 0 /* LMI DLCI */
+#define LMI_PROTO 0x08
+#define LMI_CALLREF 0x00 /* Call Reference */
+#define LMI_ANSI_LOCKSHIFT 0x95 /* ANSI lockshift */
+#define LMI_REPTYPE 1 /* report type */
+#define LMI_CCITT_REPTYPE 0x51
+#define LMI_ALIVE 3 /* keep alive */
+#define LMI_CCITT_ALIVE 0x53
+#define LMI_PVCSTAT 7 /* pvc status */
+#define LMI_CCITT_PVCSTAT 0x57
+#define LMI_FULLREP 0 /* full report */
+#define LMI_INTEGRITY 1 /* link integrity report */
+#define LMI_SINGLE 2 /* single pvc report */
+#define LMI_STATUS_ENQUIRY 0x75
+#define LMI_STATUS 0x7D /* reply */
+
+#define LMI_REPT_LEN 1 /* report type element length */
+#define LMI_INTEG_LEN 2 /* link integrity element length */
+
+#define LMI_LENGTH 13 /* standard LMI frame length */
+#define LMI_ANSI_LENGTH 14
+
+
+typedef struct {
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+ unsigned ea1: 1;
+ unsigned cr: 1;
+ unsigned dlcih: 6;
+
+ unsigned ea2: 1;
+ unsigned de: 1;
+ unsigned becn: 1;
+ unsigned fecn: 1;
+ unsigned dlcil: 4;
+#else
+ unsigned dlcih: 6;
+ unsigned cr: 1;
+ unsigned ea1: 1;
+
+ unsigned dlcil: 4;
+ unsigned fecn: 1;
+ unsigned becn: 1;
+ unsigned de: 1;
+ unsigned ea2: 1;
+#endif
+}__attribute__ ((packed)) fr_hdr;
+
+
+static inline u16 q922_to_dlci(u8 *hdr)
+{
+ return ((hdr[0] & 0xFC) << 2) | ((hdr[1] & 0xF0) >> 4);
+}
+
+
+
+static inline void dlci_to_q922(u8 *hdr, u16 dlci)
+{
+ hdr[0] = (dlci >> 2) & 0xFC;
+ hdr[1] = ((dlci << 4) & 0xF0) | 0x01;
+}
+
+
+
+static inline pvc_device* find_pvc(hdlc_device *hdlc, u16 dlci)
+{
+ pvc_device *pvc = hdlc->state.fr.first_pvc;
+
+ while (pvc) {
+ if (pvc->dlci == dlci)
+ return pvc;
+ if (pvc->dlci > dlci)
+ return NULL; /* the listed is sorted */
+ pvc = pvc->next;
+ }
+
+ return NULL;
+}
+
+
+static inline pvc_device* add_pvc(struct net_device *dev, u16 dlci)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ pvc_device *pvc, **pvc_p = &hdlc->state.fr.first_pvc;
+
+ while (*pvc_p) {
+ if ((*pvc_p)->dlci == dlci)
+ return *pvc_p;
+ if ((*pvc_p)->dlci > dlci)
+ break; /* the list is sorted */
+ pvc_p = &(*pvc_p)->next;
+ }
+
+ pvc = kmalloc(sizeof(pvc_device), GFP_ATOMIC);
+ if (!pvc)
+ return NULL;
+
+ memset(pvc, 0, sizeof(pvc_device));
+ pvc->dlci = dlci;
+ pvc->master = dev;
+ pvc->next = *pvc_p; /* Put it in the chain */
+ *pvc_p = pvc;
+ return pvc;
+}
+
+
+static inline int pvc_is_used(pvc_device *pvc)
+{
+ return pvc->main != NULL || pvc->ether != NULL;
+}
+
+
+static inline void pvc_carrier(int on, pvc_device *pvc)
+{
+ if (on) {
+ if (pvc->main)
+ if (!netif_carrier_ok(pvc->main))
+ netif_carrier_on(pvc->main);
+ if (pvc->ether)
+ if (!netif_carrier_ok(pvc->ether))
+ netif_carrier_on(pvc->ether);
+ } else {
+ if (pvc->main)
+ if (netif_carrier_ok(pvc->main))
+ netif_carrier_off(pvc->main);
+ if (pvc->ether)
+ if (netif_carrier_ok(pvc->ether))
+ netif_carrier_off(pvc->ether);
+ }
+}
+
+
+static inline void delete_unused_pvcs(hdlc_device *hdlc)
+{
+ pvc_device **pvc_p = &hdlc->state.fr.first_pvc;
+
+ while (*pvc_p) {
+ if (!pvc_is_used(*pvc_p)) {
+ pvc_device *pvc = *pvc_p;
+ *pvc_p = pvc->next;
+ kfree(pvc);
+ continue;
+ }
+ pvc_p = &(*pvc_p)->next;
+ }
+}
+
+
+static inline struct net_device** get_dev_p(pvc_device *pvc, int type)
+{
+ if (type == ARPHRD_ETHER)
+ return &pvc->ether;
+ else
+ return &pvc->main;
+}
+
+
+static inline u16 status_to_dlci(u8 *status, int *active, int *new)
+{
+ *new = (status[2] & 0x08) ? 1 : 0;
+ *active = (status[2] & 0x02) ? 1 : 0;
+
+ return ((status[0] & 0x3F) << 4) | ((status[1] & 0x78) >> 3);
+}
+
+
+static inline void dlci_to_status(u16 dlci, u8 *status, int active, int new)
+{
+ status[0] = (dlci >> 4) & 0x3F;
+ status[1] = ((dlci << 3) & 0x78) | 0x80;
+ status[2] = 0x80;
+
+ if (new)
+ status[2] |= 0x08;
+ else if (active)
+ status[2] |= 0x02;
+}
+
+
+
+static int fr_hard_header(struct sk_buff **skb_p, u16 dlci)
+{
+ u16 head_len;
+ struct sk_buff *skb = *skb_p;
+
+ switch (skb->protocol) {
+ case __constant_ntohs(ETH_P_IP):
+ head_len = 4;
+ skb_push(skb, head_len);
+ skb->data[3] = NLPID_IP;
+ break;
+
+ case __constant_ntohs(ETH_P_IPV6):
+ head_len = 4;
+ skb_push(skb, head_len);
+ skb->data[3] = NLPID_IPV6;
+ break;
+
+ case __constant_ntohs(LMI_PROTO):
+ head_len = 4;
+ skb_push(skb, head_len);
+ skb->data[3] = LMI_PROTO;
+ break;
+
+ case __constant_ntohs(ETH_P_802_3):
+ head_len = 10;
+ if (skb_headroom(skb) < head_len) {
+ struct sk_buff *skb2 = skb_realloc_headroom(skb,
+ head_len);
+ if (!skb2)
+ return -ENOBUFS;
+ dev_kfree_skb(skb);
+ skb = *skb_p = skb2;
+ }
+ skb_push(skb, head_len);
+ skb->data[3] = FR_PAD;
+ skb->data[4] = NLPID_SNAP;
+ skb->data[5] = FR_PAD;
+ skb->data[6] = 0x80;
+ skb->data[7] = 0xC2;
+ skb->data[8] = 0x00;
+ skb->data[9] = 0x07; /* bridged Ethernet frame w/out FCS */
+ break;
+
+ default:
+ head_len = 10;
+ skb_push(skb, head_len);
+ skb->data[3] = FR_PAD;
+ skb->data[4] = NLPID_SNAP;
+ skb->data[5] = FR_PAD;
+ skb->data[6] = FR_PAD;
+ skb->data[7] = FR_PAD;
+ *(u16*)(skb->data + 8) = skb->protocol;
+ }
+
+ dlci_to_q922(skb->data, dlci);
+ skb->data[2] = FR_UI;
+ return 0;
+}
+
+
+
+static int pvc_open(struct net_device *dev)
+{
+ pvc_device *pvc = dev_to_pvc(dev);
+
+ if ((pvc->master->flags & IFF_UP) == 0)
+ return -EIO; /* Master must be UP in order to activate PVC */
+
+ if (pvc->open_count++ == 0) {
+ hdlc_device *hdlc = dev_to_hdlc(pvc->master);
+ if (hdlc->state.fr.settings.lmi == LMI_NONE)
+ pvc->state.active = hdlc->carrier;
+
+ pvc_carrier(pvc->state.active, pvc);
+ hdlc->state.fr.dce_changed = 1;
+ }
+ return 0;
+}
+
+
+
+static int pvc_close(struct net_device *dev)
+{
+ pvc_device *pvc = dev_to_pvc(dev);
+
+ if (--pvc->open_count == 0) {
+ hdlc_device *hdlc = dev_to_hdlc(pvc->master);
+ if (hdlc->state.fr.settings.lmi == LMI_NONE)
+ pvc->state.active = 0;
+
+ if (hdlc->state.fr.settings.dce) {
+ hdlc->state.fr.dce_changed = 1;
+ pvc->state.active = 0;
+ }
+ }
+ return 0;
+}
+
+
+
+int pvc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ pvc_device *pvc = dev_to_pvc(dev);
+ fr_proto_pvc_info info;
+
+ if (ifr->ifr_settings.type == IF_GET_PROTO) {
+ if (dev->type == ARPHRD_ETHER)
+ ifr->ifr_settings.type = IF_PROTO_FR_ETH_PVC;
+ else
+ ifr->ifr_settings.type = IF_PROTO_FR_PVC;
+
+ if (ifr->ifr_settings.size < sizeof(info)) {
+ /* data size wanted */
+ ifr->ifr_settings.size = sizeof(info);
+ return -ENOBUFS;
+ }
+
+ info.dlci = pvc->dlci;
+ memcpy(info.master, pvc->master->name, IFNAMSIZ);
+ if (copy_to_user(ifr->ifr_settings.ifs_ifsu.fr_pvc_info,
+ &info, sizeof(info)))
+ return -EFAULT;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+
+static inline struct net_device_stats *pvc_get_stats(struct net_device *dev)
+{
+ return netdev_priv(dev);
+}
+
+
+
+static int pvc_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ pvc_device *pvc = dev_to_pvc(dev);
+ struct net_device_stats *stats = pvc_get_stats(dev);
+
+ if (pvc->state.active) {
+ if (dev->type == ARPHRD_ETHER) {
+ int pad = ETH_ZLEN - skb->len;
+ if (pad > 0) { /* Pad the frame with zeros */
+ int len = skb->len;
+ if (skb_tailroom(skb) < pad)
+ if (pskb_expand_head(skb, 0, pad,
+ GFP_ATOMIC)) {
+ stats->tx_dropped++;
+ dev_kfree_skb(skb);
+ return 0;
+ }
+ skb_put(skb, pad);
+ memset(skb->data + len, 0, pad);
+ }
+ skb->protocol = __constant_htons(ETH_P_802_3);
+ }
+ if (!fr_hard_header(&skb, pvc->dlci)) {
+ stats->tx_bytes += skb->len;
+ stats->tx_packets++;
+ if (pvc->state.fecn) /* TX Congestion counter */
+ stats->tx_compressed++;
+ skb->dev = pvc->master;
+ dev_queue_xmit(skb);
+ return 0;
+ }
+ }
+
+ stats->tx_dropped++;
+ dev_kfree_skb(skb);
+ return 0;
+}
+
+
+
+static int pvc_change_mtu(struct net_device *dev, int new_mtu)
+{
+ if ((new_mtu < 68) || (new_mtu > HDLC_MAX_MTU))
+ return -EINVAL;
+ dev->mtu = new_mtu;
+ return 0;
+}
+
+
+
+static inline void fr_log_dlci_active(pvc_device *pvc)
+{
+ printk(KERN_INFO "%s: DLCI %d [%s%s%s]%s %s\n",
+ pvc->master->name,
+ pvc->dlci,
+ pvc->main ? pvc->main->name : "",
+ pvc->main && pvc->ether ? " " : "",
+ pvc->ether ? pvc->ether->name : "",
+ pvc->state.new ? " new" : "",
+ !pvc->state.exist ? "deleted" :
+ pvc->state.active ? "active" : "inactive");
+}
+
+
+
+static inline u8 fr_lmi_nextseq(u8 x)
+{
+ x++;
+ return x ? x : 1;
+}
+
+
+
+static void fr_lmi_send(struct net_device *dev, int fullrep)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ struct sk_buff *skb;
+ pvc_device *pvc = hdlc->state.fr.first_pvc;
+ int len = (hdlc->state.fr.settings.lmi == LMI_ANSI) ? LMI_ANSI_LENGTH
+ : LMI_LENGTH;
+ int stat_len = 3;
+ u8 *data;
+ int i = 0;
+
+ if (hdlc->state.fr.settings.dce && fullrep) {
+ len += hdlc->state.fr.dce_pvc_count * (2 + stat_len);
+ if (len > HDLC_MAX_MRU) {
+ printk(KERN_WARNING "%s: Too many PVCs while sending "
+ "LMI full report\n", dev->name);
+ return;
+ }
+ }
+
+ skb = dev_alloc_skb(len);
+ if (!skb) {
+ printk(KERN_WARNING "%s: Memory squeeze on fr_lmi_send()\n",
+ dev->name);
+ return;
+ }
+ memset(skb->data, 0, len);
+ skb_reserve(skb, 4);
+ skb->protocol = __constant_htons(LMI_PROTO);
+ fr_hard_header(&skb, LMI_DLCI);
+ data = skb->tail;
+ data[i++] = LMI_CALLREF;
+ data[i++] = hdlc->state.fr.settings.dce
+ ? LMI_STATUS : LMI_STATUS_ENQUIRY;
+ if (hdlc->state.fr.settings.lmi == LMI_ANSI)
+ data[i++] = LMI_ANSI_LOCKSHIFT;
+ data[i++] = (hdlc->state.fr.settings.lmi == LMI_CCITT)
+ ? LMI_CCITT_REPTYPE : LMI_REPTYPE;
+ data[i++] = LMI_REPT_LEN;
+ data[i++] = fullrep ? LMI_FULLREP : LMI_INTEGRITY;
+
+ data[i++] = (hdlc->state.fr.settings.lmi == LMI_CCITT)
+ ? LMI_CCITT_ALIVE : LMI_ALIVE;
+ data[i++] = LMI_INTEG_LEN;
+ data[i++] = hdlc->state.fr.txseq =fr_lmi_nextseq(hdlc->state.fr.txseq);
+ data[i++] = hdlc->state.fr.rxseq;
+
+ if (hdlc->state.fr.settings.dce && fullrep) {
+ while (pvc) {
+ data[i++] = (hdlc->state.fr.settings.lmi == LMI_CCITT)
+ ? LMI_CCITT_PVCSTAT : LMI_PVCSTAT;
+ data[i++] = stat_len;
+
+ /* LMI start/restart */
+ if (hdlc->state.fr.reliable && !pvc->state.exist) {
+ pvc->state.exist = pvc->state.new = 1;
+ fr_log_dlci_active(pvc);
+ }
+
+ /* ifconfig PVC up */
+ if (pvc->open_count && !pvc->state.active &&
+ pvc->state.exist && !pvc->state.new) {
+ pvc_carrier(1, pvc);
+ pvc->state.active = 1;
+ fr_log_dlci_active(pvc);
+ }
+
+ dlci_to_status(pvc->dlci, data + i,
+ pvc->state.active, pvc->state.new);
+ i += stat_len;
+ pvc = pvc->next;
+ }
+ }
+
+ skb_put(skb, i);
+ skb->priority = TC_PRIO_CONTROL;
+ skb->dev = dev;
+ skb->nh.raw = skb->data;
+
+ dev_queue_xmit(skb);
+}
+
+
+
+static void fr_set_link_state(int reliable, struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ pvc_device *pvc = hdlc->state.fr.first_pvc;
+
+ hdlc->state.fr.reliable = reliable;
+ if (reliable) {
+ if (!netif_carrier_ok(dev))
+ netif_carrier_on(dev);
+
+ hdlc->state.fr.n391cnt = 0; /* Request full status */
+ hdlc->state.fr.dce_changed = 1;
+
+ if (hdlc->state.fr.settings.lmi == LMI_NONE) {
+ while (pvc) { /* Activate all PVCs */
+ pvc_carrier(1, pvc);
+ pvc->state.exist = pvc->state.active = 1;
+ pvc->state.new = 0;
+ pvc = pvc->next;
+ }
+ }
+ } else {
+ if (netif_carrier_ok(dev))
+ netif_carrier_off(dev);
+
+ while (pvc) { /* Deactivate all PVCs */
+ pvc_carrier(0, pvc);
+ pvc->state.exist = pvc->state.active = 0;
+ pvc->state.new = 0;
+ pvc = pvc->next;
+ }
+ }
+}
+
+
+
+static void fr_timer(unsigned long arg)
+{
+ struct net_device *dev = (struct net_device *)arg;
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ int i, cnt = 0, reliable;
+ u32 list;
+
+ if (hdlc->state.fr.settings.dce)
+ reliable = hdlc->state.fr.request &&
+ time_before(jiffies, hdlc->state.fr.last_poll +
+ hdlc->state.fr.settings.t392 * HZ);
+ else {
+ hdlc->state.fr.last_errors <<= 1; /* Shift the list */
+ if (hdlc->state.fr.request) {
+ if (hdlc->state.fr.reliable)
+ printk(KERN_INFO "%s: No LMI status reply "
+ "received\n", dev->name);
+ hdlc->state.fr.last_errors |= 1;
+ }
+
+ list = hdlc->state.fr.last_errors;
+ for (i = 0; i < hdlc->state.fr.settings.n393; i++, list >>= 1)
+ cnt += (list & 1); /* errors count */
+
+ reliable = (cnt < hdlc->state.fr.settings.n392);
+ }
+
+ if (hdlc->state.fr.reliable != reliable) {
+ printk(KERN_INFO "%s: Link %sreliable\n", dev->name,
+ reliable ? "" : "un");
+ fr_set_link_state(reliable, dev);
+ }
+
+ if (hdlc->state.fr.settings.dce)
+ hdlc->state.fr.timer.expires = jiffies +
+ hdlc->state.fr.settings.t392 * HZ;
+ else {
+ if (hdlc->state.fr.n391cnt)
+ hdlc->state.fr.n391cnt--;
+
+ fr_lmi_send(dev, hdlc->state.fr.n391cnt == 0);
+
+ hdlc->state.fr.last_poll = jiffies;
+ hdlc->state.fr.request = 1;
+ hdlc->state.fr.timer.expires = jiffies +
+ hdlc->state.fr.settings.t391 * HZ;
+ }
+
+ hdlc->state.fr.timer.function = fr_timer;
+ hdlc->state.fr.timer.data = arg;
+ add_timer(&hdlc->state.fr.timer);
+}
+
+
+
+static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ int stat_len;
+ pvc_device *pvc;
+ int reptype = -1, error, no_ram;
+ u8 rxseq, txseq;
+ int i;
+
+ if (skb->len < ((hdlc->state.fr.settings.lmi == LMI_ANSI)
+ ? LMI_ANSI_LENGTH : LMI_LENGTH)) {
+ printk(KERN_INFO "%s: Short LMI frame\n", dev->name);
+ return 1;
+ }
+
+ if (skb->data[5] != (!hdlc->state.fr.settings.dce ?
+ LMI_STATUS : LMI_STATUS_ENQUIRY)) {
+ printk(KERN_INFO "%s: LMI msgtype=%x, Not LMI status %s\n",
+ dev->name, skb->data[2],
+ hdlc->state.fr.settings.dce ? "enquiry" : "reply");
+ return 1;
+ }
+
+ i = (hdlc->state.fr.settings.lmi == LMI_ANSI) ? 7 : 6;
+
+ if (skb->data[i] !=
+ ((hdlc->state.fr.settings.lmi == LMI_CCITT)
+ ? LMI_CCITT_REPTYPE : LMI_REPTYPE)) {
+ printk(KERN_INFO "%s: Not a report type=%x\n",
+ dev->name, skb->data[i]);
+ return 1;
+ }
+ i++;
+
+ i++; /* Skip length field */
+
+ reptype = skb->data[i++];
+
+ if (skb->data[i]!=
+ ((hdlc->state.fr.settings.lmi == LMI_CCITT)
+ ? LMI_CCITT_ALIVE : LMI_ALIVE)) {
+ printk(KERN_INFO "%s: Unsupported status element=%x\n",
+ dev->name, skb->data[i]);
+ return 1;
+ }
+ i++;
+
+ i++; /* Skip length field */
+
+ hdlc->state.fr.rxseq = skb->data[i++]; /* TX sequence from peer */
+ rxseq = skb->data[i++]; /* Should confirm our sequence */
+
+ txseq = hdlc->state.fr.txseq;
+
+ if (hdlc->state.fr.settings.dce) {
+ if (reptype != LMI_FULLREP && reptype != LMI_INTEGRITY) {
+ printk(KERN_INFO "%s: Unsupported report type=%x\n",
+ dev->name, reptype);
+ return 1;
+ }
+ hdlc->state.fr.last_poll = jiffies;
+ }
+
+ error = 0;
+ if (!hdlc->state.fr.reliable)
+ error = 1;
+
+ if (rxseq == 0 || rxseq != txseq) {
+ hdlc->state.fr.n391cnt = 0; /* Ask for full report next time */
+ error = 1;
+ }
+
+ if (hdlc->state.fr.settings.dce) {
+ if (hdlc->state.fr.fullrep_sent && !error) {
+/* Stop sending full report - the last one has been confirmed by DTE */
+ hdlc->state.fr.fullrep_sent = 0;
+ pvc = hdlc->state.fr.first_pvc;
+ while (pvc) {
+ if (pvc->state.new) {
+ pvc->state.new = 0;
+
+/* Tell DTE that new PVC is now active */
+ hdlc->state.fr.dce_changed = 1;
+ }
+ pvc = pvc->next;
+ }
+ }
+
+ if (hdlc->state.fr.dce_changed) {
+ reptype = LMI_FULLREP;
+ hdlc->state.fr.fullrep_sent = 1;
+ hdlc->state.fr.dce_changed = 0;
+ }
+
+ fr_lmi_send(dev, reptype == LMI_FULLREP ? 1 : 0);
+ return 0;
+ }
+
+ /* DTE */
+
+ hdlc->state.fr.request = 0; /* got response, no request pending */
+
+ if (error)
+ return 0;
+
+ if (reptype != LMI_FULLREP)
+ return 0;
+
+ stat_len = 3;
+ pvc = hdlc->state.fr.first_pvc;
+
+ while (pvc) {
+ pvc->state.deleted = 1;
+ pvc = pvc->next;
+ }
+
+ no_ram = 0;
+ while (skb->len >= i + 2 + stat_len) {
+ u16 dlci;
+ unsigned int active, new;
+
+ if (skb->data[i] != ((hdlc->state.fr.settings.lmi == LMI_CCITT)
+ ? LMI_CCITT_PVCSTAT : LMI_PVCSTAT)) {
+ printk(KERN_WARNING "%s: Invalid PVCSTAT ID: %x\n",
+ dev->name, skb->data[i]);
+ return 1;
+ }
+ i++;
+
+ if (skb->data[i] != stat_len) {
+ printk(KERN_WARNING "%s: Invalid PVCSTAT length: %x\n",
+ dev->name, skb->data[i]);
+ return 1;
+ }
+ i++;
+
+ dlci = status_to_dlci(skb->data + i, &active, &new);
+
+ pvc = add_pvc(dev, dlci);
+
+ if (!pvc && !no_ram) {
+ printk(KERN_WARNING
+ "%s: Memory squeeze on fr_lmi_recv()\n",
+ dev->name);
+ no_ram = 1;
+ }
+
+ if (pvc) {
+ pvc->state.exist = 1;
+ pvc->state.deleted = 0;
+ if (active != pvc->state.active ||
+ new != pvc->state.new ||
+ !pvc->state.exist) {
+ pvc->state.new = new;
+ pvc->state.active = active;
+ pvc_carrier(active, pvc);
+ fr_log_dlci_active(pvc);
+ }
+ }
+
+ i += stat_len;
+ }
+
+ pvc = hdlc->state.fr.first_pvc;
+
+ while (pvc) {
+ if (pvc->state.deleted && pvc->state.exist) {
+ pvc_carrier(0, pvc);
+ pvc->state.active = pvc->state.new = 0;
+ pvc->state.exist = 0;
+ fr_log_dlci_active(pvc);
+ }
+ pvc = pvc->next;
+ }
+
+ /* Next full report after N391 polls */
+ hdlc->state.fr.n391cnt = hdlc->state.fr.settings.n391;
+
+ return 0;
+}
+
+
+
+static int fr_rx(struct sk_buff *skb)
+{
+ struct net_device *ndev = skb->dev;
+ hdlc_device *hdlc = dev_to_hdlc(ndev);
+ fr_hdr *fh = (fr_hdr*)skb->data;
+ u8 *data = skb->data;
+ u16 dlci;
+ pvc_device *pvc;
+ struct net_device *dev = NULL;
+
+ if (skb->len <= 4 || fh->ea1 || data[2] != FR_UI)
+ goto rx_error;
+
+ dlci = q922_to_dlci(skb->data);
+
+ if (dlci == LMI_DLCI) {
+ if (hdlc->state.fr.settings.lmi == LMI_NONE)
+ goto rx_error; /* LMI packet with no LMI? */
+
+ if (data[3] == LMI_PROTO) {
+ if (fr_lmi_recv(ndev, skb))
+ goto rx_error;
+ else {
+ dev_kfree_skb_any(skb);
+ return NET_RX_SUCCESS;
+ }
+ }
+
+ printk(KERN_INFO "%s: Received non-LMI frame with LMI DLCI\n",
+ ndev->name);
+ goto rx_error;
+ }
+
+ pvc = find_pvc(hdlc, dlci);
+ if (!pvc) {
+#ifdef DEBUG_PKT
+ printk(KERN_INFO "%s: No PVC for received frame's DLCI %d\n",
+ ndev->name, dlci);
+#endif
+ dev_kfree_skb_any(skb);
+ return NET_RX_DROP;
+ }
+
+ if (pvc->state.fecn != fh->fecn) {
+#ifdef DEBUG_ECN
+ printk(KERN_DEBUG "%s: DLCI %d FECN O%s\n", ndev->name,
+ dlci, fh->fecn ? "N" : "FF");
+#endif
+ pvc->state.fecn ^= 1;
+ }
+
+ if (pvc->state.becn != fh->becn) {
+#ifdef DEBUG_ECN
+ printk(KERN_DEBUG "%s: DLCI %d BECN O%s\n", ndev->name,
+ dlci, fh->becn ? "N" : "FF");
+#endif
+ pvc->state.becn ^= 1;
+ }
+
+
+ if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL) {
+ hdlc->stats.rx_dropped++;
+ return NET_RX_DROP;
+ }
+
+ if (data[3] == NLPID_IP) {
+ skb_pull(skb, 4); /* Remove 4-byte header (hdr, UI, NLPID) */
+ dev = pvc->main;
+ skb->protocol = htons(ETH_P_IP);
+
+ } else if (data[3] == NLPID_IPV6) {
+ skb_pull(skb, 4); /* Remove 4-byte header (hdr, UI, NLPID) */
+ dev = pvc->main;
+ skb->protocol = htons(ETH_P_IPV6);
+
+ } else if (skb->len > 10 && data[3] == FR_PAD &&
+ data[4] == NLPID_SNAP && data[5] == FR_PAD) {
+ u16 oui = ntohs(*(u16*)(data + 6));
+ u16 pid = ntohs(*(u16*)(data + 8));
+ skb_pull(skb, 10);
+
+ switch ((((u32)oui) << 16) | pid) {
+ case ETH_P_ARP: /* routed frame with SNAP */
+ case ETH_P_IPX:
+ case ETH_P_IP: /* a long variant */
+ case ETH_P_IPV6:
+ dev = pvc->main;
+ skb->protocol = htons(pid);
+ break;
+
+ case 0x80C20007: /* bridged Ethernet frame */
+ if ((dev = pvc->ether) != NULL)
+ skb->protocol = eth_type_trans(skb, dev);
+ break;
+
+ default:
+ printk(KERN_INFO "%s: Unsupported protocol, OUI=%x "
+ "PID=%x\n", ndev->name, oui, pid);
+ dev_kfree_skb_any(skb);
+ return NET_RX_DROP;
+ }
+ } else {
+ printk(KERN_INFO "%s: Unsupported protocol, NLPID=%x "
+ "length = %i\n", ndev->name, data[3], skb->len);
+ dev_kfree_skb_any(skb);
+ return NET_RX_DROP;
+ }
+
+ if (dev) {
+ struct net_device_stats *stats = pvc_get_stats(dev);
+ stats->rx_packets++; /* PVC traffic */
+ stats->rx_bytes += skb->len;
+ if (pvc->state.becn)
+ stats->rx_compressed++;
+ skb->dev = dev;
+ netif_rx(skb);
+ return NET_RX_SUCCESS;
+ } else {
+ dev_kfree_skb_any(skb);
+ return NET_RX_DROP;
+ }
+
+ rx_error:
+ hdlc->stats.rx_errors++; /* Mark error */
+ dev_kfree_skb_any(skb);
+ return NET_RX_DROP;
+}
+
+
+
+static void fr_start(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+#ifdef DEBUG_LINK
+ printk(KERN_DEBUG "fr_start\n");
+#endif
+ if (hdlc->state.fr.settings.lmi != LMI_NONE) {
+ hdlc->state.fr.reliable = 0;
+ hdlc->state.fr.dce_changed = 1;
+ hdlc->state.fr.request = 0;
+ hdlc->state.fr.fullrep_sent = 0;
+ hdlc->state.fr.last_errors = 0xFFFFFFFF;
+ hdlc->state.fr.n391cnt = 0;
+ hdlc->state.fr.txseq = hdlc->state.fr.rxseq = 0;
+
+ init_timer(&hdlc->state.fr.timer);
+ /* First poll after 1 s */
+ hdlc->state.fr.timer.expires = jiffies + HZ;
+ hdlc->state.fr.timer.function = fr_timer;
+ hdlc->state.fr.timer.data = (unsigned long)dev;
+ add_timer(&hdlc->state.fr.timer);
+ } else
+ fr_set_link_state(1, dev);
+}
+
+
+
+static void fr_stop(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+#ifdef DEBUG_LINK
+ printk(KERN_DEBUG "fr_stop\n");
+#endif
+ if (hdlc->state.fr.settings.lmi != LMI_NONE)
+ del_timer_sync(&hdlc->state.fr.timer);
+ fr_set_link_state(0, dev);
+}
+
+
+
+static void fr_close(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ pvc_device *pvc = hdlc->state.fr.first_pvc;
+
+ while (pvc) { /* Shutdown all PVCs for this FRAD */
+ if (pvc->main)
+ dev_close(pvc->main);
+ if (pvc->ether)
+ dev_close(pvc->ether);
+ pvc = pvc->next;
+ }
+}
+
+static void dlci_setup(struct net_device *dev)
+{
+ dev->type = ARPHRD_DLCI;
+ dev->flags = IFF_POINTOPOINT;
+ dev->hard_header_len = 10;
+ dev->addr_len = 2;
+}
+
+static int fr_add_pvc(struct net_device *master, unsigned int dlci, int type)
+{
+ hdlc_device *hdlc = dev_to_hdlc(master);
+ pvc_device *pvc = NULL;
+ struct net_device *dev;
+ int result, used;
+ char * prefix = "pvc%d";
+
+ if (type == ARPHRD_ETHER)
+ prefix = "pvceth%d";
+
+ if ((pvc = add_pvc(master, dlci)) == NULL) {
+ printk(KERN_WARNING "%s: Memory squeeze on fr_add_pvc()\n",
+ master->name);
+ return -ENOBUFS;
+ }
+
+ if (*get_dev_p(pvc, type))
+ return -EEXIST;
+
+ used = pvc_is_used(pvc);
+
+ if (type == ARPHRD_ETHER)
+ dev = alloc_netdev(sizeof(struct net_device_stats),
+ "pvceth%d", ether_setup);
+ else
+ dev = alloc_netdev(sizeof(struct net_device_stats),
+ "pvc%d", dlci_setup);
+
+ if (!dev) {
+ printk(KERN_WARNING "%s: Memory squeeze on fr_pvc()\n",
+ master->name);
+ delete_unused_pvcs(hdlc);
+ return -ENOBUFS;
+ }
+
+ if (type == ARPHRD_ETHER) {
+ memcpy(dev->dev_addr, "\x00\x01", 2);
+ get_random_bytes(dev->dev_addr + 2, ETH_ALEN - 2);
+ } else {
+ *(u16*)dev->dev_addr = htons(dlci);
+ dlci_to_q922(dev->broadcast, dlci);
+ }
+ dev->hard_start_xmit = pvc_xmit;
+ dev->get_stats = pvc_get_stats;
+ dev->open = pvc_open;
+ dev->stop = pvc_close;
+ dev->do_ioctl = pvc_ioctl;
+ dev->change_mtu = pvc_change_mtu;
+ dev->mtu = HDLC_MAX_MTU;
+ dev->tx_queue_len = 0;
+ dev->priv = pvc;
+
+ result = dev_alloc_name(dev, dev->name);
+ if (result < 0) {
+ free_netdev(dev);
+ delete_unused_pvcs(hdlc);
+ return result;
+ }
+
+ if (register_netdevice(dev) != 0) {
+ free_netdev(dev);
+ delete_unused_pvcs(hdlc);
+ return -EIO;
+ }
+
+ dev->destructor = free_netdev;
+ *get_dev_p(pvc, type) = dev;
+ if (!used) {
+ hdlc->state.fr.dce_changed = 1;
+ hdlc->state.fr.dce_pvc_count++;
+ }
+ return 0;
+}
+
+
+
+static int fr_del_pvc(hdlc_device *hdlc, unsigned int dlci, int type)
+{
+ pvc_device *pvc;
+ struct net_device *dev;
+
+ if ((pvc = find_pvc(hdlc, dlci)) == NULL)
+ return -ENOENT;
+
+ if ((dev = *get_dev_p(pvc, type)) == NULL)
+ return -ENOENT;
+
+ if (dev->flags & IFF_UP)
+ return -EBUSY; /* PVC in use */
+
+ unregister_netdevice(dev); /* the destructor will free_netdev(dev) */
+ *get_dev_p(pvc, type) = NULL;
+
+ if (!pvc_is_used(pvc)) {
+ hdlc->state.fr.dce_pvc_count--;
+ hdlc->state.fr.dce_changed = 1;
+ }
+ delete_unused_pvcs(hdlc);
+ return 0;
+}
+
+
+
+static void fr_destroy(hdlc_device *hdlc)
+{
+ pvc_device *pvc;
+
+ pvc = hdlc->state.fr.first_pvc;
+ hdlc->state.fr.first_pvc = NULL; /* All PVCs destroyed */
+ hdlc->state.fr.dce_pvc_count = 0;
+ hdlc->state.fr.dce_changed = 1;
+
+ while (pvc) {
+ pvc_device *next = pvc->next;
+ /* destructors will free_netdev() main and ether */
+ if (pvc->main)
+ unregister_netdevice(pvc->main);
+
+ if (pvc->ether)
+ unregister_netdevice(pvc->ether);
+
+ kfree(pvc);
+ pvc = next;
+ }
+}
+
+
+
+int hdlc_fr_ioctl(struct net_device *dev, struct ifreq *ifr)
+{
+ fr_proto __user *fr_s = ifr->ifr_settings.ifs_ifsu.fr;
+ const size_t size = sizeof(fr_proto);
+ fr_proto new_settings;
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ fr_proto_pvc pvc;
+ int result;
+
+ switch (ifr->ifr_settings.type) {
+ case IF_GET_PROTO:
+ ifr->ifr_settings.type = IF_PROTO_FR;
+ if (ifr->ifr_settings.size < size) {
+ ifr->ifr_settings.size = size; /* data size wanted */
+ return -ENOBUFS;
+ }
+ if (copy_to_user(fr_s, &hdlc->state.fr.settings, size))
+ return -EFAULT;
+ return 0;
+
+ case IF_PROTO_FR:
+ if(!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ if(dev->flags & IFF_UP)
+ return -EBUSY;
+
+ if (copy_from_user(&new_settings, fr_s, size))
+ return -EFAULT;
+
+ if (new_settings.lmi == LMI_DEFAULT)
+ new_settings.lmi = LMI_ANSI;
+
+ if ((new_settings.lmi != LMI_NONE &&
+ new_settings.lmi != LMI_ANSI &&
+ new_settings.lmi != LMI_CCITT) ||
+ new_settings.t391 < 1 ||
+ new_settings.t392 < 2 ||
+ new_settings.n391 < 1 ||
+ new_settings.n392 < 1 ||
+ new_settings.n393 < new_settings.n392 ||
+ new_settings.n393 > 32 ||
+ (new_settings.dce != 0 &&
+ new_settings.dce != 1))
+ return -EINVAL;
+
+ result=hdlc->attach(dev, ENCODING_NRZ,PARITY_CRC16_PR1_CCITT);
+ if (result)
+ return result;
+
+ if (hdlc->proto.id != IF_PROTO_FR) {
+ hdlc_proto_detach(hdlc);
+ hdlc->state.fr.first_pvc = NULL;
+ hdlc->state.fr.dce_pvc_count = 0;
+ }
+ memcpy(&hdlc->state.fr.settings, &new_settings, size);
+ memset(&hdlc->proto, 0, sizeof(hdlc->proto));
+
+ hdlc->proto.close = fr_close;
+ hdlc->proto.start = fr_start;
+ hdlc->proto.stop = fr_stop;
+ hdlc->proto.detach = fr_destroy;
+ hdlc->proto.netif_rx = fr_rx;
+ hdlc->proto.id = IF_PROTO_FR;
+ dev->hard_start_xmit = hdlc->xmit;
+ dev->hard_header = NULL;
+ dev->type = ARPHRD_FRAD;
+ dev->flags = IFF_POINTOPOINT | IFF_NOARP;
+ dev->addr_len = 0;
+ return 0;
+
+ case IF_PROTO_FR_ADD_PVC:
+ case IF_PROTO_FR_DEL_PVC:
+ case IF_PROTO_FR_ADD_ETH_PVC:
+ case IF_PROTO_FR_DEL_ETH_PVC:
+ if(!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ if (copy_from_user(&pvc, ifr->ifr_settings.ifs_ifsu.fr_pvc,
+ sizeof(fr_proto_pvc)))
+ return -EFAULT;
+
+ if (pvc.dlci <= 0 || pvc.dlci >= 1024)
+ return -EINVAL; /* Only 10 bits, DLCI 0 reserved */
+
+ if (ifr->ifr_settings.type == IF_PROTO_FR_ADD_ETH_PVC ||
+ ifr->ifr_settings.type == IF_PROTO_FR_DEL_ETH_PVC)
+ result = ARPHRD_ETHER; /* bridged Ethernet device */
+ else
+ result = ARPHRD_DLCI;
+
+ if (ifr->ifr_settings.type == IF_PROTO_FR_ADD_PVC ||
+ ifr->ifr_settings.type == IF_PROTO_FR_ADD_ETH_PVC)
+ return fr_add_pvc(dev, pvc.dlci, result);
+ else
+ return fr_del_pvc(hdlc, pvc.dlci, result);
+ }
+
+ return -EINVAL;
+}
diff --git a/drivers/net/wan/hdlc_generic.c b/drivers/net/wan/hdlc_generic.c
new file mode 100644
index 000000000000..6ed064cb4469
--- /dev/null
+++ b/drivers/net/wan/hdlc_generic.c
@@ -0,0 +1,343 @@
+/*
+ * Generic HDLC support routines for Linux
+ *
+ * Copyright (C) 1999 - 2003 Krzysztof Halasa
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * Currently supported:
+ * * raw IP-in-HDLC
+ * * Cisco HDLC
+ * * Frame Relay with ANSI or CCITT LMI (both user and network side)
+ * * PPP
+ * * X.25
+ *
+ * Use sethdlc utility to set line parameters, protocol and PVCs
+ *
+ * How does it work:
+ * - proto.open(), close(), start(), stop() calls are serialized.
+ * The order is: open, [ start, stop ... ] close ...
+ * - proto.start() and stop() are called with spin_lock_irq held.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+static const char* version = "HDLC support module revision 1.17";
+
+#undef DEBUG_LINK
+
+
+static int hdlc_change_mtu(struct net_device *dev, int new_mtu)
+{
+ if ((new_mtu < 68) || (new_mtu > HDLC_MAX_MTU))
+ return -EINVAL;
+ dev->mtu = new_mtu;
+ return 0;
+}
+
+
+
+static struct net_device_stats *hdlc_get_stats(struct net_device *dev)
+{
+ return hdlc_stats(dev);
+}
+
+
+
+static int hdlc_rcv(struct sk_buff *skb, struct net_device *dev,
+ struct packet_type *p)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ if (hdlc->proto.netif_rx)
+ return hdlc->proto.netif_rx(skb);
+
+ hdlc->stats.rx_dropped++; /* Shouldn't happen */
+ dev_kfree_skb(skb);
+ return NET_RX_DROP;
+}
+
+
+
+static void __hdlc_set_carrier_on(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ if (hdlc->proto.start)
+ return hdlc->proto.start(dev);
+#ifdef DEBUG_LINK
+ if (netif_carrier_ok(dev))
+ printk(KERN_ERR "hdlc_set_carrier_on(): already on\n");
+#endif
+ netif_carrier_on(dev);
+}
+
+
+
+static void __hdlc_set_carrier_off(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ if (hdlc->proto.stop)
+ return hdlc->proto.stop(dev);
+
+#ifdef DEBUG_LINK
+ if (!netif_carrier_ok(dev))
+ printk(KERN_ERR "hdlc_set_carrier_off(): already off\n");
+#endif
+ netif_carrier_off(dev);
+}
+
+
+
+void hdlc_set_carrier(int on, struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ unsigned long flags;
+ on = on ? 1 : 0;
+
+#ifdef DEBUG_LINK
+ printk(KERN_DEBUG "hdlc_set_carrier %i\n", on);
+#endif
+
+ spin_lock_irqsave(&hdlc->state_lock, flags);
+
+ if (hdlc->carrier == on)
+ goto carrier_exit; /* no change in DCD line level */
+
+#ifdef DEBUG_LINK
+ printk(KERN_INFO "%s: carrier %s\n", dev->name, on ? "ON" : "off");
+#endif
+ hdlc->carrier = on;
+
+ if (!hdlc->open)
+ goto carrier_exit;
+
+ if (hdlc->carrier)
+ __hdlc_set_carrier_on(dev);
+ else
+ __hdlc_set_carrier_off(dev);
+
+carrier_exit:
+ spin_unlock_irqrestore(&hdlc->state_lock, flags);
+}
+
+
+
+/* Must be called by hardware driver when HDLC device is being opened */
+int hdlc_open(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+#ifdef DEBUG_LINK
+ printk(KERN_DEBUG "hdlc_open() carrier %i open %i\n",
+ hdlc->carrier, hdlc->open);
+#endif
+
+ if (hdlc->proto.id == -1)
+ return -ENOSYS; /* no protocol attached */
+
+ if (hdlc->proto.open) {
+ int result = hdlc->proto.open(dev);
+ if (result)
+ return result;
+ }
+
+ spin_lock_irq(&hdlc->state_lock);
+
+ if (hdlc->carrier)
+ __hdlc_set_carrier_on(dev);
+
+ hdlc->open = 1;
+
+ spin_unlock_irq(&hdlc->state_lock);
+ return 0;
+}
+
+
+
+/* Must be called by hardware driver when HDLC device is being closed */
+void hdlc_close(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+#ifdef DEBUG_LINK
+ printk(KERN_DEBUG "hdlc_close() carrier %i open %i\n",
+ hdlc->carrier, hdlc->open);
+#endif
+
+ spin_lock_irq(&hdlc->state_lock);
+
+ hdlc->open = 0;
+ if (hdlc->carrier)
+ __hdlc_set_carrier_off(dev);
+
+ spin_unlock_irq(&hdlc->state_lock);
+
+ if (hdlc->proto.close)
+ hdlc->proto.close(dev);
+}
+
+
+
+#ifndef CONFIG_HDLC_RAW
+#define hdlc_raw_ioctl(dev, ifr) -ENOSYS
+#endif
+
+#ifndef CONFIG_HDLC_RAW_ETH
+#define hdlc_raw_eth_ioctl(dev, ifr) -ENOSYS
+#endif
+
+#ifndef CONFIG_HDLC_PPP
+#define hdlc_ppp_ioctl(dev, ifr) -ENOSYS
+#endif
+
+#ifndef CONFIG_HDLC_CISCO
+#define hdlc_cisco_ioctl(dev, ifr) -ENOSYS
+#endif
+
+#ifndef CONFIG_HDLC_FR
+#define hdlc_fr_ioctl(dev, ifr) -ENOSYS
+#endif
+
+#ifndef CONFIG_HDLC_X25
+#define hdlc_x25_ioctl(dev, ifr) -ENOSYS
+#endif
+
+
+int hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ unsigned int proto;
+
+ if (cmd != SIOCWANDEV)
+ return -EINVAL;
+
+ switch(ifr->ifr_settings.type) {
+ case IF_PROTO_HDLC:
+ case IF_PROTO_HDLC_ETH:
+ case IF_PROTO_PPP:
+ case IF_PROTO_CISCO:
+ case IF_PROTO_FR:
+ case IF_PROTO_X25:
+ proto = ifr->ifr_settings.type;
+ break;
+
+ default:
+ proto = hdlc->proto.id;
+ }
+
+ switch(proto) {
+ case IF_PROTO_HDLC: return hdlc_raw_ioctl(dev, ifr);
+ case IF_PROTO_HDLC_ETH: return hdlc_raw_eth_ioctl(dev, ifr);
+ case IF_PROTO_PPP: return hdlc_ppp_ioctl(dev, ifr);
+ case IF_PROTO_CISCO: return hdlc_cisco_ioctl(dev, ifr);
+ case IF_PROTO_FR: return hdlc_fr_ioctl(dev, ifr);
+ case IF_PROTO_X25: return hdlc_x25_ioctl(dev, ifr);
+ default: return -EINVAL;
+ }
+}
+
+static void hdlc_setup(struct net_device *dev)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+
+ dev->get_stats = hdlc_get_stats;
+ dev->change_mtu = hdlc_change_mtu;
+ dev->mtu = HDLC_MAX_MTU;
+
+ dev->type = ARPHRD_RAWHDLC;
+ dev->hard_header_len = 16;
+
+ dev->flags = IFF_POINTOPOINT | IFF_NOARP;
+
+ hdlc->proto.id = -1;
+ hdlc->proto.detach = NULL;
+ hdlc->carrier = 1;
+ hdlc->open = 0;
+ spin_lock_init(&hdlc->state_lock);
+}
+
+struct net_device *alloc_hdlcdev(void *priv)
+{
+ struct net_device *dev;
+ dev = alloc_netdev(sizeof(hdlc_device), "hdlc%d", hdlc_setup);
+ if (dev)
+ dev_to_hdlc(dev)->priv = priv;
+ return dev;
+}
+
+int register_hdlc_device(struct net_device *dev)
+{
+ int result = dev_alloc_name(dev, "hdlc%d");
+ if (result < 0)
+ return result;
+
+ result = register_netdev(dev);
+ if (result != 0)
+ return -EIO;
+
+ if (netif_carrier_ok(dev))
+ netif_carrier_off(dev); /* no carrier until DCD goes up */
+
+ return 0;
+}
+
+
+
+void unregister_hdlc_device(struct net_device *dev)
+{
+ rtnl_lock();
+ hdlc_proto_detach(dev_to_hdlc(dev));
+ unregister_netdevice(dev);
+ rtnl_unlock();
+}
+
+
+
+MODULE_AUTHOR("Krzysztof Halasa ");
+MODULE_DESCRIPTION("HDLC support module");
+MODULE_LICENSE("GPL v2");
+
+EXPORT_SYMBOL(hdlc_open);
+EXPORT_SYMBOL(hdlc_close);
+EXPORT_SYMBOL(hdlc_set_carrier);
+EXPORT_SYMBOL(hdlc_ioctl);
+EXPORT_SYMBOL(alloc_hdlcdev);
+EXPORT_SYMBOL(register_hdlc_device);
+EXPORT_SYMBOL(unregister_hdlc_device);
+
+static struct packet_type hdlc_packet_type = {
+ .type = __constant_htons(ETH_P_HDLC),
+ .func = hdlc_rcv,
+};
+
+
+static int __init hdlc_module_init(void)
+{
+ printk(KERN_INFO "%s\n", version);
+ dev_add_pack(&hdlc_packet_type);
+ return 0;
+}
+
+
+
+static void __exit hdlc_module_exit(void)
+{
+ dev_remove_pack(&hdlc_packet_type);
+}
+
+
+module_init(hdlc_module_init);
+module_exit(hdlc_module_exit);
diff --git a/drivers/net/wan/hdlc_ppp.c b/drivers/net/wan/hdlc_ppp.c
new file mode 100644
index 000000000000..7cd6195a2e46
--- /dev/null
+++ b/drivers/net/wan/hdlc_ppp.c
@@ -0,0 +1,115 @@
+/*
+ * Generic HDLC support routines for Linux
+ * Point-to-point protocol support
+ *
+ * Copyright (C) 1999 - 2003 Krzysztof Halasa
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include