From 7507445b1993087d2a6ef3e30e3eaeb2da40dbc8 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Sat, 21 Sep 2019 21:50:27 +0800 Subject: MIPS: Loongson: Add Loongson-3A R4 basic support All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang Cc: Zhangjin Wu Cc: Huacai Chen --- drivers/platform/mips/cpu_hwmon.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/platform/mips') diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c index a7f184bb47e0..1833b51690e5 100644 --- a/drivers/platform/mips/cpu_hwmon.c +++ b/drivers/platform/mips/cpu_hwmon.c @@ -9,6 +9,9 @@ #include #include #include +#include + +static int csr_temp_enable = 0; /* * Loongson-3 series cpu has two sensors inside, @@ -20,8 +23,14 @@ int loongson3_cpu_temp(int cpu) { u32 reg, prid_rev; + if (csr_temp_enable) { + reg = (csr_readl(LOONGSON_CSR_CPUTEMP) & 0xff); + goto out; + } + reg = LOONGSON_CHIPTEMP(cpu); prid_rev = read_c0_prid() & PRID_REV_MASK; + switch (prid_rev) { case PRID_REV_LOONGSON3A_R1: reg = (reg >> 8) & 0xff; @@ -34,9 +43,12 @@ int loongson3_cpu_temp(int cpu) break; case PRID_REV_LOONGSON3A_R3_0: case PRID_REV_LOONGSON3A_R3_1: + default: reg = (reg & 0xffff)*731/0x4000 - 273; break; } + +out: return (int)reg * 1000; } @@ -159,6 +171,9 @@ static int __init loongson_hwmon_init(void) pr_info("Loongson Hwmon Enter...\n"); + if (cpu_has_csr()) + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; + cpu_hwmon_dev = hwmon_device_register(NULL); if (IS_ERR(cpu_hwmon_dev)) { ret = -ENOMEM; -- cgit v1.2.3