From 5e7d4c65294174d6f58fe36df3edd55cd3b859d6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:11:57 +0100 Subject: soc/tegra: Implement Tegra186 PMC support The power management controller on Tegra186 has changed in backwards- incompatible ways with respect to earlier generations. This implements a new driver that supports inversion of the PMU interrupt as well as the "recovery", "bootloader" and "forced-recovery" reboot commands. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- drivers/soc/tegra/Kconfig | 13 +++ drivers/soc/tegra/Makefile | 3 +- drivers/soc/tegra/pmc-tegra186.c | 169 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 184 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/tegra/pmc-tegra186.c (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index e5e124c07066..208d6edb3fdb 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -12,6 +12,7 @@ config ARCH_TEGRA_2x_SOC select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_PMC select TEGRA_TIMER help Support for NVIDIA Tegra AP20 and T20 processors, based on the @@ -23,6 +24,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_764369 if SMP select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_PMC select TEGRA_TIMER help Support for NVIDIA Tegra T30 processor family, based on the @@ -33,6 +35,7 @@ config ARCH_TEGRA_114_SOC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 + select SOC_TEGRA_PMC select TEGRA_TIMER help Support for NVIDIA Tegra T114 processor family, based on the @@ -42,6 +45,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 + select SOC_TEGRA_PMC select TEGRA_TIMER help Support for NVIDIA Tegra T124 processor family, based on the @@ -55,6 +59,7 @@ if ARM64 config ARCH_TEGRA_132_SOC bool "NVIDIA Tegra132 SoC" select PINCTRL_TEGRA124 + select SOC_TEGRA_PMC help Enable support for NVIDIA Tegra132 SoC, based on the Denver ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, @@ -64,6 +69,7 @@ config ARCH_TEGRA_132_SOC config ARCH_TEGRA_210_SOC bool "NVIDIA Tegra210 SoC" select PINCTRL_TEGRA210 + select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 @@ -83,6 +89,7 @@ config ARCH_TEGRA_186_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_PMC_TEGRA186 help Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a combination of Denver and Cortex-A57 CPU cores and a GPU based on @@ -93,3 +100,9 @@ config ARCH_TEGRA_186_SOC endif endif + +config SOC_TEGRA_PMC + bool + +config SOC_TEGRA_PMC_TEGRA186 + bool diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile index ae857ff7d53d..b4425e4319ff 100644 --- a/drivers/soc/tegra/Makefile +++ b/drivers/soc/tegra/Makefile @@ -1,4 +1,5 @@ obj-y += fuse/ obj-y += common.o -obj-y += pmc.o +obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o +obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o diff --git a/drivers/soc/tegra/pmc-tegra186.c b/drivers/soc/tegra/pmc-tegra186.c new file mode 100644 index 000000000000..6f5c6f98ba92 --- /dev/null +++ b/drivers/soc/tegra/pmc-tegra186.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define pr_fmt(fmt) "tegra-pmc: " fmt + +#include +#include +#include +#include +#include + +#include + +#define PMC_CNTRL 0x000 +#define PMC_CNTRL_MAIN_RST BIT(4) + +#define PMC_RST_STATUS 0x070 + +#define WAKE_AOWAKE_CTRL 0x4f4 +#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) + +#define SCRATCH_SCRATCH0 0x2000 +#define SCRATCH_SCRATCH0_MODE_RECOVERY BIT(31) +#define SCRATCH_SCRATCH0_MODE_BOOTLOADER BIT(30) +#define SCRATCH_SCRATCH0_MODE_RCM BIT(1) +#define SCRATCH_SCRATCH0_MODE_MASK (SCRATCH_SCRATCH0_MODE_RECOVERY | \ + SCRATCH_SCRATCH0_MODE_BOOTLOADER | \ + SCRATCH_SCRATCH0_MODE_RCM) + +struct tegra_pmc { + struct device *dev; + void __iomem *regs; + void __iomem *wake; + void __iomem *aotag; + void __iomem *scratch; + + void (*system_restart)(enum reboot_mode mode, const char *cmd); + struct notifier_block restart; +}; + +static int tegra186_pmc_restart_notify(struct notifier_block *nb, + unsigned long action, + void *data) +{ + struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, restart); + const char *cmd = data; + u32 value; + + value = readl(pmc->scratch + SCRATCH_SCRATCH0); + value &= ~SCRATCH_SCRATCH0_MODE_MASK; + + if (cmd) { + if (strcmp(cmd, "recovery") == 0) + value |= SCRATCH_SCRATCH0_MODE_RECOVERY; + + if (strcmp(cmd, "bootloader") == 0) + value |= SCRATCH_SCRATCH0_MODE_BOOTLOADER; + + if (strcmp(cmd, "forced-recovery") == 0) + value |= SCRATCH_SCRATCH0_MODE_RCM; + } + + writel(value, pmc->scratch + SCRATCH_SCRATCH0); + + /* + * If available, call the system restart implementation that was + * registered earlier (typically PSCI). + */ + if (pmc->system_restart) { + pmc->system_restart(reboot_mode, cmd); + return NOTIFY_DONE; + } + + /* reset everything but SCRATCH0_SCRATCH0 and PMC_RST_STATUS */ + value = readl(pmc->regs + PMC_CNTRL); + value |= PMC_CNTRL_MAIN_RST; + writel(value, pmc->regs + PMC_CNTRL); + + return NOTIFY_DONE; +} + +static int tegra186_pmc_setup(struct tegra_pmc *pmc) +{ + struct device_node *np = pmc->dev->of_node; + bool invert; + u32 value; + + invert = of_property_read_bool(np, "nvidia,invert-interrupt"); + + value = readl(pmc->wake + WAKE_AOWAKE_CTRL); + + if (invert) + value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; + else + value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; + + writel(value, pmc->wake + WAKE_AOWAKE_CTRL); + + /* + * We need to hook any system restart implementation registered + * previously so we can write SCRATCH_SCRATCH0 before reset. + */ + pmc->system_restart = arm_pm_restart; + arm_pm_restart = NULL; + + pmc->restart.notifier_call = tegra186_pmc_restart_notify; + pmc->restart.priority = 128; + + return register_restart_handler(&pmc->restart); +} + +static int tegra186_pmc_probe(struct platform_device *pdev) +{ + struct tegra_pmc *pmc; + struct resource *res; + + pmc = devm_kzalloc(&pdev->dev, sizeof(*pmc), GFP_KERNEL); + if (!pmc) + return -ENOMEM; + + pmc->dev = &pdev->dev; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmc"); + pmc->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmc->regs)) + return PTR_ERR(pmc->regs); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); + pmc->wake = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmc->wake)) + return PTR_ERR(pmc->wake); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); + pmc->aotag = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmc->aotag)) + return PTR_ERR(pmc->aotag); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); + pmc->scratch = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmc->scratch)) + return PTR_ERR(pmc->scratch); + + return tegra186_pmc_setup(pmc); +} + +static const struct of_device_id tegra186_pmc_of_match[] = { + { .compatible = "nvidia,tegra186-pmc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tegra186_pmc_of_match); + +static struct platform_driver tegra186_pmc_driver = { + .driver = { + .name = "tegra186-pmc", + .of_match_table = tegra186_pmc_of_match, + }, + .probe = tegra186_pmc_probe, +}; +builtin_platform_driver(tegra186_pmc_driver); -- cgit v1.2.3 From 1859217bec83ebd1b4a220df396905a87285129b Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 13 Nov 2016 14:03:01 -0500 Subject: soc: tegra: make fuse-tegra explicitly non-modular The Makefiles currently controlling compilation of this code is: drivers/soc/tegra/Makefile:obj-y += fuse/ drivers/soc/tegra/fuse/Makefile:obj-y += fuse-tegra.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modularity so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Cc: Stephen Warren Cc: Thierry Reding Cc: Alexandre Courbot Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index de2c1bfe28b5..7413f60fa855 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include @@ -168,7 +168,7 @@ static struct platform_driver tegra_fuse_driver = { }, .probe = tegra_fuse_probe, }; -module_platform_driver(tegra_fuse_driver); +builtin_platform_driver(tegra_fuse_driver); bool __init tegra_fuse_read_spare(unsigned int spare) { -- cgit v1.2.3 From 7e10cf743634a6b0f3cf63046c49294b38254fe9 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 28 Mar 2017 13:42:54 +0100 Subject: soc/tegra: Move Tegra flowctrl driver The flowctrl driver is required for both ARM and ARM64 Tegra devices and in order to enable support for it for ARM64, move the Tegra flowctrl driver into drivers/soc/tegra. By moving the flowctrl driver, tegra_flowctrl_init() is now called by via an early initcall and to prevent this function from attempting to mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()' is also added. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Makefile | 1 - arch/arm/mach-tegra/cpuidle-tegra20.c | 3 +- arch/arm/mach-tegra/flowctrl.c | 171 ------------------------------- arch/arm/mach-tegra/flowctrl.h | 66 ------------ arch/arm/mach-tegra/platsmp.c | 2 +- arch/arm/mach-tegra/pm.c | 2 +- arch/arm/mach-tegra/reset-handler.S | 2 +- arch/arm/mach-tegra/sleep-tegra20.S | 3 +- arch/arm/mach-tegra/sleep-tegra30.S | 2 +- arch/arm/mach-tegra/tegra.c | 2 - drivers/soc/tegra/Kconfig | 7 ++ drivers/soc/tegra/Makefile | 1 + drivers/soc/tegra/flowctrl.c | 187 ++++++++++++++++++++++++++++++++++ include/soc/tegra/flowctrl.h | 82 +++++++++++++++ 14 files changed, 285 insertions(+), 246 deletions(-) delete mode 100644 arch/arm/mach-tegra/flowctrl.c delete mode 100644 arch/arm/mach-tegra/flowctrl.h create mode 100644 drivers/soc/tegra/flowctrl.c create mode 100644 include/soc/tegra/flowctrl.h (limited to 'drivers/soc') diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index fffad2426ee4..3b33f0bb78ae 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -2,7 +2,6 @@ asflags-y += -march=armv7-a obj-y += io.o obj-y += irq.o -obj-y += flowctrl.o obj-y += pm.o obj-y += reset.o obj-y += reset-handler.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index afcee04f2616..76e4c83cd5c8 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -26,12 +26,13 @@ #include #include +#include + #include #include #include #include "cpuidle.h" -#include "flowctrl.h" #include "iomap.h" #include "irq.h" #include "pm.h" diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c deleted file mode 100644 index 475e783992fd..000000000000 --- a/arch/arm/mach-tegra/flowctrl.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * arch/arm/mach-tegra/flowctrl.c - * - * functions and macros to control the flowcontroller - * - * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "flowctrl.h" - -static u8 flowctrl_offset_halt_cpu[] = { - FLOW_CTRL_HALT_CPU0_EVENTS, - FLOW_CTRL_HALT_CPU1_EVENTS, - FLOW_CTRL_HALT_CPU1_EVENTS + 8, - FLOW_CTRL_HALT_CPU1_EVENTS + 16, -}; - -static u8 flowctrl_offset_cpu_csr[] = { - FLOW_CTRL_CPU0_CSR, - FLOW_CTRL_CPU1_CSR, - FLOW_CTRL_CPU1_CSR + 8, - FLOW_CTRL_CPU1_CSR + 16, -}; - -static void __iomem *tegra_flowctrl_base; - -static void flowctrl_update(u8 offset, u32 value) -{ - writel(value, tegra_flowctrl_base + offset); - - /* ensure the update has reached the flow controller */ - wmb(); - readl_relaxed(tegra_flowctrl_base + offset); -} - -u32 flowctrl_read_cpu_csr(unsigned int cpuid) -{ - u8 offset = flowctrl_offset_cpu_csr[cpuid]; - - return readl(tegra_flowctrl_base + offset); -} - -void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) -{ - return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); -} - -void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) -{ - return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); -} - -void flowctrl_cpu_suspend_enter(unsigned int cpuid) -{ - unsigned int reg; - int i; - - reg = flowctrl_read_cpu_csr(cpuid); - switch (tegra_get_chip_id()) { - case TEGRA20: - /* clear wfe bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; - /* pwr gating on wfe */ - reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; - break; - case TEGRA30: - case TEGRA114: - case TEGRA124: - /* clear wfe bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; - /* pwr gating on wfi */ - reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; - break; - } - reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ - reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ - reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ - flowctrl_write_cpu_csr(cpuid, reg); - - for (i = 0; i < num_possible_cpus(); i++) { - if (i == cpuid) - continue; - reg = flowctrl_read_cpu_csr(i); - reg |= FLOW_CTRL_CSR_EVENT_FLAG; - reg |= FLOW_CTRL_CSR_INTR_FLAG; - flowctrl_write_cpu_csr(i, reg); - } -} - -void flowctrl_cpu_suspend_exit(unsigned int cpuid) -{ - unsigned int reg; - - /* Disable powergating via flow controller for CPU0 */ - reg = flowctrl_read_cpu_csr(cpuid); - switch (tegra_get_chip_id()) { - case TEGRA20: - /* clear wfe bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; - break; - case TEGRA30: - case TEGRA114: - case TEGRA124: - /* clear wfe bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; - break; - } - reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ - reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ - reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ - flowctrl_write_cpu_csr(cpuid, reg); -} - -static const struct of_device_id matches[] __initconst = { - { .compatible = "nvidia,tegra124-flowctrl" }, - { .compatible = "nvidia,tegra114-flowctrl" }, - { .compatible = "nvidia,tegra30-flowctrl" }, - { .compatible = "nvidia,tegra20-flowctrl" }, - { } -}; - -void __init tegra_flowctrl_init(void) -{ - /* hardcoded fallback if device tree node is missing */ - unsigned long base = 0x60007000; - unsigned long size = SZ_4K; - struct device_node *np; - - np = of_find_matching_node(NULL, matches); - if (np) { - struct resource res; - - if (of_address_to_resource(np, 0, &res) == 0) { - size = resource_size(&res); - base = res.start; - } - - of_node_put(np); - } - - tegra_flowctrl_base = ioremap_nocache(base, size); -} diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h deleted file mode 100644 index 73a9c5016c1a..000000000000 --- a/arch/arm/mach-tegra/flowctrl.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * arch/arm/mach-tegra/flowctrl.h - * - * functions and macros to control the flowcontroller - * - * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __MACH_TEGRA_FLOWCTRL_H -#define __MACH_TEGRA_FLOWCTRL_H - -#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 -#define FLOW_CTRL_WAITEVENT (2 << 29) -#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) -#define FLOW_CTRL_JTAG_RESUME (1 << 28) -#define FLOW_CTRL_SCLK_RESUME (1 << 27) -#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) -#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) -#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) -#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) -#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) -#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) -#define FLOW_CTRL_CPU0_CSR 0x8 -#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) -#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) -#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) -#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) -#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ - FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ - FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) -#define FLOW_CTRL_CSR_ENABLE (1 << 0) -#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 -#define FLOW_CTRL_CPU1_CSR 0x18 - -#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) -#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) -#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 - -#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) -#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) -#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) - -#ifndef __ASSEMBLY__ -u32 flowctrl_read_cpu_csr(unsigned int cpuid); -void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value); -void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); - -void flowctrl_cpu_suspend_enter(unsigned int cpuid); -void flowctrl_cpu_suspend_exit(unsigned int cpuid); - -void tegra_flowctrl_init(void); -#endif - -#endif diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 75620ae73913..b5a2afe99101 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -30,7 +31,6 @@ #include #include "common.h" -#include "flowctrl.h" #include "iomap.h" #include "reset.h" diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index b0f48a3946fa..1ad5719779b0 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -38,7 +39,6 @@ #include #include -#include "flowctrl.h" #include "iomap.h" #include "pm.h" #include "reset.h" diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index e3070fdab80b..805f306fa6f7 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -17,12 +17,12 @@ #include #include +#include #include #include #include -#include "flowctrl.h" #include "iomap.h" #include "reset.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index f5d19667484e..5c8e638ee51a 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -20,6 +20,8 @@ #include +#include + #include #include #include @@ -27,7 +29,6 @@ #include "irammap.h" #include "sleep.h" -#include "flowctrl.h" #define EMC_CFG 0xc #define EMC_ADR_CFG 0x10 diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 16e5ff03383c..dd4a67dabd91 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -16,13 +16,13 @@ #include +#include #include #include #include #include -#include "flowctrl.h" #include "irammap.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e01cbca196b5..649e9e8c7bcc 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -48,7 +48,6 @@ #include "board.h" #include "common.h" #include "cpuidle.h" -#include "flowctrl.h" #include "iomap.h" #include "irq.h" #include "pm.h" @@ -75,7 +74,6 @@ static void __init tegra_init_early(void) { of_register_trusted_foundations(); tegra_cpu_reset_handler_init(); - tegra_flowctrl_init(); } static void __init tegra_dt_init_irq(void) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 208d6edb3fdb..c7e8ddfb574e 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -12,6 +12,7 @@ config ARCH_TEGRA_2x_SOC select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER help @@ -24,6 +25,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_764369 if SMP select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER help @@ -35,6 +37,7 @@ config ARCH_TEGRA_114_SOC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER help @@ -45,6 +48,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER help @@ -101,6 +105,9 @@ config ARCH_TEGRA_186_SOC endif endif +config SOC_TEGRA_FLOWCTRL + bool + config SOC_TEGRA_PMC bool diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile index b4425e4319ff..4f81dd55e5d1 100644 --- a/drivers/soc/tegra/Makefile +++ b/drivers/soc/tegra/Makefile @@ -1,5 +1,6 @@ obj-y += fuse/ obj-y += common.o +obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o diff --git a/drivers/soc/tegra/flowctrl.c b/drivers/soc/tegra/flowctrl.c new file mode 100644 index 000000000000..3a5a1cb9ae90 --- /dev/null +++ b/drivers/soc/tegra/flowctrl.c @@ -0,0 +1,187 @@ +/* + * drivers/soc/tegra/flowctrl.c + * + * Functions and macros to control the flowcontroller + * + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static u8 flowctrl_offset_halt_cpu[] = { + FLOW_CTRL_HALT_CPU0_EVENTS, + FLOW_CTRL_HALT_CPU1_EVENTS, + FLOW_CTRL_HALT_CPU1_EVENTS + 8, + FLOW_CTRL_HALT_CPU1_EVENTS + 16, +}; + +static u8 flowctrl_offset_cpu_csr[] = { + FLOW_CTRL_CPU0_CSR, + FLOW_CTRL_CPU1_CSR, + FLOW_CTRL_CPU1_CSR + 8, + FLOW_CTRL_CPU1_CSR + 16, +}; + +static void __iomem *tegra_flowctrl_base; + +static void flowctrl_update(u8 offset, u32 value) +{ + if (WARN_ONCE(!tegra_flowctrl_base, + "Tegra flowctrl not initialised!\n")) + return; + + writel(value, tegra_flowctrl_base + offset); + + /* ensure the update has reached the flow controller */ + wmb(); + readl_relaxed(tegra_flowctrl_base + offset); +} + +u32 flowctrl_read_cpu_csr(unsigned int cpuid) +{ + u8 offset = flowctrl_offset_cpu_csr[cpuid]; + + if (WARN_ONCE(!tegra_flowctrl_base, + "Tegra flowctrl not initialised!\n")) + return 0; + + return readl(tegra_flowctrl_base + offset); +} + +void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) +{ + return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); +} + +void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) +{ + return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); +} + +void flowctrl_cpu_suspend_enter(unsigned int cpuid) +{ + unsigned int reg; + int i; + + reg = flowctrl_read_cpu_csr(cpuid); + switch (tegra_get_chip_id()) { + case TEGRA20: + /* clear wfe bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; + /* pwr gating on wfe */ + reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; + break; + case TEGRA30: + case TEGRA114: + case TEGRA124: + /* clear wfe bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; + /* pwr gating on wfi */ + reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; + break; + } + reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ + reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ + reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ + flowctrl_write_cpu_csr(cpuid, reg); + + for (i = 0; i < num_possible_cpus(); i++) { + if (i == cpuid) + continue; + reg = flowctrl_read_cpu_csr(i); + reg |= FLOW_CTRL_CSR_EVENT_FLAG; + reg |= FLOW_CTRL_CSR_INTR_FLAG; + flowctrl_write_cpu_csr(i, reg); + } +} + +void flowctrl_cpu_suspend_exit(unsigned int cpuid) +{ + unsigned int reg; + + /* Disable powergating via flow controller for CPU0 */ + reg = flowctrl_read_cpu_csr(cpuid); + switch (tegra_get_chip_id()) { + case TEGRA20: + /* clear wfe bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; + break; + case TEGRA30: + case TEGRA114: + case TEGRA124: + /* clear wfe bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; + break; + } + reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ + reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ + reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ + flowctrl_write_cpu_csr(cpuid, reg); +} + +static const struct of_device_id matches[] __initconst = { + { .compatible = "nvidia,tegra124-flowctrl" }, + { .compatible = "nvidia,tegra114-flowctrl" }, + { .compatible = "nvidia,tegra30-flowctrl" }, + { .compatible = "nvidia,tegra20-flowctrl" }, + { } +}; + +static int __init tegra_flowctrl_init(void) +{ + /* hardcoded fallback if device tree node is missing */ + unsigned long base = 0x60007000; + unsigned long size = SZ_4K; + struct device_node *np; + + if (!soc_is_tegra()) + return 0; + + np = of_find_matching_node(NULL, matches); + if (np) { + struct resource res; + + if (of_address_to_resource(np, 0, &res) == 0) { + size = resource_size(&res); + base = res.start; + } + + of_node_put(np); + } + + tegra_flowctrl_base = ioremap_nocache(base, size); + if (!tegra_flowctrl_base) + return -ENXIO; + + return 0; +} +early_initcall(tegra_flowctrl_init); diff --git a/include/soc/tegra/flowctrl.h b/include/soc/tegra/flowctrl.h new file mode 100644 index 000000000000..8f86aea4024b --- /dev/null +++ b/include/soc/tegra/flowctrl.h @@ -0,0 +1,82 @@ +/* + * Functions and macros to control the flowcontroller + * + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __SOC_TEGRA_FLOWCTRL_H__ +#define __SOC_TEGRA_FLOWCTRL_H__ + +#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 +#define FLOW_CTRL_WAITEVENT (2 << 29) +#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) +#define FLOW_CTRL_JTAG_RESUME (1 << 28) +#define FLOW_CTRL_SCLK_RESUME (1 << 27) +#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) +#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) +#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) +#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) +#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) +#define FLOW_CTRL_CPU0_CSR 0x8 +#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) +#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) +#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) +#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) +#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ + FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ + FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) +#define FLOW_CTRL_CSR_ENABLE (1 << 0) +#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 +#define FLOW_CTRL_CPU1_CSR 0x18 + +#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) +#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) +#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 + +#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) +#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) +#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_SOC_TEGRA_FLOWCTRL +u32 flowctrl_read_cpu_csr(unsigned int cpuid); +void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value); +void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); + +void flowctrl_cpu_suspend_enter(unsigned int cpuid); +void flowctrl_cpu_suspend_exit(unsigned int cpuid); +#else +static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid) +{ + return 0; +} + +static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) +{ +} + +static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {} + +static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid) +{ +} + +static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid) +{ +} +#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */ +#endif /* __ASSEMBLY */ +#endif /* __SOC_TEGRA_FLOWCTRL_H__ */ -- cgit v1.2.3 From 841fd94c43a4034f08eb830ef7b93a441b4d7378 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 28 Mar 2017 13:42:55 +0100 Subject: soc/tegra: flowctrl: Add basic platform driver Add a simple platform driver for the flowctrl module so that it gets registered as a proper device. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/flowctrl.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/flowctrl.c b/drivers/soc/tegra/flowctrl.c index 3a5a1cb9ae90..25eddfc8475d 100644 --- a/drivers/soc/tegra/flowctrl.c +++ b/drivers/soc/tegra/flowctrl.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -47,7 +48,7 @@ static void __iomem *tegra_flowctrl_base; static void flowctrl_update(u8 offset, u32 value) { - if (WARN_ONCE(!tegra_flowctrl_base, + if (WARN_ONCE(IS_ERR_OR_NULL(tegra_flowctrl_base), "Tegra flowctrl not initialised!\n")) return; @@ -62,7 +63,7 @@ u32 flowctrl_read_cpu_csr(unsigned int cpuid) { u8 offset = flowctrl_offset_cpu_csr[cpuid]; - if (WARN_ONCE(!tegra_flowctrl_base, + if (WARN_ONCE(IS_ERR_OR_NULL(tegra_flowctrl_base), "Tegra flowctrl not initialised!\n")) return 0; @@ -148,7 +149,22 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) flowctrl_write_cpu_csr(cpuid, reg); } -static const struct of_device_id matches[] __initconst = { +static int tegra_flowctrl_probe(struct platform_device *pdev) +{ + void __iomem *base = tegra_flowctrl_base; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + tegra_flowctrl_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tegra_flowctrl_base)) + return PTR_ERR(base); + + iounmap(base); + + return 0; +} + +static const struct of_device_id tegra_flowctrl_match[] = { { .compatible = "nvidia,tegra124-flowctrl" }, { .compatible = "nvidia,tegra114-flowctrl" }, { .compatible = "nvidia,tegra30-flowctrl" }, @@ -156,6 +172,16 @@ static const struct of_device_id matches[] __initconst = { { } }; +static struct platform_driver tegra_flowctrl_driver = { + .driver = { + .name = "tegra-flowctrl", + .suppress_bind_attrs = true, + .of_match_table = tegra_flowctrl_match, + }, + .probe = tegra_flowctrl_probe, +}; +builtin_platform_driver(tegra_flowctrl_driver); + static int __init tegra_flowctrl_init(void) { /* hardcoded fallback if device tree node is missing */ @@ -166,7 +192,7 @@ static int __init tegra_flowctrl_init(void) if (!soc_is_tegra()) return 0; - np = of_find_matching_node(NULL, matches); + np = of_find_matching_node(NULL, tegra_flowctrl_match); if (np) { struct resource res; -- cgit v1.2.3 From 1fd09e5d884a5ff4060948e0cf8f5d7eed16e936 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 28 Mar 2017 13:42:58 +0100 Subject: soc/tegra: Add initial flowctrl support for Tegra132/210 Tegra132 and Tegra210 support the flowctrl module and so add initial support for these devices. Please note that Tegra186 does not support the flowctrl module, so update the initialisation function such that we do not fall back and attempt to map the 'hardcoded' address range for Tegra186. Furthermore 64-bit Tegra devices have always had the flowctrl node defined in their device-tree and so only use the 'hardcoded' addresses for 32-bit Tegra devices. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/Kconfig | 2 ++ drivers/soc/tegra/flowctrl.c | 31 +++++++++++++++++++++---------- 2 files changed, 23 insertions(+), 10 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index c7e8ddfb574e..dcf088db40b6 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -63,6 +63,7 @@ if ARM64 config ARCH_TEGRA_132_SOC bool "NVIDIA Tegra132 SoC" select PINCTRL_TEGRA124 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help Enable support for NVIDIA Tegra132 SoC, based on the Denver @@ -73,6 +74,7 @@ config ARCH_TEGRA_132_SOC config ARCH_TEGRA_210_SOC bool "NVIDIA Tegra210 SoC" select PINCTRL_TEGRA210 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, diff --git a/drivers/soc/tegra/flowctrl.c b/drivers/soc/tegra/flowctrl.c index 25eddfc8475d..0e345c05fc65 100644 --- a/drivers/soc/tegra/flowctrl.c +++ b/drivers/soc/tegra/flowctrl.c @@ -165,6 +165,7 @@ static int tegra_flowctrl_probe(struct platform_device *pdev) } static const struct of_device_id tegra_flowctrl_match[] = { + { .compatible = "nvidia,tegra210-flowctrl" }, { .compatible = "nvidia,tegra124-flowctrl" }, { .compatible = "nvidia,tegra114-flowctrl" }, { .compatible = "nvidia,tegra30-flowctrl" }, @@ -184,9 +185,7 @@ builtin_platform_driver(tegra_flowctrl_driver); static int __init tegra_flowctrl_init(void) { - /* hardcoded fallback if device tree node is missing */ - unsigned long base = 0x60007000; - unsigned long size = SZ_4K; + struct resource res; struct device_node *np; if (!soc_is_tegra()) @@ -194,17 +193,29 @@ static int __init tegra_flowctrl_init(void) np = of_find_matching_node(NULL, tegra_flowctrl_match); if (np) { - struct resource res; - - if (of_address_to_resource(np, 0, &res) == 0) { - size = resource_size(&res); - base = res.start; + if (of_address_to_resource(np, 0, &res) < 0) { + pr_err("failed to get flowctrl register\n"); + return -ENXIO; } - of_node_put(np); + } else if (IS_ENABLED(CONFIG_ARM)) { + /* + * Hardcoded fallback for 32-bit Tegra + * devices if device tree node is missing. + */ + res.start = 0x60007000; + res.end = 0x60007fff; + res.flags = IORESOURCE_MEM; + } else { + /* + * At this point we're running on a Tegra, + * that doesn't support the flow controller + * (eg. Tegra186), so just return. + */ + return 0; } - tegra_flowctrl_base = ioremap_nocache(base, size); + tegra_flowctrl_base = ioremap_nocache(res.start, resource_size(&res)); if (!tegra_flowctrl_base) return -ENXIO; -- cgit v1.2.3