From 9257091cf6df707b64989f15c1e2d4311d694ad3 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 31 Jan 2017 14:47:45 -0800 Subject: soc: brcmstb: Make CPU credit offset more parameterized In preparation for fixing and changing values in the CPU_CREDIT_REG register for B53-based systems, make the offset parameterized. Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/biuctrl.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index 3c39415d484f..c3c548fcaa8c 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -26,6 +26,7 @@ static void __iomem *cpubiuctrl_base; static bool mcp_wr_pairing_en; +static unsigned int cpu_credit_reg_offset = CPU_CREDIT_REG_OFFSET; static int __init mcp_write_pairing_set(void) { @@ -34,15 +35,15 @@ static int __init mcp_write_pairing_set(void) if (!cpubiuctrl_base) return -1; - creds = readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET); + creds = readl_relaxed(cpubiuctrl_base + cpu_credit_reg_offset); if (mcp_wr_pairing_en) { pr_info("MCP: Enabling write pairing\n"); writel_relaxed(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK, - cpubiuctrl_base + CPU_CREDIT_REG_OFFSET); + cpubiuctrl_base + cpu_credit_reg_offset); } else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) { pr_info("MCP: Disabling write pairing\n"); writel_relaxed(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK, - cpubiuctrl_base + CPU_CREDIT_REG_OFFSET); + cpubiuctrl_base + cpu_credit_reg_offset); } else { pr_info("MCP: Write pairing already disabled\n"); } @@ -81,7 +82,7 @@ static int brcmstb_cpu_credit_reg_suspend(void) { if (cpubiuctrl_base) cpu_credit_reg_dump = - readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET); + readl_relaxed(cpubiuctrl_base + cpu_credit_reg_offset); return 0; } @@ -89,7 +90,7 @@ static void brcmstb_cpu_credit_reg_resume(void) { if (cpubiuctrl_base) writel_relaxed(cpu_credit_reg_dump, - cpubiuctrl_base + CPU_CREDIT_REG_OFFSET); + cpubiuctrl_base + cpu_credit_reg_offset); } static struct syscore_ops brcmstb_cpu_credit_syscore_ops = { -- cgit v1.2.3 From 22f7a9116eba9a5f16341706f83b9e09098b15f9 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 31 Jan 2017 14:54:00 -0800 Subject: soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs On Broadcom Brahma-B53 CPUs, the CPU_CREDIT_REG offset got moved to 0x0b0 instead of 0x184, correct this such that we correcty enable/disable write-pairing for these chips. Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/biuctrl.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index c3c548fcaa8c..e8322e663831 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -21,12 +21,13 @@ #include #include -#define CPU_CREDIT_REG_OFFSET 0x184 +#define B15_CPU_CREDIT_REG_OFFSET 0x184 +#define B53_CPU_CREDIT_REG_OFFSET 0x0b0 #define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000 static void __iomem *cpubiuctrl_base; static bool mcp_wr_pairing_en; -static unsigned int cpu_credit_reg_offset = CPU_CREDIT_REG_OFFSET; +static unsigned int cpu_credit_reg_offset; static int __init mcp_write_pairing_set(void) { @@ -53,7 +54,7 @@ static int __init mcp_write_pairing_set(void) static int __init setup_hifcpubiuctrl_regs(void) { - struct device_node *np; + struct device_node *np, *cpu_dn; int ret = 0; np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl"); @@ -70,6 +71,23 @@ static int __init setup_hifcpubiuctrl_regs(void) } mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing"); + + cpu_dn = of_get_cpu_node(0, NULL); + if (!cpu_dn) { + pr_err("failed to obtain CPU device node\n"); + ret = -ENODEV; + goto out; + } + + if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15")) + cpu_credit_reg_offset = B15_CPU_CREDIT_REG_OFFSET; + else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53")) + cpu_credit_reg_offset = B53_CPU_CREDIT_REG_OFFSET; + else { + pr_err("unsupported CPU\n"); + ret = -EINVAL; + } + of_node_put(cpu_dn); out: of_node_put(np); return ret; -- cgit v1.2.3 From 584e55d543d86ebbc0ddb28f55619292e6eb308a Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 27 Feb 2017 16:36:17 -0800 Subject: soc: brcmstb: biuctrl: Prepare for saving/restoring other registers In preparation for saving/restoring additional registers required on some newer platforms (7268, 7271, 7278), migrate the code to use enums and helper functions to access registers. Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/biuctrl.c | 75 ++++++++++++++++++++++++++++++--------- 1 file changed, 58 insertions(+), 17 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index e8322e663831..16cbfc2e953a 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -21,13 +21,45 @@ #include #include -#define B15_CPU_CREDIT_REG_OFFSET 0x184 -#define B53_CPU_CREDIT_REG_OFFSET 0x0b0 #define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000 static void __iomem *cpubiuctrl_base; static bool mcp_wr_pairing_en; -static unsigned int cpu_credit_reg_offset; +static const int *cpubiuctrl_regs; + +static inline u32 cbc_readl(int reg) +{ + int offset = cpubiuctrl_regs[reg]; + + if (offset == -1) + return (u32)-1; + + return readl_relaxed(cpubiuctrl_base + offset); +} + +static inline void cbc_writel(u32 val, int reg) +{ + int offset = cpubiuctrl_regs[reg]; + + if (offset == -1) + return; + + writel_relaxed(val, cpubiuctrl_base + offset); +} + +enum cpubiuctrl_regs { + CPU_CREDIT_REG = 0, +}; + +static const int b15_cpubiuctrl_regs[] = { + [CPU_CREDIT_REG] = 0x184, +}; + +static const int b53_cpubiuctrl_regs[] = { + [CPU_CREDIT_REG] = 0x0b0, +}; + +#define NUM_CPU_BIUCTRL_REGS 1 static int __init mcp_write_pairing_set(void) { @@ -36,15 +68,15 @@ static int __init mcp_write_pairing_set(void) if (!cpubiuctrl_base) return -1; - creds = readl_relaxed(cpubiuctrl_base + cpu_credit_reg_offset); + creds = cbc_readl(CPU_CREDIT_REG); if (mcp_wr_pairing_en) { pr_info("MCP: Enabling write pairing\n"); - writel_relaxed(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK, - cpubiuctrl_base + cpu_credit_reg_offset); + cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK, + CPU_CREDIT_REG); } else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) { pr_info("MCP: Disabling write pairing\n"); - writel_relaxed(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK, - cpubiuctrl_base + cpu_credit_reg_offset); + cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK, + CPU_CREDIT_REG); } else { pr_info("MCP: Write pairing already disabled\n"); } @@ -80,9 +112,9 @@ static int __init setup_hifcpubiuctrl_regs(void) } if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15")) - cpu_credit_reg_offset = B15_CPU_CREDIT_REG_OFFSET; + cpubiuctrl_regs = b15_cpubiuctrl_regs; else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53")) - cpu_credit_reg_offset = B53_CPU_CREDIT_REG_OFFSET; + cpubiuctrl_regs = b53_cpubiuctrl_regs; else { pr_err("unsupported CPU\n"); ret = -EINVAL; @@ -94,21 +126,30 @@ out: } #ifdef CONFIG_PM_SLEEP -static u32 cpu_credit_reg_dump; /* for save/restore */ +static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS]; static int brcmstb_cpu_credit_reg_suspend(void) { - if (cpubiuctrl_base) - cpu_credit_reg_dump = - readl_relaxed(cpubiuctrl_base + cpu_credit_reg_offset); + unsigned int i; + + if (!cpubiuctrl_base) + return 0; + + for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++) + cpubiuctrl_reg_save[i] = cbc_readl(i); + return 0; } static void brcmstb_cpu_credit_reg_resume(void) { - if (cpubiuctrl_base) - writel_relaxed(cpu_credit_reg_dump, - cpubiuctrl_base + cpu_credit_reg_offset); + unsigned int i; + + if (!cpubiuctrl_base) + return; + + for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++) + cbc_writel(cpubiuctrl_reg_save[i], i); } static struct syscore_ops brcmstb_cpu_credit_syscore_ops = { -- cgit v1.2.3 From 6451d644b8f3d7188778bac60e3543274b41ae30 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 27 Feb 2017 16:40:05 -0800 Subject: soc: brcmstb: biuctrl: Wire-up new registers Add definitions for B53 systems register: CPU_MCP_FLOW_REG and CPU_WRITEBACK_CTRL_REG. These register will be saved and restored accordingly. Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/biuctrl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index 16cbfc2e953a..d498f9db01ab 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -49,17 +49,23 @@ static inline void cbc_writel(u32 val, int reg) enum cpubiuctrl_regs { CPU_CREDIT_REG = 0, + CPU_MCP_FLOW_REG, + CPU_WRITEBACK_CTRL_REG }; static const int b15_cpubiuctrl_regs[] = { [CPU_CREDIT_REG] = 0x184, + [CPU_MCP_FLOW_REG] = -1, + [CPU_WRITEBACK_CTRL_REG] = -1, }; static const int b53_cpubiuctrl_regs[] = { [CPU_CREDIT_REG] = 0x0b0, + [CPU_MCP_FLOW_REG] = 0x0b4, + [CPU_WRITEBACK_CTRL_REG] = 0x22c, }; -#define NUM_CPU_BIUCTRL_REGS 1 +#define NUM_CPU_BIUCTRL_REGS 3 static int __init mcp_write_pairing_set(void) { -- cgit v1.2.3 From b4b32e321639859738e0226f42e05ed0f7e2fc64 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 27 Feb 2017 17:35:03 -0800 Subject: soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings In order to achieve expected MCP bus throughput on 3 particular chips: 7268, 7271 and 7278, do the appropriate programming of the MCP interface: increase number of MCP write credits, turn on write-back throttling when present. Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/biuctrl.c | 76 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index d498f9db01ab..dd45bbfe64dd 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -22,6 +22,18 @@ #include #define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000 +#define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf +#define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf +#define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8) +#define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4) + +#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8) +#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff + +#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf +#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf +#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4 +#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8) static void __iomem *cpubiuctrl_base; static bool mcp_wr_pairing_en; @@ -59,6 +71,13 @@ static const int b15_cpubiuctrl_regs[] = { [CPU_WRITEBACK_CTRL_REG] = -1, }; +/* Odd cases, e.g: 7260 */ +static const int b53_cpubiuctrl_no_wb_regs[] = { + [CPU_CREDIT_REG] = 0x0b0, + [CPU_MCP_FLOW_REG] = 0x0b4, + [CPU_WRITEBACK_CTRL_REG] = -1, +}; + static const int b53_cpubiuctrl_regs[] = { [CPU_CREDIT_REG] = 0x0b0, [CPU_MCP_FLOW_REG] = 0x0b4, @@ -90,6 +109,59 @@ static int __init mcp_write_pairing_set(void) return 0; } +static const u32 b53_mach_compat[] = { + 0x7268, + 0x7271, + 0x7278, +}; + +static void __init mcp_b53_set(void) +{ + unsigned int i; + u32 reg; + + reg = brcmstb_get_family_id(); + + for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) { + if (BRCM_ID(reg) == b53_mach_compat[i]) + break; + } + + if (i == ARRAY_SIZE(b53_mach_compat)) + return; + + /* Set all 3 MCP interfaces to 8 credits */ + reg = cbc_readl(CPU_CREDIT_REG); + for (i = 0; i < 3; i++) { + reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK << + CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i)); + reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK << + CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i)); + reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i); + reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i); + } + cbc_writel(reg, CPU_CREDIT_REG); + + /* Max out the number of in-flight Jwords reads on the MCP interface */ + reg = cbc_readl(CPU_MCP_FLOW_REG); + for (i = 0; i < 3; i++) + reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK << + CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i); + cbc_writel(reg, CPU_MCP_FLOW_REG); + + /* Enable writeback throttling, set timeout to 128 cycles, 256 cycles + * threshold + */ + reg = cbc_readl(CPU_WRITEBACK_CTRL_REG); + reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE; + reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK; + reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK << + CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT); + reg |= 8; + reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT; + cbc_writel(reg, CPU_WRITEBACK_CTRL_REG); +} + static int __init setup_hifcpubiuctrl_regs(void) { struct device_node *np, *cpu_dn; @@ -126,6 +198,9 @@ static int __init setup_hifcpubiuctrl_regs(void) ret = -EINVAL; } of_node_put(cpu_dn); + + if (BRCM_ID(brcmstb_get_family_id()) == 0x7260) + cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs; out: of_node_put(np); return ret; @@ -177,6 +252,7 @@ void __init brcmstb_biuctrl_init(void) return; } + mcp_b53_set(); #ifdef CONFIG_PM_SLEEP register_syscore_ops(&brcmstb_cpu_credit_syscore_ops); #endif -- cgit v1.2.3 From 5d4567ec3bacf058cdf8e67695759e0d137cf095 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 29 Nov 2017 10:54:16 -0800 Subject: soc: brcmstb: Split initialization We may need access to family_id and product_id fairly early on boot for other parts of the code (e.g: biuctrl.c), so split the initialization between an early_init() and an arch_initcall() which allows us to do that. Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/common.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/common.c b/drivers/soc/bcm/brcmstb/common.c index a71730da6385..781ada62d0a3 100644 --- a/drivers/soc/bcm/brcmstb/common.c +++ b/drivers/soc/bcm/brcmstb/common.c @@ -66,13 +66,10 @@ static const struct of_device_id sun_top_ctrl_match[] = { { } }; -static int __init brcmstb_soc_device_init(void) +static int __init brcmstb_soc_device_early_init(void) { - struct soc_device_attribute *soc_dev_attr; - struct soc_device *soc_dev; struct device_node *sun_top_ctrl; void __iomem *sun_top_ctrl_base; - int ret = 0; sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match); if (!sun_top_ctrl) @@ -84,12 +81,19 @@ static int __init brcmstb_soc_device_init(void) family_id = readl(sun_top_ctrl_base); product_id = readl(sun_top_ctrl_base + 0x4); + iounmap(sun_top_ctrl_base); + return 0; +} +early_initcall(brcmstb_soc_device_early_init); + +static int __init brcmstb_soc_device_init(void) +{ + struct soc_device_attribute *soc_dev_attr; + struct soc_device *soc_dev; soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) { - ret = -ENOMEM; - goto out; - } + if (!soc_dev_attr) + return -ENOMEM; soc_dev_attr->family = kasprintf(GFP_KERNEL, "%x", family_id >> 28 ? @@ -107,14 +111,9 @@ static int __init brcmstb_soc_device_init(void) kfree(soc_dev_attr->soc_id); kfree(soc_dev_attr->revision); kfree(soc_dev_attr); - ret = -ENODEV; - goto out; + return -ENOMEM; } return 0; - -out: - iounmap(sun_top_ctrl_base); - return ret; } arch_initcall(brcmstb_soc_device_init); -- cgit v1.2.3 From f780429adfbc222a4d8a227a2a550ba627c7338b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 11 Apr 2017 17:26:11 -0700 Subject: soc: brcmstb: biuctrl: Move to early_initcall Being called during early_initcall() is early enough that it occurs before SMP initialization, which is all we care about for the Bus Interface Unit configuration. This solves lack of BIU initialization on ARM64 platforms where we do not have an anchor where to put the BIU initialization (since there are no machine descriptors). Signed-off-by: Florian Fainelli --- arch/arm/mach-bcm/brcmstb.c | 2 -- drivers/soc/bcm/brcmstb/biuctrl.c | 6 ++++-- include/linux/soc/brcmstb/brcmstb.h | 6 ------ 3 files changed, 4 insertions(+), 10 deletions(-) (limited to 'drivers/soc') diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c index 07e3a86c6466..5f127d5f1045 100644 --- a/arch/arm/mach-bcm/brcmstb.c +++ b/arch/arm/mach-bcm/brcmstb.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include @@ -38,7 +37,6 @@ u32 brcmstb_uart_config[3] = { static void __init brcmstb_init_irq(void) { irqchip_init(); - brcmstb_biuctrl_init(); } static const char *const brcmstb_match[] __initconst = { diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index dd45bbfe64dd..2b23ae7b5e9b 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -240,7 +240,7 @@ static struct syscore_ops brcmstb_cpu_credit_syscore_ops = { #endif -void __init brcmstb_biuctrl_init(void) +static int __init brcmstb_biuctrl_init(void) { int ret; @@ -249,11 +249,13 @@ void __init brcmstb_biuctrl_init(void) ret = mcp_write_pairing_set(); if (ret) { pr_err("MCP: Unable to disable write pairing!\n"); - return; + return ret; } mcp_b53_set(); #ifdef CONFIG_PM_SLEEP register_syscore_ops(&brcmstb_cpu_credit_syscore_ops); #endif + return 0; } +early_initcall(brcmstb_biuctrl_init); diff --git a/include/linux/soc/brcmstb/brcmstb.h b/include/linux/soc/brcmstb/brcmstb.h index 12e548938bbb..8e884e0dda0a 100644 --- a/include/linux/soc/brcmstb/brcmstb.h +++ b/include/linux/soc/brcmstb/brcmstb.h @@ -12,12 +12,6 @@ static inline u32 BRCM_REV(u32 reg) return reg & 0xff; } -/* - * Bus Interface Unit control register setup, must happen early during boot, - * before SMP is brought up, called by machine entry point. - */ -void brcmstb_biuctrl_init(void); - /* * Helper functions for getting family or product id from the * SoC driver. -- cgit v1.2.3