From 16cc4af286aae85859ee39e25d21f3d910f8175d Mon Sep 17 00:00:00 2001 From: Shaokun Zhang Date: Tue, 28 Sep 2021 20:30:22 +0800 Subject: drivers/perf: hisi: Fix PA PMU counter offset The PA PMU counter offset was correct in [1] and the driver has already been verified. We want to keep the register offset using lower case character in later version that is consistent with the existed driver. Since there was no functional change, we didn't do more test. However there is typo when modified the PA PMU counter offset by mistake, so fix this bad mistake. [1] https://www.spinics.net/lists/arm-kernel/msg865263.html Cc: Will Deacon Cc: Mark Rutland Cc: John Garry Cc: Qi Liu Signed-off-by: Shaokun Zhang Link: https://lore.kernel.org/r/20210928123022.23467-1-zhangshaokun@hisilicon.com Signed-off-by: Will Deacon --- drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c index 83264ec0a957..bad99d149172 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c @@ -27,7 +27,7 @@ #define PA_INT_CLEAR 0x1c7c #define PA_EVENT_TYPE0 0x1c80 #define PA_PMU_VERSION 0x1cf0 -#define PA_EVENT_CNT0_L 0x1f00 +#define PA_EVENT_CNT0_L 0x1d00 #define PA_EVTYPE_MASK 0xff #define PA_NR_COUNTERS 0x8 -- cgit v1.2.3 From 78cac393b4642eb5936d9c0685acd50d8370648f Mon Sep 17 00:00:00 2001 From: John Garry Date: Fri, 1 Oct 2021 18:48:45 +0800 Subject: drivers/perf: thunderx2_pmu: Change data in size tx2_uncore_event_update() A LSL of 32 requires > 32b value to hold the result. However in tx2_uncore_event_update(), 1UL << 32 currently only works as unsigned long is 64b on a 64b system. If we want to compile test for a 32b system, we need unsigned long long, whose min size is 64b. Signed-off-by: John Garry Link: https://lore.kernel.org/r/1633085326-156653-2-git-send-email-john.garry@huawei.com Signed-off-by: Will Deacon --- drivers/perf/thunderx2_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/perf/thunderx2_pmu.c b/drivers/perf/thunderx2_pmu.c index fc1a376ee906..05378c0fd8f3 100644 --- a/drivers/perf/thunderx2_pmu.c +++ b/drivers/perf/thunderx2_pmu.c @@ -487,7 +487,7 @@ static void tx2_uncore_event_update(struct perf_event *event) new = reg_readl(hwc->event_base); prev = local64_xchg(&hwc->prev_count, new); /* handles rollover of 32 bit counter */ - delta = (u32)(((1UL << 32) - prev) + new); + delta = (u32)(((1ULL << 32) - prev) + new); } /* DMC event data_transfers granularity is 16 Bytes, convert it to 64 */ -- cgit v1.2.3 From e656972b69864348a747954ea187576808000c5a Mon Sep 17 00:00:00 2001 From: John Garry Date: Fri, 1 Oct 2021 18:48:46 +0800 Subject: drivers/perf: Improve build test coverage Improve build test cover by allowing some drivers to build under COMPILE_TEST where possible. Some notes: - Mostly a dependency on CONFIG_ACPI is not really required for only building (but left untouched), but is required for TX2 which uses ACPI functions which have no stubs - XGENE required 64b dependency as it relies on some unsigned long perf struct fields being 64b - I don't see why TX2 requires NUMA to build, but left untouched - Added an explicit dependency on GENERIC_MSI_IRQ_DOMAIN for ARM_SMMU_V3_PMU, which is required for platform MSI functions Signed-off-by: John Garry Link: https://lore.kernel.org/r/1633085326-156653-3-git-send-email-john.garry@huawei.com Signed-off-by: Will Deacon --- drivers/perf/Kconfig | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 77522e5efe11..4374af292e6d 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -36,7 +36,7 @@ config ARM_CCI5xx_PMU config ARM_CCN tristate "ARM CCN driver support" - depends on ARM || ARM64 + depends on ARM || ARM64 || COMPILE_TEST help PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) interconnect. @@ -62,7 +62,8 @@ config ARM_PMU_ACPI config ARM_SMMU_V3_PMU tristate "ARM SMMUv3 Performance Monitors Extension" - depends on ARM64 && ACPI + depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT) + depends on GENERIC_MSI_IRQ_DOMAIN help Provides support for the ARM SMMUv3 Performance Monitor Counter Groups (PMCG), which provide monitoring of transactions passing @@ -80,7 +81,7 @@ config ARM_DSU_PMU config FSL_IMX8_DDR_PMU tristate "Freescale i.MX8 DDR perf monitor" - depends on ARCH_MXC + depends on ARCH_MXC || COMPILE_TEST help Provides support for the DDR performance monitor in i.MX8, which can give information about memory throughput and other related @@ -108,7 +109,8 @@ config QCOM_L3_PMU config THUNDERX2_PMU tristate "Cavium ThunderX2 SoC PMU UNCORE" - depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA + depends on ARCH_THUNDER2 || COMPILE_TEST + depends on NUMA && ACPI default m help Provides support for ThunderX2 UNCORE events. @@ -116,7 +118,7 @@ config THUNDERX2_PMU in the DDR4 Memory Controller (DMC). config XGENE_PMU - depends on ARCH_XGENE + depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) bool "APM X-Gene SoC PMU" default n help -- cgit v1.2.3