From 2046b94e7c4fce92eb8165c2c36c6478f4927178 Mon Sep 17 00:00:00 2001 From: Fenghua Yu Date: Fri, 4 Apr 2008 11:05:59 -0700 Subject: [IA64] Multiple outstanding ptc.g instruction support According to SDM2.2, Itanium supports multiple outstanding ptc.g instructions. But current kernel function ia64_global_tlb_purge() uses a spinlock to serialize ptc.g instructions issued by multiple processors. This serialization might have scalability issue on a big SMP machine where many processors could purge TLB in parallel. The patch fixes this problem by issuing multiple ptc.g instructions in ia64_global_tlb_purge(). It also adds support for the "PALO" table to get a platform view of the max number of outstanding ptc.g instructions (which may be different from the processor view found from PAL_VM_SUMMARY). PALO specification can be found at: http://www.dig64.org/home/DIG64_PALO_R1_0.pdf spinaphore implementation by Matthew Wilcox. Signed-off-by: Fenghua Yu Signed-off-by: Tony Luck --- include/asm-ia64/sal.h | 17 +++++++++++++++++ include/asm-ia64/tlbflush.h | 1 + 2 files changed, 18 insertions(+) (limited to 'include/asm-ia64') diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h index f4904db3b057..3cd637a2c051 100644 --- a/include/asm-ia64/sal.h +++ b/include/asm-ia64/sal.h @@ -296,6 +296,9 @@ enum { EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) #define SAL_PLAT_BUS_ERR_SECT_GUID \ EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) +#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \ + EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \ + 0xca, 0x4d) #define MAX_CACHE_ERRORS 6 #define MAX_TLB_ERRORS 6 @@ -879,6 +882,20 @@ extern void ia64_jump_to_sal(struct sal_to_os_boot *); extern void ia64_sal_handler_init(void *entry_point, void *gpval); +#define PALO_MAX_TLB_PURGES 0xFFFF +#define PALO_SIG "PALO" + +struct palo_table { + u8 signature[4]; /* Should be "PALO" */ + u32 length; + u8 minor_revision; + u8 major_revision; + u8 checksum; + u8 reserved1[5]; + u16 max_tlb_purges; + u8 reserved2[6]; +}; + #endif /* __ASSEMBLY__ */ #endif /* _ASM_IA64_SAL_H */ diff --git a/include/asm-ia64/tlbflush.h b/include/asm-ia64/tlbflush.h index 7774a1cac0cc..3be25dfed164 100644 --- a/include/asm-ia64/tlbflush.h +++ b/include/asm-ia64/tlbflush.h @@ -17,6 +17,7 @@ * Now for some TLB flushing routines. This is the kind of stuff that * can be very expensive, so try to avoid them whenever possible. */ +extern void setup_ptcg_sem(int max_purges, int from_palo); /* * Flush everything (kernel mapping may also have changed due to -- cgit v1.2.3 From a6c75b86ce9f01db4ea9912877b526c2dc4d2f0a Mon Sep 17 00:00:00 2001 From: Fenghua Yu Date: Fri, 14 Mar 2008 13:57:08 -0700 Subject: [IA64] Kernel parameter for max number of concurrent global TLB purges The patch defines kernel parameter "nptcg=". The parameter overrides max number of concurrent global TLB purges which is reported from either PAL_VM_SUMMARY or SAL PALO. Signed-off-by: Fenghua Yu Signed-off-by: Tony Luck --- Documentation/kernel-parameters.txt | 4 ++++ arch/ia64/kernel/efi.c | 2 +- arch/ia64/kernel/setup.c | 2 +- arch/ia64/mm/tlb.c | 46 +++++++++++++++++++++++++++++++++---- include/asm-ia64/sal.h | 4 ++++ 5 files changed, 51 insertions(+), 7 deletions(-) (limited to 'include/asm-ia64') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 4cd1a5da80a4..be92e6165722 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1335,6 +1335,10 @@ and is between 256 and 4096 characters. It is defined in the file nowb [ARM] + nptcg= [IA64] Override max number of concurrent global TLB + purges which is reported from either PAL_VM_SUMMARY or + SAL PALO. + numa_zonelist_order= [KNL, BOOT] Select zonelist order for NUMA. one of ['zone', 'node', 'default'] can be specified This can be set from sysctl after boot. diff --git a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c index 003cd09b0732..d45f215bc8fc 100644 --- a/arch/ia64/kernel/efi.c +++ b/arch/ia64/kernel/efi.c @@ -436,7 +436,7 @@ static void __init handle_palo(unsigned long palo_phys) return; } - setup_ptcg_sem(palo->max_tlb_purges, 1); + setup_ptcg_sem(palo->max_tlb_purges, NPTCG_FROM_PALO); } void diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index 1cbd26340d87..f798c0769d36 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c @@ -949,7 +949,7 @@ cpu_init (void) /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ if (ia64_pal_vm_summary(NULL, &vmi) == 0) { max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; - setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, 0); + setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); } else { printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); max_ctx = (1U << 15) - 1; /* use architected minimum */ diff --git a/arch/ia64/mm/tlb.c b/arch/ia64/mm/tlb.c index d41d6076ed03..1a8948fd0029 100644 --- a/arch/ia64/mm/tlb.c +++ b/arch/ia64/mm/tlb.c @@ -119,6 +119,27 @@ static u16 nptcg = 1; static int need_ptcg_sem = 1; static int toolatetochangeptcgsem = 0; +/* + * Kernel parameter "nptcg=" overrides max number of concurrent global TLB + * purges which is reported from either PAL or SAL PALO. + * + * We don't have sanity checking for nptcg value. It's the user's responsibility + * for valid nptcg value on the platform. Otherwise, kernel may hang in some + * cases. + */ +static int __init +set_nptcg(char *str) +{ + int value = 0; + + get_option(&str, &value); + setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER); + + return 1; +} + +__setup("nptcg=", set_nptcg); + /* * Maximum number of simultaneous ptc.g purges in the system can * be defined by PAL_VM_SUMMARY (in which case we should take @@ -126,13 +147,18 @@ static int toolatetochangeptcgsem = 0; * override table (in which case we should ignore the value from * PAL_VM_SUMMARY). * + * Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g + * purges defined in either PAL_VM_SUMMARY or PAL override table. In this case, + * we should ignore the value from either PAL_VM_SUMMARY or PAL override table. + * * Complicating the logic here is the fact that num_possible_cpus() * isn't fully setup until we start bringing cpus online. */ void -setup_ptcg_sem(int max_purges, int from_palo) +setup_ptcg_sem(int max_purges, int nptcg_from) { - static int have_palo; + static int kp_override; + static int palo_override; static int firstcpu = 1; if (toolatetochangeptcgsem) { @@ -140,8 +166,18 @@ setup_ptcg_sem(int max_purges, int from_palo) return; } - if (from_palo) { - have_palo = 1; + if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) { + kp_override = 1; + nptcg = max_purges; + goto resetsema; + } + if (kp_override) { + need_ptcg_sem = num_possible_cpus() > nptcg; + return; + } + + if (nptcg_from == NPTCG_FROM_PALO) { + palo_override = 1; /* In PALO max_purges == 0 really means it! */ if (max_purges == 0) @@ -153,7 +189,7 @@ setup_ptcg_sem(int max_purges, int from_palo) } goto resetsema; } - if (have_palo) { + if (palo_override) { if (nptcg != PALO_MAX_TLB_PURGES) need_ptcg_sem = (num_possible_cpus() > nptcg); return; diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h index 3cd637a2c051..89594b442f83 100644 --- a/include/asm-ia64/sal.h +++ b/include/asm-ia64/sal.h @@ -896,6 +896,10 @@ struct palo_table { u8 reserved2[6]; }; +#define NPTCG_FROM_PAL 0 +#define NPTCG_FROM_PALO 1 +#define NPTCG_FROM_KERNEL_PARAMETER 2 + #endif /* __ASSEMBLY__ */ #endif /* _ASM_IA64_SAL_H */ -- cgit v1.2.3