From c7c12de893f808bd7c1215fe9056262295e5203b Mon Sep 17 00:00:00 2001 From: Juha-Pekka Heikkila Date: Sun, 14 May 2023 21:42:39 +0300 Subject: drm/fourcc: define Intel Meteorlake related ccs modifiers Add Tile4 type ccs modifiers with aux buffer needed for MTL Bspec: 49251, 49252, 49253 Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula Signed-off-by: Juha-Pekka Heikkila Reviewed-by: Matt Atwood Acked-by: Thomas Zimmermann Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20230514184240.6184-1-juhapekka.heikkila@gmail.com --- include/uapi/drm/drm_fourcc.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'include') diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index de703c6be969..8db7fd3f743e 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -657,6 +657,49 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) +/* + * Intel Color Control Surfaces (CCS) for display ver. 14 render compression. + * + * The main surface is tile4 and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * tile4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13) + +/* + * Intel Color Control Surfaces (CCS) for display ver. 14 media compression + * + * The main surface is tile4 and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * tile4 widths. For semi-planar formats like NV12, CCS planes follow the + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, + * planes 2 and 3 for the respective CCS. + */ +#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14) + +/* + * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render + * compression. + * + * The main surface is tile4 and is at plane index 0 whereas CCS is linear + * and at index 1. The clear color is stored at index 2, and the pitch should + * be ignored. The clear color structure is 256 bits. The first 128 bits + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented + * by 32 bits. The raw clear color is consumed by the 3d engine and generates + * the converted clear color of size 64 bits. The first 32 bits store the Lower + * Converted Clear Color value and the next 32 bits store the Higher Converted + * Clear Color value when applicable. The Converted Clear Color values are + * consumed by the DE. The last 64 bits are used to store Color Discard Enable + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line + * corresponds to an area of 4x1 tiles in the main surface. The main surface + * pitch is required to be a multiple of 4 tile widths. + */ +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * -- cgit v1.2.3 From 169219213c144abf0f2cc86886df218159dbe4b7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 17 May 2023 13:28:01 +0300 Subject: drm/i915/dsc: move rc_buf_thresh values to common helper The rc_buf_thresh values are common to all DSC implementations. Move them to the common helper together with the code to propagate them to the drm_dsc_config. Reviewed-by: Jani Nikula Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20230517102807.2181589-3-dmitry.baryshkov@linaro.org Acked-by: Dave Airlie --- drivers/gpu/drm/display/drm_dsc_helper.c | 35 +++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +-------------------- include/drm/display/drm_dsc_helper.h | 1 + 3 files changed, 37 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index c869c6e51e2b..be91abe2cfb2 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -270,6 +270,41 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, } EXPORT_SYMBOL(drm_dsc_pps_payload_pack); +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ +static const u16 drm_dsc_rc_buf_thresh[] = { + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, + 7744, 7872, 8000, 8064 +}; + +/** + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model + * in accordance with the DSC 1.2 specification. + * + * @vdsc_cfg: DSC Configuration data partially filled by driver + */ +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg) +{ + int i; + + BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) != + DSC_NUM_BUF_RANGES - 1); + BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) != + ARRAY_SIZE(vdsc_cfg->rc_buf_thresh)); + + for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++) + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6; + + /* + * For 6bpp, RC Buffer threshold 12 and 13 need a different value + * as per C Model + */ + if (vdsc_cfg->bits_per_pixel == 6 << 4) { + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6; + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6; + } +} +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh); + /** * drm_dsc_compute_rc_parameters() - Write rate control * parameters to the dsc configuration defined in diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 7003ae9f683a..2fd08375bbe3 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -37,12 +37,6 @@ enum COLUMN_INDEX_BPC { MAX_COLUMN_INDEX }; -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ -static const u16 rc_buf_thresh[] = { - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, - 7744, 7872, 8000, 8064 -}; - struct rc_parameters { u16 initial_xmit_delay; u8 first_line_bpg_offset; @@ -543,23 +537,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { - /* - * six 0s are appended to the lsb of each threshold value - * internally in h/w. - * Only 8 bits are allowed for programming RcBufThreshold - */ - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; - } - - /* - * For 6bpp, RC Buffer threshold 12 and 13 need a different value - * as per C Model - */ - if (compressed_bpp == 6) { - vdsc_cfg->rc_buf_thresh[12] = 0x7C; - vdsc_cfg->rc_buf_thresh[13] = 0x7D; - } + drm_dsc_set_rc_buf_thresh(vdsc_cfg); /* * From XE_LPD onwards we supports compression bpps in steps of 1 diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 8b41edbbabab..706ba1d34742 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif /* _DRM_DSC_HELPER_H_ */ -- cgit v1.2.3 From 2b470e5531f57c1b9bfa129cca0ee17a2ecd2183 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 17 May 2023 13:28:02 +0300 Subject: drm/i915/dsc: move DSC tables to DRM DSC helper Move DSC RC tables to DRM DSC helper. No additional code changes and/or cleanups are a part of this commit, it will be cleaned up in the followup commits. Reviewed-by: Jani Nikula Signed-off-by: Dmitry Baryshkov Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20230517102807.2181589-4-dmitry.baryshkov@linaro.org Acked-by: Dave Airlie --- drivers/gpu/drm/display/drm_dsc_helper.c | 372 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------------ include/drm/display/drm_dsc_helper.h | 1 + 3 files changed, 380 insertions(+), 312 deletions(-) (limited to 'include') diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index be91abe2cfb2..122a292bbc8f 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -305,6 +305,378 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg) } EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh); +enum ROW_INDEX_BPP { + ROW_INDEX_6BPP = 0, + ROW_INDEX_8BPP, + ROW_INDEX_10BPP, + ROW_INDEX_12BPP, + ROW_INDEX_15BPP, + MAX_ROW_INDEX +}; + +enum COLUMN_INDEX_BPC { + COLUMN_INDEX_8BPC = 0, + COLUMN_INDEX_10BPC, + COLUMN_INDEX_12BPC, + COLUMN_INDEX_14BPC, + COLUMN_INDEX_16BPC, + MAX_COLUMN_INDEX +}; + +struct rc_parameters { + u16 initial_xmit_delay; + u8 first_line_bpg_offset; + u16 initial_offset; + u8 flatness_min_qp; + u8 flatness_max_qp; + u8 rc_quant_incr_limit0; + u8 rc_quant_incr_limit1; + struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; +}; + +/* + * Selected Rate Control Related Parameter Recommended Values + * from DSC_v1.11 spec & C Model release: DSC_model_20161212 + */ +static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { + { + /* 6BPP/8BPC */ + { 768, 15, 6144, 3, 13, 11, 11, { + { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, + { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, + { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, + { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } + } + }, + /* 6BPP/10BPC */ + { 768, 15, 6144, 7, 17, 15, 15, { + { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, + { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, + { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, + { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, + { 17, 18, -12 } + } + }, + /* 6BPP/12BPC */ + { 768, 15, 6144, 11, 21, 19, 19, { + { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, + { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, + { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, + { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, + { 21, 22, -12 } + } + }, + /* 6BPP/14BPC */ + { 768, 15, 6144, 15, 25, 23, 23, { + { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, + { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, + { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, + { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, + { 25, 26, -12 } + } + }, + /* 6BPP/16BPC */ + { 768, 15, 6144, 19, 29, 27, 27, { + { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, + { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, + { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, + { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, + { 29, 30, -12 } + } + }, + }, + { + /* 8BPP/8BPC */ + { 512, 12, 6144, 3, 12, 11, 11, { + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + }, + /* 8BPP/10BPC */ + { 512, 12, 6144, 7, 16, 15, 15, { + /* + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however + * VESA DSC 1.1 Table E-5 sets it to 4. + */ + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + }, + /* 8BPP/12BPC */ + { 512, 12, 6144, 11, 20, 19, 19, { + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + }, + /* 8BPP/14BPC */ + { 512, 12, 6144, 15, 24, 23, 23, { + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, + { 24, 25, -12 } + } + }, + /* 8BPP/16BPC */ + { 512, 12, 6144, 19, 28, 27, 27, { + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, + { 28, 29, -12 } + } + }, + }, + { + /* 10BPP/8BPC */ + { 410, 15, 5632, 3, 12, 11, 11, { + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } + } + }, + /* 10BPP/10BPC */ + { 410, 15, 5632, 7, 16, 15, 15, { + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } + } + }, + /* 10BPP/12BPC */ + { 410, 15, 5632, 11, 20, 19, 19, { + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, + { 19, 20, -12 } + } + }, + /* 10BPP/14BPC */ + { 410, 15, 5632, 15, 24, 23, 23, { + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, + { 23, 24, -12 } + } + }, + /* 10BPP/16BPC */ + { 410, 15, 5632, 19, 28, 27, 27, { + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, + { 27, 28, -12 } + } + }, + }, + { + /* 12BPP/8BPC */ + { 341, 15, 2048, 3, 12, 11, 11, { + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + }, + /* 12BPP/10BPC */ + { 341, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + }, + /* 12BPP/12BPC */ + { 341, 15, 2048, 11, 20, 19, 19, { + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + }, + /* 12BPP/14BPC */ + { 341, 15, 2048, 15, 24, 23, 23, { + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, + { 22, 23, -12 } + } + }, + /* 12BPP/16BPC */ + { 341, 15, 2048, 19, 28, 27, 27, { + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, + { 26, 27, -12 } + } + }, + }, + { + /* 15BPP/8BPC */ + { 273, 15, 2048, 3, 12, 11, 11, { + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } + } + }, + /* 15BPP/10BPC */ + { 273, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } + } + }, + /* 15BPP/12BPC */ + { 273, 15, 2048, 11, 20, 19, 19, { + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, + { 16, 17, -12 } + } + }, + /* 15BPP/14BPC */ + { 273, 15, 2048, 15, 24, 23, 23, { + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, + { 20, 21, -12 } + } + }, + /* 15BPP/16BPC */ + { 273, 15, 2048, 19, 28, 27, 27, { + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, + { 24, 25, -12 } + } + } + } +}; + +static int get_row_index_for_rc_params(u16 compressed_bpp) +{ + switch (compressed_bpp) { + case 6: + return ROW_INDEX_6BPP; + case 8: + return ROW_INDEX_8BPP; + case 10: + return ROW_INDEX_10BPP; + case 12: + return ROW_INDEX_12BPP; + case 15: + return ROW_INDEX_15BPP; + default: + return -EINVAL; + } +} + +static int get_column_index_for_rc_params(u8 bits_per_component) +{ + switch (bits_per_component) { + case 8: + return COLUMN_INDEX_8BPC; + case 10: + return COLUMN_INDEX_10BPC; + case 12: + return COLUMN_INDEX_12BPC; + case 14: + return COLUMN_INDEX_14BPC; + case 16: + return COLUMN_INDEX_16BPC; + default: + return -EINVAL; + } +} + +static const struct rc_parameters *get_rc_params(u16 compressed_bpp, + u8 bits_per_component) +{ + int row_index, column_index; + + row_index = get_row_index_for_rc_params(compressed_bpp); + if (row_index < 0) + return NULL; + + column_index = get_column_index_for_rc_params(bits_per_component); + if (column_index < 0) + return NULL; + + return &rc_parameters[row_index][column_index]; +} + +/** + * drm_dsc_setup_rc_params() - Set parameters and limits for RC model in + * accordance with the DSC 1.1 or 1.2 specification and DSC C Model + * Required bits_per_pixel and bits_per_component to be set before calling this + * function. + * + * @vdsc_cfg: DSC Configuration data partially filled by driver + * + * Return: 0 or -error code in case of an error + */ +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg) +{ + const struct rc_parameters *rc_params; + int i; + + if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel || + !vdsc_cfg->bits_per_component)) + return -EINVAL; + + /* fractional BPP is not supported */ + if (vdsc_cfg->bits_per_pixel & 0xf) + return -EINVAL; + + rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4, + vdsc_cfg->bits_per_component); + if (!rc_params) + return -EINVAL; + + vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; + vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; + vdsc_cfg->initial_offset = rc_params->initial_offset; + vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; + vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; + vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; + vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; + + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + vdsc_cfg->rc_range_params[i].range_min_qp = + rc_params->rc_range_params[i].range_min_qp; + vdsc_cfg->rc_range_params[i].range_max_qp = + rc_params->rc_range_params[i].range_max_qp; + /* + * Range BPG Offset uses 2's complement and is only a 6 bits. So + * mask it to get only 6 bits. + */ + vdsc_cfg->rc_range_params[i].range_bpg_offset = + rc_params->rc_range_params[i].range_bpg_offset & + DSC_RANGE_BPG_OFFSET_MASK; + } + + return 0; +} +EXPORT_SYMBOL(drm_dsc_setup_rc_params); + /** * drm_dsc_compute_rc_parameters() - Write rate control * parameters to the dsc configuration defined in diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 2fd08375bbe3..d0536582e4b9 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -19,24 +19,6 @@ #include "intel_vdsc.h" #include "intel_vdsc_regs.h" -enum ROW_INDEX_BPP { - ROW_INDEX_6BPP = 0, - ROW_INDEX_8BPP, - ROW_INDEX_10BPP, - ROW_INDEX_12BPP, - ROW_INDEX_15BPP, - MAX_ROW_INDEX -}; - -enum COLUMN_INDEX_BPC { - COLUMN_INDEX_8BPC = 0, - COLUMN_INDEX_10BPC, - COLUMN_INDEX_12BPC, - COLUMN_INDEX_14BPC, - COLUMN_INDEX_16BPC, - MAX_COLUMN_INDEX -}; - struct rc_parameters { u16 initial_xmit_delay; u8 first_line_bpg_offset; @@ -48,296 +30,6 @@ struct rc_parameters { struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; }; -/* - * Selected Rate Control Related Parameter Recommended Values - * from DSC_v1.11 spec & C Model release: DSC_model_20161212 - */ -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { -{ - /* 6BPP/8BPC */ - { 768, 15, 6144, 3, 13, 11, 11, { - { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, - { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, - { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, - { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } - } - }, - /* 6BPP/10BPC */ - { 768, 15, 6144, 7, 17, 15, 15, { - { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, - { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, - { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, - { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, - { 17, 18, -12 } - } - }, - /* 6BPP/12BPC */ - { 768, 15, 6144, 11, 21, 19, 19, { - { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, - { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, - { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, - { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, - { 21, 22, -12 } - } - }, - /* 6BPP/14BPC */ - { 768, 15, 6144, 15, 25, 23, 23, { - { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, - { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, - { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, - { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, - { 25, 26, -12 } - } - }, - /* 6BPP/16BPC */ - { 768, 15, 6144, 19, 29, 27, 27, { - { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, - { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, - { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, - { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, - { 29, 30, -12 } - } - }, -}, -{ - /* 8BPP/8BPC */ - { 512, 12, 6144, 3, 12, 11, 11, { - { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } - } - }, - /* 8BPP/10BPC */ - { 512, 12, 6144, 7, 16, 15, 15, { - /* - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however - * VESA DSC 1.1 Table E-5 sets it to 4. - */ - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, - { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } - } - }, - /* 8BPP/12BPC */ - { 512, 12, 6144, 11, 20, 19, 19, { - { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, - { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, - { 21, 23, -12 } - } - }, - /* 8BPP/14BPC */ - { 512, 12, 6144, 15, 24, 23, 23, { - { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, - { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, - { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, - { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, - { 24, 25, -12 } - } - }, - /* 8BPP/16BPC */ - { 512, 12, 6144, 19, 28, 27, 27, { - { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, - { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, - { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, - { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, - { 28, 29, -12 } - } - }, -}, -{ - /* 10BPP/8BPC */ - { 410, 15, 5632, 3, 12, 11, 11, { - { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, - { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, - { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } - } - }, - /* 10BPP/10BPC */ - { 410, 15, 5632, 7, 16, 15, 15, { - { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, - { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, - { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, - { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } - } - }, - /* 10BPP/12BPC */ - { 410, 15, 5632, 11, 20, 19, 19, { - { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, - { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, - { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, - { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, - { 19, 20, -12 } - } - }, - /* 10BPP/14BPC */ - { 410, 15, 5632, 15, 24, 23, 23, { - { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, - { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, - { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, - { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, - { 23, 24, -12 } - } - }, - /* 10BPP/16BPC */ - { 410, 15, 5632, 19, 28, 27, 27, { - { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, - { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, - { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, - { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, - { 27, 28, -12 } - } - }, -}, -{ - /* 12BPP/8BPC */ - { 341, 15, 2048, 3, 12, 11, 11, { - { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } - } - }, - /* 12BPP/10BPC */ - { 341, 15, 2048, 7, 16, 15, 15, { - { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, - { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } - } - }, - /* 12BPP/12BPC */ - { 341, 15, 2048, 11, 20, 19, 19, { - { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, - { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, - { 21, 23, -12 } - } - }, - /* 12BPP/14BPC */ - { 341, 15, 2048, 15, 24, 23, 23, { - { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, - { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, - { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, - { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, - { 22, 23, -12 } - } - }, - /* 12BPP/16BPC */ - { 341, 15, 2048, 19, 28, 27, 27, { - { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, - { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, - { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, - { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, - { 26, 27, -12 } - } - }, -}, -{ - /* 15BPP/8BPC */ - { 273, 15, 2048, 3, 12, 11, 11, { - { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, - { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, - { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, - { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } - } - }, - /* 15BPP/10BPC */ - { 273, 15, 2048, 7, 16, 15, 15, { - { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, - { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, - { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, - { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } - } - }, - /* 15BPP/12BPC */ - { 273, 15, 2048, 11, 20, 19, 19, { - { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, - { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, - { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, - { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, - { 16, 17, -12 } - } - }, - /* 15BPP/14BPC */ - { 273, 15, 2048, 15, 24, 23, 23, { - { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, - { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, - { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, - { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, - { 20, 21, -12 } - } - }, - /* 15BPP/16BPC */ - { 273, 15, 2048, 19, 28, 27, 27, { - { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, - { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, - { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, - { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, - { 24, 25, -12 } - } - } -} - -}; - -static int get_row_index_for_rc_params(u16 compressed_bpp) -{ - switch (compressed_bpp) { - case 6: - return ROW_INDEX_6BPP; - case 8: - return ROW_INDEX_8BPP; - case 10: - return ROW_INDEX_10BPP; - case 12: - return ROW_INDEX_12BPP; - case 15: - return ROW_INDEX_15BPP; - default: - return -EINVAL; - } -} - -static int get_column_index_for_rc_params(u8 bits_per_component) -{ - switch (bits_per_component) { - case 8: - return COLUMN_INDEX_8BPC; - case 10: - return COLUMN_INDEX_10BPC; - case 12: - return COLUMN_INDEX_12BPC; - case 14: - return COLUMN_INDEX_14BPC; - case 16: - return COLUMN_INDEX_16BPC; - default: - return -EINVAL; - } -} - -static const struct rc_parameters *get_rc_params(u16 compressed_bpp, - u8 bits_per_component) -{ - int row_index, column_index; - - row_index = get_row_index_for_rc_params(compressed_bpp); - if (row_index < 0) - return NULL; - - column_index = get_column_index_for_rc_params(bits_per_component); - if (column_index < 0) - return NULL; - - return &rc_parameters[row_index][column_index]; -} - bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) { const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -479,6 +171,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) struct rc_parameters *rc = NULL; int err; u8 i = 0; + int ret; vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, @@ -552,10 +245,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) calculate_rc_params(rc, vdsc_cfg); rc_params = rc; } else { - rc_params = get_rc_params(compressed_bpp, - vdsc_cfg->bits_per_component); - if (!rc_params) - return -EINVAL; + ret = drm_dsc_setup_rc_params(vdsc_cfg); + if (ret) + return ret; + + goto out; } vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; @@ -594,6 +288,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->rc_range_params[0].range_bpg_offset = 0; } +out: /* * BitsPerComponent value determines mux_word_size: * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 706ba1d34742..1681791f65a5 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif /* _DRM_DSC_HELPER_H_ */ -- cgit v1.2.3 From e3290f883127159e3aa7957f30bd4266602d403e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 17 May 2023 13:28:05 +0300 Subject: drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters The array of rc_parameters contains a mixture of parameters from DSC 1.1 and DSC 1.2 standards. Split these tow configuration arrays in preparation to adding more configuration data. Signed-off-by: Dmitry Baryshkov Reviewed-by: Suraj Kandpal Reviewed-by: Suraj Kandpal Reviewed-by: Suraj Kandpal Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20230517102807.2181589-7-dmitry.baryshkov@linaro.org Acked-by: Dave Airlie --- drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++++++++++++++++++++++++------ drivers/gpu/drm/i915/display/intel_vdsc.c | 10 ++- include/drm/display/drm_dsc_helper.h | 7 +- 3 files changed, 129 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index acb93d4116e0..f1ba39df5708 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -325,10 +325,88 @@ struct rc_parameters_data { #define DSC_BPP(bpp) ((bpp) << 4) /* - * Selected Rate Control Related Parameter Recommended Values - * from DSC_v1.11 spec & C Model release: DSC_model_20161212 + * Rate Control Related Parameter Recommended Values from DSC_v1.1 spec prior + * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf) + * + * Cross-checked against C Model releases: DSC_model_20161212 and 20210623 */ -static const struct rc_parameters_data rc_parameters[] = { +static const struct rc_parameters_data rc_parameters_pre_scr[] = { + { + .bpp = DSC_BPP(8), .bpc = 8, + { 512, 12, 6144, 3, 12, 11, 11, { + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 10, + { 512, 12, 6144, 7, 16, 15, 15, { + /* + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however + * VESA DSC 1.1 Table E-5 sets it to 4. + */ + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 12, + { 512, 12, 6144, 11, 20, 19, 19, { + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + } + }, + { + .bpp = DSC_BPP(12), .bpc = 8, + { 341, 15, 2048, 3, 12, 11, 11, { + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + } + }, + { + .bpp = DSC_BPP(12), .bpc = 10, + { 341, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + } + }, + { + .bpp = DSC_BPP(12), .bpc = 12, + { 341, 15, 2048, 11, 20, 19, 19, { + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + } + }, + { /* sentinel */ } +}; + +/* + * Selected Rate Control Related Parameter Recommended Values from DSC v1.2, v1.2a, v1.2b and + * DSC_v1.1_E1 specs. + * + * Cross-checked against C Model releases: DSC_model_20161212 and 20210623 + */ +static const struct rc_parameters_data rc_parameters_1_2_444[] = { { .bpp = DSC_BPP(6), .bpc = 8, { 768, 15, 6144, 3, 13, 11, 11, { @@ -388,22 +466,18 @@ static const struct rc_parameters_data rc_parameters[] = { { 512, 12, 6144, 3, 12, 11, 11, { { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 }, + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 } } } }, { .bpp = DSC_BPP(8), .bpc = 10, { 512, 12, 6144, 7, 16, 15, 15, { - /* - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however - * VESA DSC 1.1 Table E-5 sets it to 4. - */ - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 }, + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 } } } }, @@ -412,9 +486,9 @@ static const struct rc_parameters_data rc_parameters[] = { { 512, 12, 6144, 11, 20, 19, 19, { { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, - { 21, 23, -12 } + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 }, + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 }, + { 20, 21, -12 } } } }, @@ -498,8 +572,8 @@ static const struct rc_parameters_data rc_parameters[] = { { 341, 15, 2048, 3, 12, 11, 11, { { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 }, + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 } } } }, @@ -508,8 +582,8 @@ static const struct rc_parameters_data rc_parameters[] = { { 341, 15, 2048, 7, 16, 15, 15, { { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 }, + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 } } } }, @@ -518,9 +592,9 @@ static const struct rc_parameters_data rc_parameters[] = { { 341, 15, 2048, 11, 20, 19, 19, { { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, - { 21, 23, -12 } + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 }, + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 }, + { 18, 19, -12 } } } }, @@ -602,7 +676,8 @@ static const struct rc_parameters_data rc_parameters[] = { { /* sentinel */ } }; -static const struct rc_parameters *get_rc_params(u16 dsc_bpp, +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters, + u16 dsc_bpp, u8 bits_per_component) { int i; @@ -622,11 +697,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp, * function. * * @vdsc_cfg: DSC Configuration data partially filled by driver + * @type: operating mode and standard to follow * * Return: 0 or -error code in case of an error */ -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg) +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type) { + const struct rc_parameters_data *data; const struct rc_parameters *rc_params; int i; @@ -634,7 +711,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg) !vdsc_cfg->bits_per_component)) return -EINVAL; - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel, + switch (type) { + case DRM_DSC_1_2_444: + data = rc_parameters_1_2_444; + break; + case DRM_DSC_1_1_PRE_SCR: + data = rc_parameters_pre_scr; + break; + default: + return -EINVAL; + } + + rc_params = get_rc_params(data, + vdsc_cfg->bits_per_pixel, vdsc_cfg->bits_per_component); if (!rc_params) return -EINVAL; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index d4340b18c18d..bd9116d2cd76 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -226,7 +226,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) if (DISPLAY_VER(dev_priv) >= 13) { calculate_rc_params(vdsc_cfg); } else { - ret = drm_dsc_setup_rc_params(vdsc_cfg); + if ((compressed_bpp == 8 || + compressed_bpp == 12) && + (vdsc_cfg->bits_per_component == 8 || + vdsc_cfg->bits_per_component == 10 || + vdsc_cfg->bits_per_component == 12)) + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR); + else + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444); + if (ret) return ret; diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 1681791f65a5..66eac7276d04 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -10,12 +10,17 @@ #include +enum drm_dsc_params_type { + DRM_DSC_1_2_444, + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */ +}; + void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg); +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif /* _DRM_DSC_HELPER_H_ */ -- cgit v1.2.3 From d54fbea3bbbe04cdc944db94eb11c8bda30438b8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 17 May 2023 13:28:07 +0300 Subject: drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations. Reviewed-by: Suraj Kandpal Signed-off-by: Dmitry Baryshkov Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20230517102807.2181589-9-dmitry.baryshkov@linaro.org Acked-by: Dave Airlie --- drivers/gpu/drm/display/drm_dsc_helper.c | 450 +++++++++++++++++++++++++++++++ include/drm/display/drm_dsc_helper.h | 2 + 2 files changed, 452 insertions(+) (limited to 'include') diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index f6d8a7be5967..fc187a8d8873 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -748,6 +748,450 @@ static const struct rc_parameters_data rc_parameters_1_2_444[] = { { /* sentinel */ } }; +/* + * Selected Rate Control Related Parameter Recommended Values for 4:2:2 from + * DSC v1.2, v1.2a, v1.2b + * + * Cross-checked against C Model releases: DSC_model_20161212 and 20210623 + */ +static const struct rc_parameters_data rc_parameters_1_2_422[] = { + { + .bpp = DSC_BPP(6), .bpc = 8, + { 512, 15, 6144, 3, 12, 11, 11, { + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 }, + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 10, + { 512, 15, 6144, 7, 16, 15, 15, { + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 }, + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 12, + { 512, 15, 6144, 11, 20, 19, 19, { + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 }, + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 }, + { 20, 21, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 14, + { 512, 15, 6144, 15, 24, 23, 23, { + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, + { 24, 25, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 16, + { 512, 15, 6144, 19, 28, 27, 27, { + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, + { 28, 29, -12 } + } + } + }, + { + .bpp = DSC_BPP(7), .bpc = 8, + { 410, 15, 5632, 3, 12, 11, 11, { + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } + } + } + }, + { + .bpp = DSC_BPP(7), .bpc = 10, + { 410, 15, 5632, 7, 16, 15, 15, { + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } + } + } + }, + { + .bpp = DSC_BPP(7), .bpc = 12, + { 410, 15, 5632, 11, 20, 19, 19, { + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, + { 19, 20, -12 } + } + } + }, + { + .bpp = DSC_BPP(7), .bpc = 14, + { 410, 15, 5632, 15, 24, 23, 23, { + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, + { 23, 24, -12 } + } + } + }, + { + .bpp = DSC_BPP(7), .bpc = 16, + { 410, 15, 5632, 19, 28, 27, 27, { + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, + { 27, 28, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 8, + { 341, 15, 2048, 3, 12, 11, 11, { + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 }, + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 10, + { 341, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 }, + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 12, + { 341, 15, 2048, 11, 20, 19, 19, { + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 }, + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 }, + { 18, 19, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 14, + { 341, 15, 2048, 15, 24, 23, 23, { + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, + { 22, 23, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 16, + { 341, 15, 2048, 19, 28, 27, 27, { + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, + { 26, 27, -12 } + } + } + }, + { + .bpp = DSC_BPP(10), .bpc = 8, + { 273, 15, 2048, 3, 12, 11, 11, { + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } + } + } + }, + { + .bpp = DSC_BPP(10), .bpc = 10, + { 273, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } + } + } + }, + { + .bpp = DSC_BPP(10), .bpc = 12, + { 273, 15, 2048, 11, 20, 19, 19, { + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, + { 16, 17, -12 } + } + } + }, + { + .bpp = DSC_BPP(10), .bpc = 14, + { 273, 15, 2048, 15, 24, 23, 23, { + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, + { 20, 21, -12 } + } + } + }, + { + .bpp = DSC_BPP(10), .bpc = 16, + { 273, 15, 2048, 19, 28, 27, 27, { + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, + { 24, 25, -12 } + } + } + }, + { /* sentinel */ } +}; + +/* + * Selected Rate Control Related Parameter Recommended Values for 4:2:2 from + * DSC v1.2, v1.2a, v1.2b + * + * Cross-checked against C Model releases: DSC_model_20161212 and 20210623 + */ +static const struct rc_parameters_data rc_parameters_1_2_420[] = { + { + .bpp = DSC_BPP(4), .bpc = 8, + { 512, 12, 6144, 3, 12, 11, 11, { + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 }, + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 } + } + } + }, + { + .bpp = DSC_BPP(4), .bpc = 10, + { 512, 12, 6144, 7, 16, 15, 15, { + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 }, + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 } + } + } + }, + { + .bpp = DSC_BPP(4), .bpc = 12, + { 512, 12, 6144, 11, 20, 19, 19, { + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 }, + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 }, + { 20, 21, -12 } + } + } + }, + { + .bpp = DSC_BPP(4), .bpc = 14, + { 512, 12, 6144, 15, 24, 23, 23, { + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, + { 24, 25, -12 } + } + } + }, + { + .bpp = DSC_BPP(4), .bpc = 16, + { 512, 12, 6144, 19, 28, 27, 27, { + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, + { 28, 29, -12 } + } + } + }, + { + .bpp = DSC_BPP(5), .bpc = 8, + { 410, 15, 5632, 3, 12, 11, 11, { + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } + } + } + }, + { + .bpp = DSC_BPP(5), .bpc = 10, + { 410, 15, 5632, 7, 16, 15, 15, { + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } + } + } + }, + { + .bpp = DSC_BPP(5), .bpc = 12, + { 410, 15, 5632, 11, 20, 19, 19, { + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, + { 19, 20, -12 } + } + } + }, + { + .bpp = DSC_BPP(5), .bpc = 14, + { 410, 15, 5632, 15, 24, 23, 23, { + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, + { 23, 24, -12 } + } + } + }, + { + .bpp = DSC_BPP(5), .bpc = 16, + { 410, 15, 5632, 19, 28, 27, 27, { + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, + { 27, 28, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 8, + { 341, 15, 2048, 3, 12, 11, 11, { + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 }, + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 10, + { 341, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 }, + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 12, + { 341, 15, 2048, 11, 20, 19, 19, { + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 }, + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 }, + { 18, 19, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 14, + { 341, 15, 2048, 15, 24, 23, 23, { + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, + { 22, 23, -12 } + } + } + }, + { + .bpp = DSC_BPP(6), .bpc = 16, + { 341, 15, 2048, 19, 28, 27, 27, { + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, + { 26, 27, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 8, + { 256, 15, 2048, 3, 12, 11, 11, { + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 10, + { 256, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 12, + { 256, 15, 2048, 11, 20, 19, 19, { + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, + { 16, 17, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 14, + { 256, 15, 2048, 15, 24, 23, 23, { + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, + { 20, 21, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 16, + { 256, 15, 2048, 19, 28, 27, 27, { + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, + { 24, 25, -12 } + } + } + }, + { /* sentinel */ } +}; + static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters, u16 dsc_bpp, u8 bits_per_component) @@ -790,6 +1234,12 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params case DRM_DSC_1_1_PRE_SCR: data = rc_parameters_pre_scr; break; + case DRM_DSC_1_2_422: + data = rc_parameters_1_2_422; + break; + case DRM_DSC_1_2_420: + data = rc_parameters_1_2_420; + break; default: return -EINVAL; } diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 66eac7276d04..fc2104415dcb 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -13,6 +13,8 @@ enum drm_dsc_params_type { DRM_DSC_1_2_444, DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */ + DRM_DSC_1_2_422, + DRM_DSC_1_2_420, }; void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); -- cgit v1.2.3 From 5c8ec987997ab444df18813e0a3f565f366d05d1 Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Mon, 29 May 2023 16:37:39 +0530 Subject: drm/i915/hdcp: Move away from master naming to arbiter Rename variables to move away from master convention to arbiter %s/hdcp.master/hdcp.arbiter %s/i915_hdcp_master/i915_hdcp_arbiter %s/comp_master/comp_arbiter --v2 - delete i915_hdcp_comp_master redundant declaration [Chaitanya] - use %s/foo/bar/ format in commit message to show changes [Chaitanya] --v3 - replace i915_hdcp_comp_master declaration with i915_hdcp_arbiter to avoid any compile fail with old compilers [Chaitanya] Cc: Chaitanya Kumar Borah Cc: Ankit Nautiyal Cc: Jani Nikula Signed-off-by: Suraj Kandpal Reviewed-by: Chaitanya Kumar Borah Signed-off-by: Ankit Nautiyal Link: https://patchwork.freedesktop.org/patch/msgid/20230529110740.1522985-3-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_display_core.h | 4 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 52 +++++++++++------------ drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 12 +++--- drivers/misc/mei/hdcp/mei_hdcp.c | 26 ++++++------ include/drm/i915_hdcp_interface.h | 4 +- 5 files changed, 49 insertions(+), 49 deletions(-) (limited to 'include') diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index e36f88a39b86..23957d80efe8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -30,7 +30,7 @@ struct drm_i915_private; struct drm_property; struct drm_property_blob; struct i915_audio_component; -struct i915_hdcp_comp_master; +struct i915_hdcp_arbiter; struct intel_atomic_state; struct intel_audio_funcs; struct intel_bios_encoder_data; @@ -395,7 +395,7 @@ struct intel_display { } gmbus; struct { - struct i915_hdcp_master *master; + struct i915_hdcp_arbiter *arbiter; bool comp_added; /* diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index e2e5527efc4b..bf28c6f1d748 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -183,7 +183,7 @@ bool intel_hdcp2_capable(struct intel_connector *connector) /* MEI/GSC interface is solid depending on which is used */ mutex_lock(&i915->display.hdcp.comp_mutex); - if (!i915->display.hdcp.comp_added || !i915->display.hdcp.master) { + if (!i915->display.hdcp.comp_added || !i915->display.hdcp.arbiter) { mutex_unlock(&i915->display.hdcp.comp_mutex); return false; } @@ -1114,11 +1114,11 @@ hdcp2_prepare_ake_init(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1144,11 +1144,11 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1172,11 +1172,11 @@ static int hdcp2_verify_hprime(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1198,11 +1198,11 @@ hdcp2_store_pairing_info(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1225,11 +1225,11 @@ hdcp2_prepare_lc_init(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1252,11 +1252,11 @@ hdcp2_verify_lprime(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1278,11 +1278,11 @@ static int hdcp2_prepare_skey(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1307,11 +1307,11 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1337,11 +1337,11 @@ hdcp2_verify_mprime(struct intel_connector *connector, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1361,11 +1361,11 @@ static int hdcp2_authenticate_port(struct intel_connector *connector) struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct hdcp_port_data *data = &dig_port->hdcp_port_data; struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -1385,11 +1385,11 @@ static int hdcp2_close_session(struct intel_connector *connector) { struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct i915_hdcp_master *arbiter; + struct i915_hdcp_arbiter *arbiter; int ret; mutex_lock(&i915->display.hdcp.comp_mutex); - arbiter = i915->display.hdcp.master; + arbiter = i915->display.hdcp.arbiter; if (!arbiter || !arbiter->ops) { mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -2109,8 +2109,8 @@ static int i915_hdcp_component_bind(struct device *i915_kdev, drm_dbg(&i915->drm, "I915 HDCP comp bind\n"); mutex_lock(&i915->display.hdcp.comp_mutex); - i915->display.hdcp.master = (struct i915_hdcp_master *)data; - i915->display.hdcp.master->hdcp_dev = mei_kdev; + i915->display.hdcp.arbiter = (struct i915_hdcp_arbiter *)data; + i915->display.hdcp.arbiter->hdcp_dev = mei_kdev; mutex_unlock(&i915->display.hdcp.comp_mutex); return 0; @@ -2123,7 +2123,7 @@ static void i915_hdcp_component_unbind(struct device *i915_kdev, drm_dbg(&i915->drm, "I915 HDCP comp unbind\n"); mutex_lock(&i915->display.hdcp.comp_mutex); - i915->display.hdcp.master = NULL; + i915->display.hdcp.arbiter = NULL; mutex_unlock(&i915->display.hdcp.comp_mutex); } diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c index 4056bb2323ca..62e7bf0e1035 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c @@ -697,17 +697,17 @@ static void intel_hdcp_gsc_free_message(struct drm_i915_private *i915) int intel_hdcp_gsc_init(struct drm_i915_private *i915) { - struct i915_hdcp_master *data; + struct i915_hdcp_arbiter *data; int ret; - data = kzalloc(sizeof(struct i915_hdcp_master), GFP_KERNEL); + data = kzalloc(sizeof(struct i915_hdcp_arbiter), GFP_KERNEL); if (!data) return -ENOMEM; mutex_lock(&i915->display.hdcp.comp_mutex); - i915->display.hdcp.master = data; - i915->display.hdcp.master->hdcp_dev = i915->drm.dev; - i915->display.hdcp.master->ops = &gsc_hdcp_ops; + i915->display.hdcp.arbiter = data; + i915->display.hdcp.arbiter->hdcp_dev = i915->drm.dev; + i915->display.hdcp.arbiter->ops = &gsc_hdcp_ops; ret = intel_hdcp_gsc_hdcp2_init(i915); mutex_unlock(&i915->display.hdcp.comp_mutex); @@ -717,7 +717,7 @@ int intel_hdcp_gsc_init(struct drm_i915_private *i915) void intel_hdcp_gsc_fini(struct drm_i915_private *i915) { intel_hdcp_gsc_free_message(i915); - kfree(i915->display.hdcp.master); + kfree(i915->display.hdcp.arbiter); } static int intel_gsc_send_sync(struct drm_i915_private *i915, diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c index 85cbfc3413ee..51359cc5ece9 100644 --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -735,13 +735,13 @@ static const struct i915_hdcp_ops mei_hdcp_ops = { static int mei_component_master_bind(struct device *dev) { struct mei_cl_device *cldev = to_mei_cl_device(dev); - struct i915_hdcp_master *comp_master = mei_cldev_get_drvdata(cldev); + struct i915_hdcp_arbiter *comp_arbiter = mei_cldev_get_drvdata(cldev); int ret; dev_dbg(dev, "%s\n", __func__); - comp_master->ops = &mei_hdcp_ops; - comp_master->hdcp_dev = dev; - ret = component_bind_all(dev, comp_master); + comp_arbiter->ops = &mei_hdcp_ops; + comp_arbiter->hdcp_dev = dev; + ret = component_bind_all(dev, comp_arbiter); if (ret < 0) return ret; @@ -751,10 +751,10 @@ static int mei_component_master_bind(struct device *dev) static void mei_component_master_unbind(struct device *dev) { struct mei_cl_device *cldev = to_mei_cl_device(dev); - struct i915_hdcp_master *comp_master = mei_cldev_get_drvdata(cldev); + struct i915_hdcp_arbiter *comp_arbiter = mei_cldev_get_drvdata(cldev); dev_dbg(dev, "%s\n", __func__); - component_unbind_all(dev, comp_master); + component_unbind_all(dev, comp_arbiter); } static const struct component_master_ops mei_component_master_ops = { @@ -799,7 +799,7 @@ static int mei_hdcp_component_match(struct device *dev, int subcomponent, static int mei_hdcp_probe(struct mei_cl_device *cldev, const struct mei_cl_device_id *id) { - struct i915_hdcp_master *comp_master; + struct i915_hdcp_arbiter *comp_arbiter; struct component_match *master_match; int ret; @@ -809,8 +809,8 @@ static int mei_hdcp_probe(struct mei_cl_device *cldev, goto enable_err_exit; } - comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL); - if (!comp_master) { + comp_arbiter = kzalloc(sizeof(*comp_arbiter), GFP_KERNEL); + if (!comp_arbiter) { ret = -ENOMEM; goto err_exit; } @@ -823,7 +823,7 @@ static int mei_hdcp_probe(struct mei_cl_device *cldev, goto err_exit; } - mei_cldev_set_drvdata(cldev, comp_master); + mei_cldev_set_drvdata(cldev, comp_arbiter); ret = component_master_add_with_match(&cldev->dev, &mei_component_master_ops, master_match); @@ -836,7 +836,7 @@ static int mei_hdcp_probe(struct mei_cl_device *cldev, err_exit: mei_cldev_set_drvdata(cldev, NULL); - kfree(comp_master); + kfree(comp_arbiter); mei_cldev_disable(cldev); enable_err_exit: return ret; @@ -844,11 +844,11 @@ enable_err_exit: static void mei_hdcp_remove(struct mei_cl_device *cldev) { - struct i915_hdcp_master *comp_master = mei_cldev_get_drvdata(cldev); + struct i915_hdcp_arbiter *comp_arbiter = mei_cldev_get_drvdata(cldev); int ret; component_master_del(&cldev->dev, &mei_component_master_ops); - kfree(comp_master); + kfree(comp_arbiter); mei_cldev_set_drvdata(cldev, NULL); ret = mei_cldev_disable(cldev); diff --git a/include/drm/i915_hdcp_interface.h b/include/drm/i915_hdcp_interface.h index 2059b066f8a1..4c9c8167c2d5 100644 --- a/include/drm/i915_hdcp_interface.h +++ b/include/drm/i915_hdcp_interface.h @@ -168,12 +168,12 @@ struct i915_hdcp_ops { }; /** - * struct i915_hdcp_master - Used for communication between i915 + * struct i915_hdcp_arbiter - Used for communication between i915 * and hdcp drivers for the HDCP2.2 services * @hdcp_dev: device that provide the HDCP2.2 service from MEI Bus. * @hdcp_ops: Ops implemented by hdcp driver or intel_hdcp_gsc , used by i915 driver. */ -struct i915_hdcp_master { +struct i915_hdcp_arbiter { struct device *hdcp_dev; const struct i915_hdcp_ops *ops; -- cgit v1.2.3 From 0374ffa507d8106202a956f5951226f1d9eac22e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 May 2023 12:08:13 +0300 Subject: drm/edid: parse display info has_audio similar to is_hdmi Since we already iterate everything that's needed for determining audio, reduce the need to call drm_detect_monitor_audio() by storing has_audio to connector info. Reviewed-by: Ankit Nautiyal Acked-by: Thomas Zimmermann Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/391a93b25c6bcbb39854aaa2813570cfb1580ed9.1685437500.git.jani.nikula@intel.com --- drivers/gpu/drm/drm_edid.c | 6 ++++++ include/drm/drm_connector.h | 8 ++++++++ 2 files changed, 14 insertions(+) (limited to 'include') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 0454da505687..813ce00a106a 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -6243,6 +6243,9 @@ static void drm_parse_cea_ext(struct drm_connector *connector, info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; if (edid_ext[3] & EDID_CEA_YCRCB422) info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; + if (edid_ext[3] & EDID_BASIC_AUDIO) + info->has_audio = true; + } drm_edid_iter_end(&edid_iter); @@ -6268,6 +6271,8 @@ static void drm_parse_cea_ext(struct drm_connector *connector, drm_parse_hdr_metadata_block(connector, data); else if (cea_db_tag(db) == CTA_DB_VIDEO) parse_cta_vdb(connector, db); + else if (cea_db_tag(db) == CTA_DB_AUDIO) + info->has_audio = true; } cea_db_iter_end(&iter); @@ -6424,6 +6429,7 @@ static void drm_reset_display_info(struct drm_connector *connector) info->max_tmds_clock = 0; info->dvi_dual = false; info->is_hdmi = false; + info->has_audio = false; info->has_hdmi_infoframe = false; info->rgb_quant_range_selectable = false; memset(&info->hdmi, 0, sizeof(info->hdmi)); diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index e6478fafa6b0..e143fef07de9 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -658,6 +658,14 @@ struct drm_display_info { */ bool is_hdmi; + /** + * @has_audio: True if the sink supports audio. + * + * This field shall be used instead of calling + * drm_detect_monitor_audio() when possible. + */ + bool has_audio; + /** * @has_hdmi_infoframe: Does the sink support the HDMI infoframe? */ -- cgit v1.2.3 From 3d35ddfb07136cb4220fd9672589dcdf5c9d4acf Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 May 2023 12:08:14 +0300 Subject: drm/display/dp_mst: drop has_audio from struct drm_dp_mst_port Caching the has_audio in struct drm_dp_mst_port seems odd, and oddly placed. Defer audio handling to drivers, and use the info from the connector display info. i915 was the only one using it anyway. Reviewed-by: Ankit Nautiyal Acked-by: Thomas Zimmermann Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/7d9eefdf150870479c5797f027d4c2b0a19ff583.1685437500.git.jani.nikula@intel.com --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 2 +- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- include/drm/display/drm_dp_mst_helper.h | 5 ----- 4 files changed, 4 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 38dab76ae69e..a2b8732db0c8 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -4170,7 +4170,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_ else { edid = drm_get_edid(connector, &port->aux.ddc); } - port->has_audio = drm_detect_monitor_audio(edid); + drm_dp_mst_topology_put_port(port); return edid; } diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index e72288662f02..77caed2552d0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -244,9 +244,9 @@ static void intel_dp_info(struct seq_file *m, } static void intel_dp_mst_info(struct seq_file *m, - struct intel_connector *intel_connector) + struct intel_connector *connector) { - bool has_audio = intel_connector->port->has_audio; + bool has_audio = connector->base.display_info.has_audio; seq_printf(m, "\taudio support: %s\n", str_yes_no(has_audio)); } diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 6df8519b3347..1d483a83d59c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -298,7 +298,7 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state) to_intel_connector(conn_state->connector); if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) - return connector->port->has_audio; + return connector->base.display_info.has_audio; else return intel_conn_state->force_audio == HDMI_AUDIO_ON; } diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index 32c764fb9cb5..5be96a158ab2 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -139,11 +139,6 @@ struct drm_dp_mst_port { * that the EDID for all connectors is read immediately. */ struct edid *cached_edid; - /** - * @has_audio: Tracks whether the sink connector to this port is - * audio-capable. - */ - bool has_audio; /** * @fec_capable: bool indicating if FEC can be supported up to that -- cgit v1.2.3 From 6c46f644cd5aa5b2b18020bef83d67101a98d873 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 May 2023 12:08:21 +0300 Subject: drm/edid: add drm_edid_read_switcheroo() Add a switcheroo variant to the struct drm_edid based EDID read functions. Reviewed-by: Ankit Nautiyal Acked-by: Thomas Zimmermann Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/4ab5ec994670ea50f95c8079c1f1ae915940b00f.1685437501.git.jani.nikula@intel.com --- drivers/gpu/drm/drm_edid.c | 29 +++++++++++++++++++++++++++++ include/drm/drm_edid.h | 2 ++ 2 files changed, 31 insertions(+) (limited to 'include') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 813ce00a106a..941f3d53a701 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2844,6 +2844,35 @@ struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, } EXPORT_SYMBOL(drm_get_edid_switcheroo); +/** + * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output + * @connector: connector we're probing + * @adapter: I2C adapter to use for DDC + * + * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set + * of outputs. The wrapper adds the requisite vga_switcheroo calls to + * temporarily switch DDC to the GPU which is retrieving EDID. + * + * Return: Pointer to valid EDID or %NULL if we couldn't find any. + */ +const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, + struct i2c_adapter *adapter) +{ + struct drm_device *dev = connector->dev; + struct pci_dev *pdev = to_pci_dev(dev->dev); + const struct drm_edid *drm_edid; + + if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) + return NULL; + + vga_switcheroo_lock_ddc(pdev); + drm_edid = drm_edid_read_ddc(connector, adapter); + vga_switcheroo_unlock_ddc(pdev); + + return drm_edid; +} +EXPORT_SYMBOL(drm_edid_read_switcheroo); + /** * drm_edid_duplicate - duplicate an EDID and the extensions * @edid: EDID to duplicate diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 571885d32907..169755d3de19 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -613,6 +613,8 @@ const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len), void *context); +const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, + struct i2c_adapter *adapter); int drm_edid_connector_update(struct drm_connector *connector, const struct drm_edid *edid); int drm_edid_connector_add_modes(struct drm_connector *connector); -- cgit v1.2.3 From c1c9042b20031aa4f86f60bba8f04e304bb9f72a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 May 2023 12:08:24 +0300 Subject: drm/display/dp_mst: convert to struct drm_edid Convert the topology manager to use struct drm_edid, add drm_dp_mst_edid_read() that returns drm_edid, and rewrite the old drm_dp_mst_get_edid() to use it. Note that the old drm_get_edid() ended up calling drm_connector_update_edid_property(). This responsibility is now deferred to drivers, which all do it anyway after calling drm_dp_mst_edid_read() or drm_dp_mst_get_edid(). Reviewed-by: Ankit Nautiyal Acked-by: Thomas Zimmermann Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/9c32e5c241934093fc4144eed4c01155e1f03af1.1685437501.git.jani.nikula@intel.com --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 53 +++++++++++++++++++++------ include/drm/display/drm_dp_mst_helper.h | 9 ++++- 2 files changed, 49 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index a2b8732db0c8..be71be95b706 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -1823,7 +1823,7 @@ static void drm_dp_destroy_port(struct kref *kref) return; } - kfree(port->cached_edid); + drm_edid_free(port->cached_edid); /* * we can't destroy the connector here, as we might be holding the @@ -2272,8 +2272,8 @@ drm_dp_mst_port_add_connector(struct drm_dp_mst_branch *mstb, if (port->pdt != DP_PEER_DEVICE_NONE && drm_dp_mst_is_end_device(port->pdt, port->mcs) && port->port_num >= DP_MST_LOGICAL_PORT_0) - port->cached_edid = drm_get_edid(port->connector, - &port->aux.ddc); + port->cached_edid = drm_edid_read_ddc(port->connector, + &port->aux.ddc); drm_connector_register(port->connector); return; @@ -4133,7 +4133,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector, ret = connector_status_connected; /* for logical ports - cache the EDID */ if (port->port_num >= DP_MST_LOGICAL_PORT_0 && !port->cached_edid) - port->cached_edid = drm_get_edid(connector, &port->aux.ddc); + port->cached_edid = drm_edid_read_ddc(connector, &port->aux.ddc); break; case DP_PEER_DEVICE_DP_LEGACY_CONV: if (port->ldps) @@ -4147,7 +4147,7 @@ out: EXPORT_SYMBOL(drm_dp_mst_detect_port); /** - * drm_dp_mst_get_edid() - get EDID for an MST port + * drm_dp_mst_edid_read() - get EDID for an MST port * @connector: toplevel connector to get EDID for * @mgr: manager for this port * @port: unverified pointer to a port. @@ -4156,9 +4156,11 @@ EXPORT_SYMBOL(drm_dp_mst_detect_port); * It validates the pointer still exists so the caller doesn't require a * reference. */ -struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port) +const struct drm_edid *drm_dp_mst_edid_read(struct drm_connector *connector, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port) { - struct edid *edid = NULL; + const struct drm_edid *drm_edid; /* we need to search for the port in the mgr in case it's gone */ port = drm_dp_mst_topology_get_port_validated(mgr, port); @@ -4166,12 +4168,41 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_ return NULL; if (port->cached_edid) - edid = drm_edid_duplicate(port->cached_edid); - else { - edid = drm_get_edid(connector, &port->aux.ddc); - } + drm_edid = drm_edid_dup(port->cached_edid); + else + drm_edid = drm_edid_read_ddc(connector, &port->aux.ddc); drm_dp_mst_topology_put_port(port); + + return drm_edid; +} +EXPORT_SYMBOL(drm_dp_mst_edid_read); + +/** + * drm_dp_mst_get_edid() - get EDID for an MST port + * @connector: toplevel connector to get EDID for + * @mgr: manager for this port + * @port: unverified pointer to a port. + * + * This function is deprecated; please use drm_dp_mst_edid_read() instead. + * + * This returns an EDID for the port connected to a connector, + * It validates the pointer still exists so the caller doesn't require a + * reference. + */ +struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port) +{ + const struct drm_edid *drm_edid; + struct edid *edid; + + drm_edid = drm_dp_mst_edid_read(connector, mgr, port); + + edid = drm_edid_duplicate(drm_edid_raw(drm_edid)); + + drm_edid_free(drm_edid); + return edid; } EXPORT_SYMBOL(drm_dp_mst_get_edid); diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index 5be96a158ab2..f962e97880b4 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -138,7 +138,7 @@ struct drm_dp_mst_port { * @cached_edid: for DP logical ports - make tiling work by ensuring * that the EDID for all connectors is read immediately. */ - struct edid *cached_edid; + const struct drm_edid *cached_edid; /** * @fec_capable: bool indicating if FEC can be supported up to that @@ -819,7 +819,12 @@ drm_dp_mst_detect_port(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); -struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); +const struct drm_edid *drm_dp_mst_edid_read(struct drm_connector *connector, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port); +struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port); int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, int link_rate, int link_lane_count); -- cgit v1.2.3 From e788ff7ee3b4b7b8ae534e605154f50dc4443a40 Mon Sep 17 00:00:00 2001 From: Sui Jingfeng Date: Mon, 29 May 2023 19:29:56 +0800 Subject: drm/i915_drm.h: fix a typo 'rbiter' -> 'arbiter' Signed-off-by: Sui Jingfeng Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20230529112956.2083389-1-suijingfeng@loongson.cn --- include/drm/i915_drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 7adce327c1c2..adff68538484 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -42,7 +42,7 @@ extern struct resource intel_graphics_stolen_res; * The Bridge device's PCI config space has information about the * fb aperture size and the amount of pre-reserved memory. * This is all handled in the intel-gtt.ko module. i915.ko only - * cares about the vga bit for the vga rbiter. + * cares about the vga bit for the vga arbiter. */ #define INTEL_GMCH_CTRL 0x52 #define INTEL_GMCH_VGA_DISABLE (1 << 1) -- cgit v1.2.3