1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
|
Marvell Distributed Switch Architecture Device Tree Bindings
------------------------------------------------------------
Required properties:
- compatible : Should be "marvell,dsa"
- #address-cells : Must be 2, first cell is the address on the MDIO bus
and second cell is the address in the switch tree.
Second cell is used only when cascading/chaining.
- #size-cells : Must be 0
- dsa,ethernet : Should be a phandle to a valid Ethernet device node
- dsa,mii-bus : Should be a phandle to a valid MDIO bus device node
Optional properties:
- interrupts : property with a value describing the switch
interrupt number (not supported by the driver)
A DSA node can contain multiple switch chips which are therefore child nodes of
the parent DSA node. The maximum number of allowed child nodes is 4
(DSA_MAX_SWITCHES).
Each of these switch child nodes should have the following required properties:
- reg : Contains two fields. The first one describes the
address on the MII bus. The second is the switch
number that must be unique in cascaded configurations
- #address-cells : Must be 1
- #size-cells : Must be 0
A switch child node has the following optional property:
- eeprom-length : Set to the length of an EEPROM connected to the
switch. Must be set if the switch can not detect
the presence and/or size of a connected EEPROM,
otherwise optional.
A switch may have multiple "port" children nodes
Each port children node must have the following mandatory properties:
- reg : Describes the port address in the switch
- label : Describes the label associated with this port, special
labels are "cpu" to indicate a CPU port and "dsa" to
indicate an uplink/downlink port.
Note that a port labelled "dsa" will imply checking for the uplink phandle
described below.
Optionnal property:
- link : Should be a list of phandles to another switch's DSA port.
This property is only used when switches are being
chained/cascaded together. This port is used as outgoing port
towards the phandle port, which can be more than one hop away.
- phy-handle : Phandle to a PHY on an external MDIO bus, not the
switch internal one. See
Documentation/devicetree/bindings/net/ethernet.txt
for details.
- phy-mode : String representing the connection to the designated
PHY node specified by the 'phy-handle' property. See
Documentation/devicetree/bindings/net/ethernet.txt
for details.
- mii-bus : Should be a phandle to a valid MDIO bus device node.
This mii-bus will be used in preference to the
global dsa,mii-bus defined above, for this switch.
Optional subnodes:
- fixed-link : Fixed-link subnode describing a link to a non-MDIO
managed entity. See
Documentation/devicetree/bindings/net/fixed-link.txt
for details.
Example:
dsa@0 {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
interrupts = <10>;
dsa,ethernet = <ðernet0>;
dsa,mii-bus = <&mii_bus0>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <16 0>; /* MDIO address 16, switch 0 in tree */
port@0 {
reg = <0>;
label = "lan1";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan2";
};
port@5 {
reg = <5>;
label = "cpu";
};
switch0port6: port@6 {
reg = <6>;
label = "dsa";
link = <&switch1port0
&switch2port0>;
};
};
switch@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <17 1>; /* MDIO address 17, switch 1 in tree */
mii-bus = <&mii_bus1>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
switch1port0: port@0 {
reg = <0>;
label = "dsa";
link = <&switch0port6>;
};
switch1port1: port@1 {
reg = <1>;
label = "dsa";
link = <&switch2port1>;
};
};
switch@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <18 2>; /* MDIO address 18, switch 2 in tree */
mii-bus = <&mii_bus1>;
switch2port0: port@0 {
reg = <0>;
label = "dsa";
link = <&switch1port1
&switch0port6>;
};
};
};
|
