blob: 3c13fdcafb1e8818241cbc266c5f98cf09c7f6ad (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2011 Calxeda, Inc.
*/
#ifndef _MACH_HIGHBANK__SYSREGS_H_
#define _MACH_HIGHBANK__SYSREGS_H_
#include <linux/io.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include "core.h"
extern void __iomem *sregs_base;
#define HB_SREG_A9_PWR_REQ 0xf00
#define HB_SREG_A9_BOOT_STAT 0xf04
#define HB_SREG_A9_BOOT_DATA 0xf08
#define HB_PWR_SUSPEND 0
#define HB_PWR_SOFT_RESET 1
#define HB_PWR_HARD_RESET 2
#define HB_PWR_SHUTDOWN 3
#define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
static inline void highbank_set_core_pwr(void)
{
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (scu_base_addr)
scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
else
writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
}
static inline void highbank_clear_core_pwr(void)
{
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (scu_base_addr)
scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
else
writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
}
static inline void highbank_set_pwr_suspend(void)
{
writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_set_core_pwr();
}
static inline void highbank_set_pwr_shutdown(void)
{
writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_set_core_pwr();
}
static inline void highbank_set_pwr_soft_reset(void)
{
writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_set_core_pwr();
}
static inline void highbank_set_pwr_hard_reset(void)
{
writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_set_core_pwr();
}
static inline void highbank_clear_pwr_request(void)
{
writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_clear_core_pwr();
}
#endif
|
