aboutsummaryrefslogtreecommitdiff
path: root/drivers/firmware/efi/cper-x86.c
blob: 438ed9eff6d01e7d03e3d91d5089448d5d3cb18c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2018, Advanced Micro Devices, Inc.

#include <linux/cper.h>
#include <linux/acpi.h>

/*
 * We don't need a "CPER_IA" prefix since these are all locally defined.
 * This will save us a lot of line space.
 */
#define VALID_LAPIC_ID			BIT_ULL(0)
#define VALID_CPUID_INFO		BIT_ULL(1)
#define VALID_PROC_ERR_INFO_NUM(bits)	(((bits) & GENMASK_ULL(7, 2)) >> 2)
#define VALID_PROC_CXT_INFO_NUM(bits)	(((bits) & GENMASK_ULL(13, 8)) >> 8)

#define INFO_ERR_STRUCT_TYPE_CACHE					\
	GUID_INIT(0xA55701F5, 0xE3EF, 0x43DE, 0xAC, 0x72, 0x24, 0x9B,	\
		  0x57, 0x3F, 0xAD, 0x2C)
#define INFO_ERR_STRUCT_TYPE_TLB					\
	GUID_INIT(0xFC06B535, 0x5E1F, 0x4562, 0x9F, 0x25, 0x0A, 0x3B,	\
		  0x9A, 0xDB, 0x63, 0xC3)
#define INFO_ERR_STRUCT_TYPE_BUS					\
	GUID_INIT(0x1CF3F8B3, 0xC5B1, 0x49a2, 0xAA, 0x59, 0x5E, 0xEF,	\
		  0x92, 0xFF, 0xA6, 0x3C)
#define INFO_ERR_STRUCT_TYPE_MS						\
	GUID_INIT(0x48AB7F57, 0xDC34, 0x4f6c, 0xA7, 0xD3, 0xB0, 0xB5,	\
		  0xB0, 0xA7, 0x43, 0x14)

#define INFO_VALID_CHECK_INFO		BIT_ULL(0)
#define INFO_VALID_TARGET_ID		BIT_ULL(1)
#define INFO_VALID_REQUESTOR_ID		BIT_ULL(2)
#define INFO_VALID_RESPONDER_ID		BIT_ULL(3)
#define INFO_VALID_IP			BIT_ULL(4)

#define CHECK_VALID_TRANS_TYPE		BIT_ULL(0)
#define CHECK_VALID_OPERATION		BIT_ULL(1)
#define CHECK_VALID_LEVEL		BIT_ULL(2)
#define CHECK_VALID_PCC			BIT_ULL(3)
#define CHECK_VALID_UNCORRECTED		BIT_ULL(4)
#define CHECK_VALID_PRECISE_IP		BIT_ULL(5)
#define CHECK_VALID_RESTARTABLE_IP	BIT_ULL(6)
#define CHECK_VALID_OVERFLOW		BIT_ULL(7)

#define CHECK_VALID_BUS_PART_TYPE	BIT_ULL(8)
#define CHECK_VALID_BUS_TIME_OUT	BIT_ULL(9)
#define CHECK_VALID_BUS_ADDR_SPACE	BIT_ULL(10)

#define CHECK_VALID_BITS(check)		(((check) & GENMASK_ULL(15, 0)))
#define CHECK_TRANS_TYPE(check)		(((check) & GENMASK_ULL(17, 16)) >> 16)
#define CHECK_OPERATION(check)		(((check) & GENMASK_ULL(21, 18)) >> 18)
#define CHECK_LEVEL(check)		(((check) & GENMASK_ULL(24, 22)) >> 22)
#define CHECK_PCC			BIT_ULL(25)
#define CHECK_UNCORRECTED		BIT_ULL(26)
#define CHECK_PRECISE_IP		BIT_ULL(27)
#define CHECK_RESTARTABLE_IP		BIT_ULL(28)
#define CHECK_OVERFLOW			BIT_ULL(29)

#define CHECK_BUS_PART_TYPE(check)	(((check) & GENMASK_ULL(31, 30)) >> 30)
#define CHECK_BUS_TIME_OUT		BIT_ULL(32)
#define CHECK_BUS_ADDR_SPACE(check)	(((check) & GENMASK_ULL(34, 33)) >> 33)

#define CHECK_VALID_MS_ERR_TYPE		BIT_ULL(0)
#define CHECK_VALID_MS_PCC		BIT_ULL(1)
#define CHECK_VALID_MS_UNCORRECTED	BIT_ULL(2)
#define CHECK_VALID_MS_PRECISE_IP	BIT_ULL(3)
#define CHECK_VALID_MS_RESTARTABLE_IP	BIT_ULL(4)
#define CHECK_VALID_MS_OVERFLOW		BIT_ULL(5)

#define CHECK_MS_ERR_TYPE(check)	(((check) & GENMASK_ULL(18, 16)) >> 16)
#define CHECK_MS_PCC			BIT_ULL(19)
#define CHECK_MS_UNCORRECTED		BIT_ULL(20)
#define CHECK_MS_PRECISE_IP		BIT_ULL(21)
#define CHECK_MS_RESTARTABLE_IP		BIT_ULL(22)
#define CHECK_MS_OVERFLOW		BIT_ULL(23)

#define CTX_TYPE_MSR			1
#define CTX_TYPE_MMREG			7

enum err_types {
	ERR_TYPE_CACHE = 0,
	ERR_TYPE_TLB,
	ERR_TYPE_BUS,
	ERR_TYPE_MS,
	N_ERR_TYPES
};

static enum err_types cper_get_err_type(const guid_t *err_type)
{
	if (guid_equal(err_type, &INFO_ERR_STRUCT_TYPE_CACHE))
		return ERR_TYPE_CACHE;
	else if (guid_equal(err_type, &INFO_ERR_STRUCT_TYPE_TLB))
		return ERR_TYPE_TLB;
	else if (guid_equal(err_type, &INFO_ERR_STRUCT_TYPE_BUS))
		return ERR_TYPE_BUS;
	else if (guid_equal(err_type, &INFO_ERR_STRUCT_TYPE_MS))
		return ERR_TYPE_MS;
	else
		return N_ERR_TYPES;
}

static const char * const ia_check_trans_type_strs[] = {
	"Instruction",
	"Data Access",
	"Generic",
};

static const char * const ia_check_op_strs[] = {
	"generic error",
	"generic read",
	"generic write",
	"data read",
	"data write",
	"instruction fetch",
	"prefetch",
	"eviction",
	"snoop",
};

static const char * const ia_check_bus_part_type_strs[] = {
	"Local Processor originated request",
	"Local Processor responded to request",
	"Local Processor observed",
	"Generic",
};

static const char * const ia_check_bus_addr_space_strs[] = {
	"Memory Access",
	"Reserved",
	"I/O",
	"Other Transaction",
};

static const char * const ia_check_ms_error_type_strs[] = {
	"No Error",
	"Unclassified",
	"Microcode ROM Parity Error",
	"External Error",
	"FRC Error",
	"Internal Unclassified",
};

static const char * const ia_reg_ctx_strs[] = {
	"Unclassified Data",
	"MSR Registers (Machine Check and other MSRs)",
	"32-bit Mode Execution Context",
	"64-bit Mode Execution Context",
	"FXSAVE Context",
	"32-bit Mode Debug Registers (DR0-DR7)",
	"64-bit Mode Debug Registers (DR0-DR7)",
	"Memory Mapped Registers",
};

static inline void print_bool(char *str, const char *pfx, u64 check, u64 bit)
{
	printk("%s%s: %s\n", pfx, str, (check & bit) ? "true" : "false");
}

static void print_err_info_ms(const char *pfx, u16 validation_bits, u64 check)
{
	if (validation_bits & CHECK_VALID_MS_ERR_TYPE) {
		u8 err_type = CHECK_MS_ERR_TYPE(check);

		printk("%sError Type: %u, %s\n", pfx, err_type,
		       err_type < ARRAY_SIZE(ia_check_ms_error_type_strs) ?
		       ia_check_ms_error_type_strs[err_type] : "unknown");
	}

	if (validation_bits & CHECK_VALID_MS_PCC)
		print_bool("Processor Context Corrupt", pfx, check, CHECK_MS_PCC);

	if (validation_bits & CHECK_VALID_MS_UNCORRECTED)
		print_bool("Uncorrected", pfx, check, CHECK_MS_UNCORRECTED);

	if (validation_bits & CHECK_VALID_MS_PRECISE_IP)
		print_bool("Precise IP", pfx, check, CHECK_MS_PRECISE_IP);

	if (validation_bits & CHECK_VALID_MS_RESTARTABLE_IP)
		print_bool("Restartable IP", pfx, check, CHECK_MS_RESTARTABLE_IP);

	if (validation_bits & CHECK_VALID_MS_OVERFLOW)
		print_bool("Overflow", pfx, check, CHECK_MS_OVERFLOW);
}

static void print_err_info(const char *pfx, u8 err_type, u64 check)
{
	u16 validation_bits = CHECK_VALID_BITS(check);

	/*
	 * The MS Check structure varies a lot from the others, so use a
	 * separate function for decoding.
	 */
	if (err_type == ERR_TYPE_MS)
		return print_err_info_ms(pfx, validation_bits, check);

	if (validation_bits & CHECK_VALID_TRANS_TYPE) {
		u8 trans_type = CHECK_TRANS_TYPE(check);

		printk("%sTransaction Type: %u, %s\n", pfx, trans_type,
		       trans_type < ARRAY_SIZE(ia_check_trans_type_strs) ?
		       ia_check_trans_type_strs[trans_type] : "unknown");
	}

	if (validation_bits & CHECK_VALID_OPERATION) {
		u8 op = CHECK_OPERATION(check);

		/*
		 * CACHE has more operation types than TLB or BUS, though the
		 * name and the order are the same.
		 */
		u8 max_ops = (err_type == ERR_TYPE_CACHE) ? 9 : 7;

		printk("%sOperation: %u, %s\n", pfx, op,
		       op < max_ops ? ia_check_op_strs[op] : "unknown");
	}

	if (validation_bits & CHECK_VALID_LEVEL)
		printk("%sLevel: %llu\n", pfx, CHECK_LEVEL(check));

	if (validation_bits & CHECK_VALID_PCC)
		print_bool("Processor Context Corrupt", pfx, check, CHECK_PCC);

	if (validation_bits & CHECK_VALID_UNCORRECTED)
		print_bool("Uncorrected", pfx, check, CHECK_UNCORRECTED);

	if (validation_bits & CHECK_VALID_PRECISE_IP)
		print_bool("Precise IP", pfx, check, CHECK_PRECISE_IP);

	if (validation_bits & CHECK_VALID_RESTARTABLE_IP)
		print_bool("Restartable IP", pfx, check, CHECK_RESTARTABLE_IP);

	if (validation_bits & CHECK_VALID_OVERFLOW)
		print_bool("Overflow", pfx, check, CHECK_OVERFLOW);

	if (err_type != ERR_TYPE_BUS)
		return;

	if (validation_bits & CHECK_VALID_BUS_PART_TYPE) {
		u8 part_type = CHECK_BUS_PART_TYPE(check);

		printk("%sParticipation Type: %u, %s\n", pfx, part_type,
		       part_type < ARRAY_SIZE(ia_check_bus_part_type_strs) ?
		       ia_check_bus_part_type_strs[part_type] : "unknown");
	}

	if (validation_bits & CHECK_VALID_BUS_TIME_OUT)
		print_bool("Time Out", pfx, check, CHECK_BUS_TIME_OUT);

	if (validation_bits & CHECK_VALID_BUS_ADDR_SPACE) {
		u8 addr_space = CHECK_BUS_ADDR_SPACE(check);

		printk("%sAddress Space: %u, %s\n", pfx, addr_space,
		       addr_space < ARRAY_SIZE(ia_check_bus_addr_space_strs) ?
		       ia_check_bus_addr_space_strs[addr_space] : "unknown");
	}
}

void cper_print_proc_ia(const char *pfx, const struct cper_sec_proc_ia *proc)
{
	int i;
	struct cper_ia_err_info *err_info;
	struct cper_ia_proc_ctx *ctx_info;
	char newpfx[64], infopfx[64];
	u8 err_type;

	if (proc->validation_bits & VALID_LAPIC_ID)
		printk("%sLocal APIC_ID: 0x%llx\n", pfx, proc->lapic_id);

	if (proc->validation_bits & VALID_CPUID_INFO) {
		printk("%sCPUID Info:\n", pfx);
		print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, proc->cpuid,
			       sizeof(proc->cpuid), 0);
	}

	snprintf(newpfx, sizeof(newpfx), "%s ", pfx);

	err_info = (struct cper_ia_err_info *)(proc + 1);
	for (i = 0; i < VALID_PROC_ERR_INFO_NUM(proc->validation_bits); i++) {
		printk("%sError Information Structure %d:\n", pfx, i);

		err_type = cper_get_err_type(&err_info->err_type);
		printk("%sError Structure Type: %s\n", newpfx,
		       err_type < ARRAY_SIZE(cper_proc_error_type_strs) ?
		       cper_proc_error_type_strs[err_type] : "unknown");

		if (err_type >= N_ERR_TYPES) {
			printk("%sError Structure Type: %pUl\n", newpfx,
			       &err_info->err_type);
		}

		if (err_info->validation_bits & INFO_VALID_CHECK_INFO) {
			printk("%sCheck Information: 0x%016llx\n", newpfx,
			       err_info->check_info);

			if (err_type < N_ERR_TYPES) {
				snprintf(infopfx, sizeof(infopfx), "%s ",
					 newpfx);

				print_err_info(infopfx, err_type,
					       err_info->check_info);
			}
		}

		if (err_info->validation_bits & INFO_VALID_TARGET_ID) {
			printk("%sTarget Identifier: 0x%016llx\n",
			       newpfx, err_info->target_id);
		}

		if (err_info->validation_bits & INFO_VALID_REQUESTOR_ID) {
			printk("%sRequestor Identifier: 0x%016llx\n",
			       newpfx, err_info->requestor_id);
		}

		if (err_info->validation_bits & INFO_VALID_RESPONDER_ID) {
			printk("%sResponder Identifier: 0x%016llx\n",
			       newpfx, err_info->responder_id);
		}

		if (err_info->validation_bits & INFO_VALID_IP) {
			printk("%sInstruction Pointer: 0x%016llx\n",
			       newpfx, err_info->ip);
		}

		err_info++;
	}

	ctx_info = (struct cper_ia_proc_ctx *)err_info;
	for (i = 0; i < VALID_PROC_CXT_INFO_NUM(proc->validation_bits); i++) {
		int size = sizeof(*ctx_info) + ctx_info->reg_arr_size;
		int groupsize = 4;

		printk("%sContext Information Structure %d:\n", pfx, i);

		printk("%sRegister Context Type: %s\n", newpfx,
		       ctx_info->reg_ctx_type < ARRAY_SIZE(ia_reg_ctx_strs) ?
		       ia_reg_ctx_strs[ctx_info->reg_ctx_type] : "unknown");

		printk("%sRegister Array Size: 0x%04x\n", newpfx,
		       ctx_info->reg_arr_size);

		if (ctx_info->reg_ctx_type == CTX_TYPE_MSR) {
			groupsize = 8; /* MSRs are 8 bytes wide. */
			printk("%sMSR Address: 0x%08x\n", newpfx,
			       ctx_info->msr_addr);
		}

		if (ctx_info->reg_ctx_type == CTX_TYPE_MMREG) {
			printk("%sMM Register Address: 0x%016llx\n", newpfx,
			       ctx_info->mm_reg_addr);
		}

		if (ctx_info->reg_ctx_type != CTX_TYPE_MSR ||
		    arch_apei_report_x86_error(ctx_info, proc->lapic_id)) {
			printk("%sRegister Array:\n", newpfx);
			print_hex_dump(newpfx, "", DUMP_PREFIX_OFFSET, 16,
				       groupsize, (ctx_info + 1),
				       ctx_info->reg_arr_size, 0);
		}

		ctx_info = (struct cper_ia_proc_ctx *)((long)ctx_info + size);
	}
}