aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/kmb/kmb_crtc.c
blob: 44327bc629ca0fc794d5947fa4f899ef95b46a4e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright © 2018-2020 Intel Corporation
 */

#include <linux/clk.h>

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
#include <drm/drm_modeset_helper_vtables.h>

#include "kmb_drv.h"
#include "kmb_dsi.h"
#include "kmb_plane.h"
#include "kmb_regs.h"

struct kmb_crtc_timing {
	u32 vfront_porch;
	u32 vback_porch;
	u32 vsync_len;
	u32 hfront_porch;
	u32 hback_porch;
	u32 hsync_len;
};

static int kmb_crtc_enable_vblank(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct kmb_drm_private *kmb = to_kmb(dev);

	/* Clear interrupt */
	kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
	/* Set which interval to generate vertical interrupt */
	kmb_write_lcd(kmb, LCD_VSTATUS_COMPARE,
		      LCD_VSTATUS_COMPARE_VSYNC);
	/* Enable vertical interrupt */
	kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE,
			    LCD_INT_VERT_COMP);
	return 0;
}

static void kmb_crtc_disable_vblank(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct kmb_drm_private *kmb = to_kmb(dev);

	/* Clear interrupt */
	kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
	/* Disable vertical interrupt */
	kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
			    LCD_INT_VERT_COMP);
}

static const struct drm_crtc_funcs kmb_crtc_funcs = {
	.destroy = drm_crtc_cleanup,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = drm_atomic_helper_crtc_reset,
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	.enable_vblank = kmb_crtc_enable_vblank,
	.disable_vblank = kmb_crtc_disable_vblank,
};

static void kmb_crtc_set_mode(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_display_mode *m = &crtc->state->adjusted_mode;
	struct kmb_crtc_timing vm;
	struct kmb_drm_private *kmb = to_kmb(dev);
	unsigned int val = 0;

	/* Initialize mipi */
	kmb_dsi_mode_set(kmb->kmb_dsi, m, kmb->sys_clk_mhz);
	drm_info(dev,
		 "vfp= %d vbp= %d vsync_len=%d hfp=%d hbp=%d hsync_len=%d\n",
		 m->crtc_vsync_start - m->crtc_vdisplay,
		 m->crtc_vtotal - m->crtc_vsync_end,
		 m->crtc_vsync_end - m->crtc_vsync_start,
		 m->crtc_hsync_start - m->crtc_hdisplay,
		 m->crtc_htotal - m->crtc_hsync_end,
		 m->crtc_hsync_end - m->crtc_hsync_start);
	val = kmb_read_lcd(kmb, LCD_INT_ENABLE);
	kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, val);
	kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, ~0x0);
	vm.vfront_porch = 2;
	vm.vback_porch = 2;
	vm.vsync_len = 8;
	vm.hfront_porch = 0;
	vm.hback_porch = 0;
	vm.hsync_len = 28;

	drm_dbg(dev, "%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hsync-l=%d",
		__func__, __LINE__,
			m->crtc_vdisplay, vm.vback_porch, vm.vfront_porch,
			vm.vsync_len, m->crtc_hdisplay, vm.hback_porch,
			vm.hfront_porch, vm.hsync_len);
	kmb_write_lcd(kmb, LCD_V_ACTIVEHEIGHT,
		      m->crtc_vdisplay - 1);
	kmb_write_lcd(kmb, LCD_V_BACKPORCH, vm.vback_porch);
	kmb_write_lcd(kmb, LCD_V_FRONTPORCH, vm.vfront_porch);
	kmb_write_lcd(kmb, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
	kmb_write_lcd(kmb, LCD_H_ACTIVEWIDTH,
		      m->crtc_hdisplay - 1);
	kmb_write_lcd(kmb, LCD_H_BACKPORCH, vm.hback_porch);
	kmb_write_lcd(kmb, LCD_H_FRONTPORCH, vm.hfront_porch);
	kmb_write_lcd(kmb, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
	/* This is hardcoded as 0 in the Myriadx code */
	kmb_write_lcd(kmb, LCD_VSYNC_START, 0);
	kmb_write_lcd(kmb, LCD_VSYNC_END, 0);
	/* Back ground color */
	kmb_write_lcd(kmb, LCD_BG_COLOUR_LS, 0x4);
	if (m->flags == DRM_MODE_FLAG_INTERLACE) {
		kmb_write_lcd(kmb,
			      LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
		kmb_write_lcd(kmb,
			      LCD_V_BACKPORCH_EVEN, vm.vback_porch);
		kmb_write_lcd(kmb,
			      LCD_V_FRONTPORCH_EVEN, vm.vfront_porch);
		kmb_write_lcd(kmb, LCD_V_ACTIVEHEIGHT_EVEN,
			      m->crtc_vdisplay - 1);
		/* This is hardcoded as 10 in the Myriadx code */
		kmb_write_lcd(kmb, LCD_VSYNC_START_EVEN, 10);
		kmb_write_lcd(kmb, LCD_VSYNC_END_EVEN, 10);
	}
	kmb_write_lcd(kmb, LCD_TIMING_GEN_TRIG, 1);
	kmb_set_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_ENABLE);
	kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE, val);
}

static void kmb_crtc_atomic_enable(struct drm_crtc *crtc,
				   struct drm_atomic_state *state)
{
	struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc);

	clk_prepare_enable(kmb->kmb_clk.clk_lcd);
	kmb_crtc_set_mode(crtc);
	drm_crtc_vblank_on(crtc);
}

static void kmb_crtc_atomic_disable(struct drm_crtc *crtc,
				    struct drm_atomic_state *state)
{
	struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc);
	struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);

	/* due to hw limitations, planes need to be off when crtc is off */
	drm_atomic_helper_disable_planes_on_crtc(old_state, false);

	drm_crtc_vblank_off(crtc);
	clk_disable_unprepare(kmb->kmb_clk.clk_lcd);
}

static void kmb_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_atomic_state *state)
{
	struct drm_device *dev = crtc->dev;
	struct kmb_drm_private *kmb = to_kmb(dev);

	kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
			    LCD_INT_VERT_COMP);
}

static void kmb_crtc_atomic_flush(struct drm_crtc *crtc,
				  struct drm_atomic_state *state)
{
	struct drm_device *dev = crtc->dev;
	struct kmb_drm_private *kmb = to_kmb(dev);

	kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE,
			    LCD_INT_VERT_COMP);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		if (drm_crtc_vblank_get(crtc) == 0)
			drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		else
			drm_crtc_send_vblank_event(crtc, crtc->state->event);
	}
	crtc->state->event = NULL;
	spin_unlock_irq(&crtc->dev->event_lock);
}

static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = {
	.atomic_begin = kmb_crtc_atomic_begin,
	.atomic_enable = kmb_crtc_atomic_enable,
	.atomic_disable = kmb_crtc_atomic_disable,
	.atomic_flush = kmb_crtc_atomic_flush,
};

int kmb_setup_crtc(struct drm_device *drm)
{
	struct kmb_drm_private *kmb = to_kmb(drm);
	struct kmb_plane *primary;
	int ret;

	primary = kmb_plane_init(drm);
	if (IS_ERR(primary))
		return PTR_ERR(primary);

	ret = drm_crtc_init_with_planes(drm, &kmb->crtc, &primary->base_plane,
					NULL, &kmb_crtc_funcs, NULL);
	if (ret) {
		kmb_plane_destroy(&primary->base_plane);
		return ret;
	}

	drm_crtc_helper_add(&kmb->crtc, &kmb_crtc_helper_funcs);
	return 0;
}