From 61bd2f75f5eaf645e2c90fe2294cba37f7d8627f Mon Sep 17 00:00:00 2001
From: York Sun
Date: Wed, 4 Nov 2015 09:53:10 -0800
Subject: drivers/ddr/fsl: Enable detection of one DDR controller operation for
 LSCH3

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  7 ++++
 drivers/ddr/fsl/main.c                            |  1 +
 drivers/ddr/fsl/util.c                            | 40 +++++++++++++++++++++++
 include/fsl_ddr.h                                 |  1 +
 4 files changed, 49 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5ce916c4d09..afc329ad6b6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -67,6 +67,13 @@
 #define CCI_MN_DVM_DOMAIN_CTL		0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
 
+#define CCI_HN_F_0_BASE			(CCI_MN_BASE + 0x200000)
+#define CCI_HN_F_1_BASE			(CCI_MN_BASE + 0x210000)
+#define CCN_HN_F_SAM_CTL		0x8	/* offset on base HN_F base */
+#define CCN_HN_F_SAM_NODEID_MASK	0x7f
+#define CCN_HN_F_SAM_NODEID_DDR0	0x4
+#define CCN_HN_F_SAM_NODEID_DDR1	0xe
+
 #define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
 #define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
 #define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 72ec1be65d1..c68663220d8 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -813,6 +813,7 @@ phys_size_t fsl_ddr_sdram(void)
 	info.board_need_mem_reset = board_need_mem_reset;
 	info.board_mem_reset = board_assert_mem_reset;
 	info.board_mem_de_reset = board_deassert_mem_reset;
+	remove_unused_controllers(&info);
 
 	return __fsl_ddr_sdram(&info);
 }
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index ce55aea1b48..1a49b28f331 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -385,3 +385,43 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 		ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
 }
 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
+
+void remove_unused_controllers(fsl_ddr_info_t *info)
+{
+#ifdef CONFIG_FSL_LSCH3
+	int i;
+	u64 nodeid;
+	void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
+	bool ddr0_used = false;
+	bool ddr1_used = false;
+
+	for (i = 0; i < 8; i++) {
+		nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
+		if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
+			ddr0_used = true;
+		} else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
+			ddr1_used = true;
+		} else {
+			printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
+			       nodeid);
+		}
+		hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
+	}
+	if (!ddr0_used && !ddr1_used) {
+		printf("Invalid configuration in HN-F SAM control\n");
+		return;
+	}
+
+	if (!ddr0_used && info->first_ctrl == 0) {
+		info->first_ctrl = 1;
+		info->num_ctrls = 1;
+		debug("First DDR controller disabled\n");
+		return;
+	}
+
+	if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
+		info->num_ctrls = 1;
+		debug("Second DDR controller disabled\n");
+	}
+#endif
+}
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 1ac092bb92d..9aaf6b334cd 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -131,6 +131,7 @@ void board_add_ram_info(int use_default);
 /* processor specific function */
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 				   unsigned int ctrl_num, int step);
+void remove_unused_controllers(fsl_ddr_info_t *info);
 
 /* board specific function */
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-- 
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