diff options
| author | Rob Herring | 2012-12-30 10:15:03 -0600 |
|---|---|---|
| committer | Olof Johansson | 2013-01-07 21:08:23 -0800 |
| commit | 3943deeddac65ab1d19fcc839ab58ef13a653532 (patch) | |
| tree | 4f46df39e4991a65e548faf86e11200397ee3021 | |
| parent | 36ff67bc948292065b0f20928d7e96f261b6ddc1 (diff) | |
ARM: dts: fix highbank cpu mpidr values
With the addition of commit a0ae0240 (ARM: kernel: add device tree init
map function), the cpu reg values must match the cpu mpidr register or we'll
get warnings. For some reason, the CLUSTERID on highbank is 9, so the reg
value needs to be 0x90n to quiet the warnings.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
| -rw-r--r-- | arch/arm/boot/dts/highbank.dts | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 81e0bfa6c175..5927a8df5625 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -30,37 +30,37 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu@900 { compatible = "arm,cortex-a9"; device_type = "cpu"; - reg = <0>; + reg = <0x900>; next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; }; - cpu@1 { + cpu@901 { compatible = "arm,cortex-a9"; device_type = "cpu"; - reg = <1>; + reg = <0x901>; next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; }; - cpu@2 { + cpu@902 { compatible = "arm,cortex-a9"; device_type = "cpu"; - reg = <2>; + reg = <0x902>; next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; }; - cpu@3 { + cpu@903 { compatible = "arm,cortex-a9"; device_type = "cpu"; - reg = <3>; + reg = <0x903>; next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; |