diff options
| author | Nicolin Chen | 2020-09-17 04:31:55 -0700 |
|---|---|---|
| committer | Joerg Roedel | 2020-09-18 11:07:07 +0200 |
| commit | 675d12acb66bb190d32a3fae187e379f01cbd8ce (patch) | |
| tree | bfa799b0d6499d932ca5bc68dc04f75c5b553ea7 | |
| parent | d5c152c3409ac1982a9277d8d344e073eda17e78 (diff) | |
memory: tegra: Correct num_tlb_lines for tegra210
According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
should be 48 (0x30) rather than 32 (0x20).
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200917113155.13438-3-nicoleotsuka@gmail.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
| -rw-r--r-- | drivers/memory/tegra/tegra210.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index cc0482434c75..7212d1d7b348 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1073,7 +1073,7 @@ static const struct tegra_smmu_soc tegra210_smmu_soc = { .num_groups = ARRAY_SIZE(tegra210_groups), .supports_round_robin_arbitration = true, .supports_request_limit = true, - .num_tlb_lines = 32, + .num_tlb_lines = 48, .num_asids = 128, }; |