diff options
| author | Paul Burton | 2015-05-24 16:11:37 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2015-06-21 21:53:17 +0200 |
| commit | 41dd641e9a1a7229383f9b342a57cb6720e7ea46 (patch) | |
| tree | 1d449d2800799b126035d8ce7c78a77a8763dad7 /drivers/clk/ingenic | |
| parent | ff1930c6bdf031e72e101a8aa47d54e73a745f93 (diff) | |
MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move jz4740_clock_set_wait_mode for such consistency.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10153/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/clk/ingenic')
| -rw-r--r-- | drivers/clk/ingenic/jz4740-cgu.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index d5bb7a39219e..0209ed6d412a 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -19,10 +19,12 @@ #include <linux/delay.h> #include <linux/of.h> #include <dt-bindings/clock/jz4740-cgu.h> +#include <asm/mach-jz4740/clock.h> #include "cgu.h" /* CGU register offsets */ #define CGU_REG_CPCCR 0x00 +#define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR 0x10 #define CGU_REG_SCR 0x24 #define CGU_REG_I2SCDR 0x60 @@ -42,6 +44,9 @@ #define PLLCTL_BYPASS (1 << 9) #define PLLCTL_ENABLE (1 << 8) +/* bits within the LCR register */ +#define LCR_SLEEP (1 << 0) + static struct ingenic_cgu *cgu; static const s8 pll_od_encoding[4] = { @@ -220,3 +225,20 @@ static void __init jz4740_cgu_init(struct device_node *np) pr_err("%s: failed to register CGU Clocks\n", __func__); } CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); + +void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode) +{ + uint32_t lcr = readl(cgu->base + CGU_REG_LCR); + + switch (mode) { + case JZ4740_WAIT_MODE_IDLE: + lcr &= ~LCR_SLEEP; + break; + + case JZ4740_WAIT_MODE_SLEEP: + lcr |= LCR_SLEEP; + break; + } + + writel(lcr, cgu->base + CGU_REG_LCR); +} |