diff options
| author | AngeloGioacchino Del Regno | 2023-03-06 15:05:11 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2023-05-11 23:03:32 +0900 |
| commit | 2b18f12fe6d2701757e0d2fad7385ee7c05e5a5b (patch) | |
| tree | c56b3f3b53619604d1f98bf610afefcd9135e143 /drivers/clk/mediatek/clk-mt8173-mm.c | |
| parent | 6f24e8ef3372330b52648a407a8c53200c3ab085 (diff) | |
clk: mediatek: Consistently use GATE_MTK() macro
[ Upstream commit 4c85e20b656607897e3bb06ff565822fa4b4de95 ]
All the various MediaTek clock drivers are, in a way or another,
redefining the GATE_MTK() macro with different names: while some
are doing that by actually using GATE_MTK(), others are copying
it entirely (hence, entirely redefining it).
Change all clock drivers to always and consistently use this macro.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-23-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stable-dep-of: fa8c0d01df62 ("clk: mediatek: mt7622: Properly use CLK_IS_CRITICAL flag")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8173-mm.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8173-mm.c | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/clk-mt8173-mm.c index 8abf42c2030c..5826eabdc9c7 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -25,23 +25,11 @@ static const struct mtk_gate_regs mm1_cg_regs = { .sta_ofs = 0x0110, }; -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mt8173_mm_clks[] = { /* MM0 */ |