diff options
| author | Martin Blumenstingl | 2019-05-20 22:03:17 +0200 |
|---|---|---|
| committer | Jerome Brunet | 2019-06-11 11:02:04 +0200 |
| commit | f278f05e748cdce3d7994c5de7cc2f02cc185f65 (patch) | |
| tree | b93740ae9d50be4c3dc8c310b85bd3d41a91c5da /drivers/clk/meson/meson8b.h | |
| parent | 4c7c965903ffb8d91ba1552d2dcaa41a5711d15e (diff) | |
clk: meson: meson8b: add the cts_amclk clocks
Add the I2S master clock also referred as cts_amclk. The setup for this
clock is identical to GXBB, so this ports commit 4087bd4b21702d ("clk:
meson: gxbb: add cts_amclk") to the Meson8/Meson8b/Meson8m2 clock
driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/meson8b.h')
| -rw-r--r-- | drivers/clk/meson/meson8b.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index ed37196187e6..03efa47e800f 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -30,6 +30,7 @@ #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ +#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ @@ -171,8 +172,10 @@ #define CLKID_VDEC_HEVC_SEL 203 #define CLKID_VDEC_HEVC_DIV 204 #define CLKID_VDEC_HEVC_EN 205 +#define CLKID_CTS_AMCLK_SEL 207 +#define CLKID_CTS_AMCLK_DIV 208 -#define CLK_NR_CLKS 207 +#define CLK_NR_CLKS 210 /* * include the CLKID and RESETID that have |