diff options
27 files changed, 1540 insertions, 522 deletions
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml new file mode 100644 index 000000000000..d783d9276124 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Coresight Address Translation Unit (CATU) + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Address Translation Unit (CATU) translates addresses between an + AXI master and system memory. The CATU is normally used along with the TMC to + implement scattering of virtual trace buffers in physical memory. The CATU + translates contiguous Virtual Addresses (VAs) from an AXI master into + non-contiguous Physical Addresses (PAs) that are intended for system memory. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-catu + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-catu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + interrupts: + maxItems: 1 + description: Address translation error interrupt + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: AXI Slave connected to another Coresight component + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + catu@207e0000 { + compatible = "arm,coresight-catu", "arm,primecell"; + reg = <0x207e0000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + in-ports { + port { + catu_in_port: endpoint { + remote-endpoint = <&etr_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml new file mode 100644 index 000000000000..0a6bc03ebe00 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight CPU Debug Component + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight CPU debug component are compliant with the ARMv8 architecture + reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The + external debug module is mainly used for two modes: self-hosted debug and + external debug, and it can be accessed from mmio region from Coresight and + eventually the debug module connects with CPU for debugging. And the debug + module provides sample-based profiling extension, which can be used to sample + CPU program counter, secure state and exception level, etc; usually every CPU + has one dedicated debug module to be connected. + +select: + properties: + compatible: + contains: + const: arm,coresight-cpu-debug + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-cpu-debug + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + cpu: + description: + A phandle to the cpu this debug component is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + description: + A phandle to the debug power domain if the debug logic has its own + dedicated power domain. CPU idle states may also need to be separately + constrained to keep CPU cores powered. + +required: + - compatible + - reg + - clocks + - clock-names + - cpu + +unevaluatedProperties: false + +examples: + - | + debug@f6590000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0xf6590000 0x1000>; + clocks = <&sys_ctrl 1>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml index 21e3515491f4..72ffe4d1e948 100644 --- a/Documentation/devicetree/bindings/arm/coresight-cti.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml @@ -2,7 +2,7 @@ # Copyright 2019 Linaro Ltd. %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/coresight-cti.yaml# +$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Coresight Cross Trigger Interface (CTI) device. @@ -12,8 +12,7 @@ description: | to one or more CoreSight components and/or a CPU, with CTIs interconnected in a star topology via the Cross Trigger Matrix (CTM), which is not programmable. The ECT components are not part of the trace generation data path and are thus - not part of the CoreSight graph described in the general CoreSight bindings - file coresight.txt. + not part of the CoreSight graph. The CTI component properties define the connections between the individual CTI and the components it is directly connected to, consisting of input and diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file mode 100644 index 000000000000..1eeedc22857c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Programmable Trace Bus Funnel + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight funnel merges 2-8 trace sources into a single trace + stream with programmable enable and priority of input ports. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-dynamic-funnel + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-dynamic-funnel + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-7])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +unevaluatedProperties: false + +examples: + - | + funnel@20040000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x20040000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel_out_port0: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel_in_port2: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml new file mode 100644 index 000000000000..a26ed9214e00 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Coresight Programmable Trace Bus Replicator + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight replicator splits a single trace stream into two trace streams + for systems that have more than one trace sink component. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-dynamic-replicator + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-dynamic-replicator + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + qcom,replicator-loses-context: + type: boolean + description: + Indicates that the replicator will lose register context when AMBA clock + is removed which is observed in some replicator designs. + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[01])?$': + description: Output connections to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +unevaluatedProperties: false + +examples: + - | + replicator@20120000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x20120000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&csys2_funnel_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml new file mode 100644 index 000000000000..fd06ede26ceb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Embedded Trace Buffer + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is + used as a circular buffer. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-etb10 + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-etb10 + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + etb@20010000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x20010000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file mode 100644 index 000000000000..e0377ce48537 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Embedded Trace MacroCell + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Embedded Trace Macrocell (ETM) is a real-time trace module providing + instruction and data tracing of a processor. + +select: + properties: + compatible: + contains: + enum: + - arm,coresight-etm3x + - arm,coresight-etm4x + - arm,coresight-etm4x-sysreg + required: + - compatible + +allOf: + - if: + not: + properties: + compatible: + contains: + const: arm,coresight-etm4x-sysreg + then: + $ref: /schemas/arm/primecell.yaml# + required: + - reg + +properties: + compatible: + oneOf: + - description: + Embedded Trace Macrocell with memory mapped access. + items: + - enum: + - arm,coresight-etm3x + - arm,coresight-etm4x + - const: arm,primecell + - description: + Embedded Trace Macrocell (version 4.x), with system register access only + const: arm,coresight-etm4x-sysreg + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + arm,coresight-loses-context-with-cpu: + type: boolean + description: + Indicates that the hardware will lose register context on CPU power down + (e.g. CPUIdle). An example of where this may be needed are systems which + contain a coresight component and CPU in the same power domain. When the + CPU powers down the coresight component also powers down and loses its + context. + + arm,cp14: + type: boolean + description: + Must be present if the system accesses ETM/PTM management registers via + co-processor 14. + + qcom,skip-power-up: + type: boolean + description: + Indicates that an implementation can skip powering up the trace unit. + TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems + since ETMs are in the same power domain as their CPU cores. This property + is required to identify such systems with hardware errata where the CPU + watchdog counter is stopped when TRCPDCR.PU is set. + + cpu: + description: + phandle to the cpu this ETM is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection from the ETM to CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - clocks + - clock-names + - cpu + - out-ports + +unevaluatedProperties: false + +examples: + - | + ptm@2201c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x2201c000 0x1000>; + + cpu = <&cpu0>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + ptm@2201d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x2201d000 0x1000>; + + cpu = <&cpu1>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml new file mode 100644 index 000000000000..374083956b20 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Static Trace Bus Funnel + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight static funnel merges 2-8 trace sources into a single trace + stream. + +properties: + compatible: + const: arm,coresight-static-funnel + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port@[0-7]$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + funnel { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + out-ports { + port { + combo_funnel_out: endpoint { + remote-endpoint = <&top_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + combo_funnel_in0: endpoint { + remote-endpoint = <&cluster0_etf_out>; + }; + }; + + port@1 { + reg = <1>; + combo_funnel_in1: endpoint { + remote-endpoint = <&cluster1_etf_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file mode 100644 index 000000000000..a34d8583830c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Static Trace Bus Replicator + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight replicator splits a single trace stream into two trace streams + for systems that have more than one trace sink component. + +properties: + compatible: + const: arm,coresight-static-replicator + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port@[01]$': + description: Output connections to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file mode 100644 index 000000000000..905008faa012 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight System Trace MacroCell + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The STM is a trace source that is integrated into a CoreSight system, designed + primarily for high-bandwidth trace of instrumentation embedded into software. + This instrumentation is made up of memory-mapped writes to the STM Advanced + eXtensible Interface (AXI) slave, which carry information about the behavior + of the software. + +select: + properties: + compatible: + contains: + const: arm,coresight-stm + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-stm + - const: arm,primecell + + reg: + maxItems: 2 + + reg-names: + items: + - const: stm-base + - const: stm-stimulus-base + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - out-ports + +unevaluatedProperties: false + +examples: + - | + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x20100000 0x1000>, + <0x28000000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file mode 100644 index 000000000000..3463b6e53aef --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Trace Memory Controller + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace + FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration + mode (ETB, ETF, ETR) is discovered at boot time when the device is probed. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-tmc + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-tmc + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + arm,buffer-size: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: + Size of contiguous buffer space for TMC ETR (embedded trace router). The + buffer size can be configured dynamically via buffer_size property in + sysfs instead. + + arm,scatter-gather: + type: boolean + description: + Indicates that the TMC-ETR can safely use the SG mode on this system. + + arm,max-burst-size: + description: + The maximum burst size initiated by TMC on the AXI master interface. The + burst size can be in the range [0..15], the setting supports one data + transfer per burst up to a maximum of 16 data transfers per burst. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: AXI or ATB Master output connection. Used for ETR + and ETF configurations. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x20070000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator2_out_port0>; + }; + }; + }; + + out-ports { + port { + etr_out_port: endpoint { + remote-endpoint = <&catu_in_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml new file mode 100644 index 000000000000..e80d48200c37 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Trace Port Interface Unit + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Trace Port Interface Unit captures trace data from the trace bus + and outputs it to an external trace port. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-tpiu + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-tpiu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + tpiu@e3c05000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xe3c05000 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&funnel4_out_port0>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml index 7f9b2d1e1147..5f07fb166c56 100644 --- a/Documentation/devicetree/bindings/arm/ete.yaml +++ b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml @@ -2,7 +2,7 @@ # Copyright 2021, Arm Ltd %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/ete.yaml#" +$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: ARM Embedded Trace Extensions @@ -20,7 +20,6 @@ description: | Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to legacy CoreSight components, a node must be listed per instance, along with any optional connection graph as per the coresight bindings. - See bindings/arm/coresight.txt. properties: $nodename: diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml index 4402d7bfd1fc..b1322658063a 100644 --- a/Documentation/devicetree/bindings/arm/trbe.yaml +++ b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml @@ -2,7 +2,7 @@ # Copyright 2021, Arm Ltd %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/trbe.yaml#" +$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: ARM Trace Buffer Extensions diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt deleted file mode 100644 index f1de3247c1b7..000000000000 --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +++ /dev/null @@ -1,49 +0,0 @@ -* CoreSight CPU Debug Component: - -CoreSight CPU debug component are compliant with the ARMv8 architecture -reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The -external debug module is mainly used for two modes: self-hosted debug and -external debug, and it can be accessed from mmio region from Coresight -and eventually the debug module connects with CPU for debugging. And the -debug module provides sample-based profiling extension, which can be used -to sample CPU program counter, secure state and exception level, etc; -usually every CPU has one dedicated debug module to be connected. - -Required properties: - -- compatible : should be "arm,coresight-cpu-debug"; supplemented with - "arm,primecell" since this driver is using the AMBA bus - interface. - -- reg : physical base address and length of the register set. - -- clocks : the clock associated to this component. - -- clock-names : the name of the clock referenced by the code. Since we are - using the AMBA framework, the name of the clock providing - the interconnect should be "apb_pclk" and the clock is - mandatory. The interface between the debug logic and the - processor core is clocked by the internal CPU clock, so it - is enabled with CPU clock by default. - -- cpu : the CPU phandle the debug module is affined to. Do not assume it - to default to CPU0 if omitted. - -Optional properties: - -- power-domains: a phandle to the debug power domain. We use "power-domains" - binding to turn on the debug logic if it has own dedicated - power domain and if necessary to use "cpuidle.off=1" or - "nohlt" in the kernel command line or sysfs node to - constrain idle states to ensure registers in the CPU power - domain are accessible. - -Example: - - debug@f6590000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6590000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu0>; - }; diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt deleted file mode 100644 index c68d93a35b6c..000000000000 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ /dev/null @@ -1,402 +0,0 @@ -* CoreSight Components: - -CoreSight components are compliant with the ARM CoreSight architecture -specification and can be connected in various topologies to suit a particular -SoCs tracing needs. These trace components can generally be classified as -sinks, links and sources. Trace data produced by one or more sources flows -through the intermediate links connecting the source to the currently selected -sink. Each CoreSight component device should use these properties to describe -its hardware characteristcs. - -* Required properties for all components *except* non-configurable replicators - and non-configurable funnels: - - * compatible: These have to be supplemented with "arm,primecell" as - drivers are using the AMBA bus interface. Possible values include: - - Embedded Trace Buffer (version 1.0): - "arm,coresight-etb10", "arm,primecell"; - - - Trace Port Interface Unit: - "arm,coresight-tpiu", "arm,primecell"; - - - Trace Memory Controller, used for Embedded Trace Buffer(ETB), - Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) - configuration. The configuration mode (ETB, ETF, ETR) is - discovered at boot time when the device is probed. - "arm,coresight-tmc", "arm,primecell"; - - - Trace Programmable Funnel: - "arm,coresight-dynamic-funnel", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For - backward compatibility and will be removed) - - - Embedded Trace Macrocell (version 3.x) and - Program Flow Trace Macrocell: - "arm,coresight-etm3x", "arm,primecell"; - - - Embedded Trace Macrocell (version 4.x), with memory mapped access. - "arm,coresight-etm4x", "arm,primecell"; - - - Embedded Trace Macrocell (version 4.x), with system register access only. - "arm,coresight-etm4x-sysreg"; - - - Coresight programmable Replicator : - "arm,coresight-dynamic-replicator", "arm,primecell"; - - - System Trace Macrocell: - "arm,coresight-stm", "arm,primecell"; [1] - - Coresight Address Translation Unit (CATU) - "arm,coresight-catu", "arm,primecell"; - - - Coresight Cross Trigger Interface (CTI): - "arm,coresight-cti", "arm,primecell"; - See coresight-cti.yaml for full CTI definitions. - - * reg: physical base address and length of the register - set(s) of the component. - - * clocks: the clocks associated to this component. - - * clock-names: the name of the clocks referenced by the code. - Since we are using the AMBA framework, the name of the clock - providing the interconnect should be "apb_pclk", and some - coresight blocks also have an additional clock "atclk", which - clocks the core of that coresight component. The latter clock - is optional. - - * port or ports: see "Graph bindings for Coresight" below. - -* Additional required property for Embedded Trace Macrocell (version 3.x and - version 4.x): - * cpu: the cpu phandle this ETM/PTM is affined to. Do not - assume it to default to CPU0 if omitted. - -* Additional required properties for System Trace Macrocells (STM): - * reg: along with the physical base address and length of the register - set as described above, another entry is required to describe the - mapping of the extended stimulus port area. - - * reg-names: the only acceptable values are "stm-base" and - "stm-stimulus-base", each corresponding to the areas defined in "reg". - -* Required properties for Coresight Cross Trigger Interface (CTI) - See coresight-cti.yaml for full CTI definitions. - -* Required properties for devices that don't show up on the AMBA bus, such as - non-configurable replicators and non-configurable funnels: - - * compatible: Currently supported value is (note the absence of the - AMBA markee): - - Coresight Non-configurable Replicator: - "arm,coresight-static-replicator"; - "arm,coresight-replicator"; (OBSOLETE. For backward - compatibility and will be removed) - - - Coresight Non-configurable Funnel: - "arm,coresight-static-funnel"; - - * port or ports: see "Graph bindings for Coresight" below. - -* Optional properties for all components: - - * arm,coresight-loses-context-with-cpu : boolean. Indicates that the - hardware will lose register context on CPU power down (e.g. CPUIdle). - An example of where this may be needed are systems which contain a - coresight component and CPU in the same power domain. When the CPU - powers down the coresight component also powers down and loses its - context. This property is currently only used for the ETM 4.x driver. - -* Optional properties for ETM/PTMs: - - * arm,cp14: must be present if the system accesses ETM/PTM management - registers via co-processor 14. - - * qcom,skip-power-up: boolean. Indicates that an implementation can - skip powering up the trace unit. TRCPDCR.PU does not have to be set - on Qualcomm Technologies Inc. systems since ETMs are in the same power - domain as their CPU cores. This property is required to identify such - systems with hardware errata where the CPU watchdog counter is stopped - when TRCPDCR.PU is set. - -* Optional property for TMC: - - * arm,buffer-size: size of contiguous buffer space for TMC ETR - (embedded trace router). This property is obsolete. The buffer size - can be configured dynamically via buffer_size property in sysfs. - - * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely - use the SG mode on this system. - - * arm,max-burst-size: The maximum burst size initiated by TMC on the - AXI master interface. The burst size can be in the range [0..15], - the setting supports one data transfer per burst up to a maximum of - 16 data transfers per burst. - -* Optional property for CATU : - * interrupts : Exactly one SPI may be listed for reporting the address - error - -* Optional property for configurable replicators: - - * qcom,replicator-loses-context: boolean. Indicates that the replicator - will lose register context when AMBA clock is removed which is observed - in some replicator designs. - -Graph bindings for Coresight -------------------------------- - -Coresight components are interconnected to create a data path for the flow of -trace data generated from the "sources" to their collection points "sink". -Each coresight component must describe the "input" and "output" connections. -The connections must be described via generic DT graph bindings as described -by the "bindings/graph.txt", where each "port" along with an "endpoint" -component represents a hardware port and the connection. - - * All output ports must be listed inside a child node named "out-ports" - * All input ports must be listed inside a child node named "in-ports". - * Port address must match the hardware port number. - -Example: - -1. Sinks - etb@20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in_port: endpoint@0 { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint@0 { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - etr@20070000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20070000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etr_in_port: endpoint { - remote-endpoint = <&replicator2_out_port0>; - }; - }; - }; - - out-ports { - port { - etr_out_port: endpoint { - remote-endpoint = <&catu_in_port>; - }; - }; - }; - }; - -2. Links - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel { - /* - * non-configurable funnel don't show up on the AMBA - * bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-funnel"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - combo_funnel_out: endpoint { - remote-endpoint = <&top_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - combo_funnel_in0: endpoint { - remote-endpoint = <&cluster0_etf_out>; - }; - }; - - port@1 { - reg = <1>; - combo_funnel_in1: endpoint { - remote-endpoint = <&cluster1_etf_out>; - }; - }; - }; - }; - - funnel@20040000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - }; - }; - -3. Sources - ptm@2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - -4. STM - stm@20100000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x20100000 0 0x1000>, - <0 0x28000000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - stm_out_port: endpoint { - remote-endpoint = <&main_funnel_in_port2>; - }; - }; - }; - }; - -5. CATU - - catu@207e0000 { - compatible = "arm,coresight-catu", "arm,primecell"; - reg = <0 0x207e0000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - in-ports { - port { - catu_in_port: endpoint { - remote-endpoint = <&etr_out_port>; - }; - }; - }; - }; - -[1]. There is currently two version of STM: STM32 and STM500. Both -have the same HW interface and as such don't need an explicit binding name. diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst index d25dfe86af9b..fb7578fd9372 100644 --- a/Documentation/trace/coresight/coresight-etm4x-reference.rst +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst @@ -650,13 +650,26 @@ Bit assignments shown below:- parameter is set this value is applied to the currently indexed address range. +.. _coresight-branch-broadcast: **bit (4):** ETM_MODE_BB **description:** - Set to enable branch broadcast if supported in hardware [IDR0]. + Set to enable branch broadcast if supported in hardware [IDR0]. The primary use for this feature + is when code is patched dynamically at run time and the full program flow may not be able to be + reconstructed using only conditional branches. + There is currently no support in Perf for supplying modified binaries to the decoder, so this + feature is only inteded to be used for debugging purposes or with a 3rd party tool. + + Choosing this option will result in a significant increase in the amount of trace generated - + possible danger of overflows, or fewer instructions covered. Note, that this option also + overrides any setting of :ref:`ETM_MODE_RETURNSTACK <coresight-return-stack>`, so where a branch + broadcast range overlaps a return stack range, return stacks will not be available for that + range. + +.. _coresight-cycle-accurate: **bit (5):** ETMv4_MODE_CYCACC @@ -678,6 +691,7 @@ Bit assignments shown below:- **description:** Set to enable virtual machine ID tracing if supported [IDR2]. +.. _coresight-timestamp: **bit (11):** ETMv4_MODE_TIMESTAMP @@ -685,6 +699,7 @@ Bit assignments shown below:- **description:** Set to enable timestamp generation if supported [IDR0]. +.. _coresight-return-stack: **bit (12):** ETM_MODE_RETURNSTACK diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index a15571d96cc8..4a71ea6cb390 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -130,7 +130,7 @@ Misc: Device Tree Bindings -------------------- -See Documentation/devicetree/bindings/arm/coresight.txt for details. +See Documentation/devicetree/bindings/arm/arm,coresight-\*.yaml for details. As of this writing drivers for ITM, STMs and CTIs are not provided but are expected to be added as the solution matures. @@ -339,7 +339,8 @@ Preference is given to the former as using the sysFS interface requires a deep understanding of the Coresight HW. The following sections provide details on using both methods. -1) Using the sysFS interface: +Using the sysFS interface +~~~~~~~~~~~~~~~~~~~~~~~~~ Before trace collection can start, a coresight sink needs to be identified. There is no limit on the amount of sinks (nor sources) that can be enabled at @@ -446,7 +447,8 @@ wealth of possibilities that coresight provides. Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc} Timestamp Timestamp: 17107041535 -2) Using perf framework: +Using perf framework +~~~~~~~~~~~~~~~~~~~~ Coresight tracers are represented using the Perf framework's Performance Monitoring Unit (PMU) abstraction. As such the perf framework takes charge of @@ -495,7 +497,11 @@ More information on the above and other example on how to use Coresight with the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub repository [#third]_. -2.1) AutoFDO analysis using the perf tools: +Advanced perf framework usage +----------------------------- + +AutoFDO analysis using the perf tools +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ perf can be used to record and analyze trace of programs. @@ -513,7 +519,8 @@ The --itrace option controls the type and frequency of synthesized events Note that only 64-bit programs are currently supported - further work is required to support instruction decode of 32-bit Arm programs. -2.2) Tracing PID +Tracing PID +~~~~~~~~~~~ The kernel can be built to write the PID value into the PE ContextID registers. For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may @@ -547,7 +554,7 @@ wants to trace PIDs for both host and guest, the two configs "contextid1" and Generating coverage files for Feedback Directed Optimization: AutoFDO ---------------------------------------------------------------------- +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 'perf inject' accepts the --itrace option in which case tracing data is removed and replaced with the synthesized events. e.g. @@ -578,6 +585,45 @@ sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tuto Bubble sorting array of 30000 elements 5806 ms +Config option formats +~~~~~~~~~~~~~~~~~~~~~ + +The following strings can be provided between // on the perf command line to enable various options. +They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/ + +.. list-table:: + :header-rows: 1 + + * - Option + - Description + * - branch_broadcast + - Session local version of the system wide setting: + :ref:`ETM_MODE_BB <coresight-branch-broadcast>` + * - contextid + - See `Tracing PID`_ + * - contextid1 + - See `Tracing PID`_ + * - contextid2 + - See `Tracing PID`_ + * - configid + - Selection for a custom configuration. This is an implementation detail and not used directly, + see :ref:`trace/coresight/coresight-config:Using Configurations in perf` + * - preset + - Override for parameters in a custom configuration, see + :ref:`trace/coresight/coresight-config:Using Configurations in perf` + * - sinkid + - Hashed version of the string to select a sink, automatically set when using the @ notation. + This is an internal implementation detail and is not used directly, see `Using perf + framework`_. + * - cycacc + - Session local version of the system wide setting: :ref:`ETMv4_MODE_CYCACC + <coresight-cycle-accurate>` + * - retstack + - Session local version of the system wide setting: :ref:`ETM_MODE_RETURNSTACK + <coresight-return-stack>` + * - timestamp + - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP + <coresight-timestamp>` How to use the STM module ------------------------- diff --git a/MAINTAINERS b/MAINTAINERS index 916cb822bcdc..daf105fc7d8d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1981,11 +1981,9 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* -F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt -F: Documentation/devicetree/bindings/arm/coresight-cti.yaml -F: Documentation/devicetree/bindings/arm/coresight.txt -F: Documentation/devicetree/bindings/arm/ete.yaml -F: Documentation/devicetree/bindings/arm/trbe.yaml +F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml +F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml +F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml F: Documentation/trace/coresight/* F: drivers/hwtracing/coresight/* F: include/dt-bindings/arm/coresight-cti-dt.h diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 2e1670523461..6ba013975741 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -134,6 +134,7 @@ struct cscfg_feature_desc { * @active_cnt: ref count for activate on this configuration. * @load_owner: handle to load owner for dynamic load and unload of configs. * @fs_group: reference to configfs group for dynamic unload. + * @available: config can be activated - multi-stage load sets true on completion. */ struct cscfg_config_desc { const char *name; @@ -148,6 +149,7 @@ struct cscfg_config_desc { atomic_t active_cnt; void *load_owner; struct config_group *fs_group; + bool available; }; /** diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ee6ce92ab4c3..1edfec1e9d18 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1424,6 +1424,7 @@ static int coresight_remove_match(struct device *dev, void *data) * platform data. */ fwnode_handle_put(conn->child_fwnode); + conn->child_fwnode = NULL; /* No need to continue */ break; } diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index c039b6ae206f..43bbd5dc3d3b 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -52,6 +52,7 @@ static DEFINE_PER_CPU(struct coresight_device *, csdev_src); * The PMU formats were orignally for ETMv3.5/PTM's ETMCR 'config'; * now take them as general formats and apply on all ETMs. */ +PMU_FORMAT_ATTR(branch_broadcast, "config:"__stringify(ETM_OPT_BRANCH_BROADCAST)); PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); /* contextid1 enables tracing CONTEXTIDR_EL1 for ETMv4 */ PMU_FORMAT_ATTR(contextid1, "config:" __stringify(ETM_OPT_CTXTID)); @@ -97,6 +98,7 @@ static struct attribute *etm_config_formats_attr[] = { &format_attr_sinkid.attr, &format_attr_preset.attr, &format_attr_configid.attr, + &format_attr_branch_broadcast.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 87299e99dabb..cf249ecad5a5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -696,6 +696,20 @@ static int etm4_parse_event_config(struct coresight_device *csdev, ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); } + /* branch broadcast - enable if selected and supported */ + if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) { + if (!drvdata->trcbb) { + /* + * Missing BB support could cause silent decode errors + * so fail to open if it's not supported. + */ + ret = -EINVAL; + goto out; + } else { + config->cfg |= BIT(ETM4_CFG_BIT_BB); + } + } + out: return ret; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 33869c1d20c3..a7bfea31f7d8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -7,6 +7,7 @@ #define _CORESIGHT_CORESIGHT_ETM_H #include <asm/local.h> +#include <linux/const.h> #include <linux/spinlock.h> #include <linux/types.h> #include "coresight-priv.h" @@ -515,7 +516,7 @@ ({ \ u64 __val; \ \ - if (__builtin_constant_p((offset))) \ + if (__is_constexpr((offset))) \ __val = read_etm4x_sysreg_const_offset((offset)); \ else \ __val = etm4x_sysreg_read((offset), true, (_64bit)); \ diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index 11850fd8c3b5..11138a9762b0 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -415,6 +415,27 @@ static void cscfg_remove_owned_csdev_features(struct coresight_device *csdev, vo } /* + * Unregister all configuration and features from configfs owned by load_owner. + * Although this is called without the list mutex being held, it is in the + * context of an unload operation which are strictly serialised, + * so the lists cannot change during this call. + */ +static void cscfg_fs_unregister_cfgs_feats(void *load_owner) +{ + struct cscfg_config_desc *config_desc; + struct cscfg_feature_desc *feat_desc; + + list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { + if (config_desc->load_owner == load_owner) + cscfg_configfs_del_config(config_desc); + } + list_for_each_entry(feat_desc, &cscfg_mgr->feat_desc_list, item) { + if (feat_desc->load_owner == load_owner) + cscfg_configfs_del_feature(feat_desc); + } +} + +/* * removal is relatively easy - just remove from all lists, anything that * matches the owner. Memory for the descriptors will be managed by the owner, * memory for the csdev items is devm_ allocated with the individual csdev @@ -426,6 +447,8 @@ static void cscfg_unload_owned_cfgs_feats(void *load_owner) struct cscfg_feature_desc *feat_desc, *feat_tmp; struct cscfg_registered_csdev *csdev_item; + lockdep_assert_held(&cscfg_mutex); + /* remove from each csdev instance feature and config lists */ list_for_each_entry(csdev_item, &cscfg_mgr->csdev_desc_list, item) { /* @@ -439,7 +462,6 @@ static void cscfg_unload_owned_cfgs_feats(void *load_owner) /* remove from the config descriptor lists */ list_for_each_entry_safe(config_desc, cfg_tmp, &cscfg_mgr->config_desc_list, item) { if (config_desc->load_owner == load_owner) { - cscfg_configfs_del_config(config_desc); etm_perf_del_symlink_cscfg(config_desc); list_del(&config_desc->item); } @@ -448,12 +470,90 @@ static void cscfg_unload_owned_cfgs_feats(void *load_owner) /* remove from the feature descriptor lists */ list_for_each_entry_safe(feat_desc, feat_tmp, &cscfg_mgr->feat_desc_list, item) { if (feat_desc->load_owner == load_owner) { - cscfg_configfs_del_feature(feat_desc); list_del(&feat_desc->item); } } } +/* + * load the features and configs to the lists - called with list mutex held + */ +static int cscfg_load_owned_cfgs_feats(struct cscfg_config_desc **config_descs, + struct cscfg_feature_desc **feat_descs, + struct cscfg_load_owner_info *owner_info) +{ + int i, err; + + lockdep_assert_held(&cscfg_mutex); + + /* load features first */ + if (feat_descs) { + for (i = 0; feat_descs[i]; i++) { + err = cscfg_load_feat(feat_descs[i]); + if (err) { + pr_err("coresight-syscfg: Failed to load feature %s\n", + feat_descs[i]->name); + return err; + } + feat_descs[i]->load_owner = owner_info; + } + } + + /* next any configurations to check feature dependencies */ + if (config_descs) { + for (i = 0; config_descs[i]; i++) { + err = cscfg_load_config(config_descs[i]); + if (err) { + pr_err("coresight-syscfg: Failed to load configuration %s\n", + config_descs[i]->name); + return err; + } + config_descs[i]->load_owner = owner_info; + config_descs[i]->available = false; + } + } + return 0; +} + +/* set configurations as available to activate at the end of the load process */ +static void cscfg_set_configs_available(struct cscfg_config_desc **config_descs) +{ + int i; + + lockdep_assert_held(&cscfg_mutex); + + if (config_descs) { + for (i = 0; config_descs[i]; i++) + config_descs[i]->available = true; + } +} + +/* + * Create and register each of the configurations and features with configfs. + * Called without mutex being held. + */ +static int cscfg_fs_register_cfgs_feats(struct cscfg_config_desc **config_descs, + struct cscfg_feature_desc **feat_descs) +{ + int i, err; + + if (feat_descs) { + for (i = 0; feat_descs[i]; i++) { + err = cscfg_configfs_add_feature(feat_descs[i]); + if (err) + return err; + } + } + if (config_descs) { + for (i = 0; config_descs[i]; i++) { + err = cscfg_configfs_add_config(config_descs[i]); + if (err) + return err; + } + } + return 0; +} + /** * cscfg_load_config_sets - API function to load feature and config sets. * @@ -476,57 +576,63 @@ int cscfg_load_config_sets(struct cscfg_config_desc **config_descs, struct cscfg_feature_desc **feat_descs, struct cscfg_load_owner_info *owner_info) { - int err = 0, i = 0; + int err = 0; mutex_lock(&cscfg_mutex); - - /* load features first */ - if (feat_descs) { - while (feat_descs[i]) { - err = cscfg_load_feat(feat_descs[i]); - if (!err) - err = cscfg_configfs_add_feature(feat_descs[i]); - if (err) { - pr_err("coresight-syscfg: Failed to load feature %s\n", - feat_descs[i]->name); - cscfg_unload_owned_cfgs_feats(owner_info); - goto exit_unlock; - } - feat_descs[i]->load_owner = owner_info; - i++; - } + if (cscfg_mgr->load_state != CSCFG_NONE) { + mutex_unlock(&cscfg_mutex); + return -EBUSY; } + cscfg_mgr->load_state = CSCFG_LOAD; - /* next any configurations to check feature dependencies */ - i = 0; - if (config_descs) { - while (config_descs[i]) { - err = cscfg_load_config(config_descs[i]); - if (!err) - err = cscfg_configfs_add_config(config_descs[i]); - if (err) { - pr_err("coresight-syscfg: Failed to load configuration %s\n", - config_descs[i]->name); - cscfg_unload_owned_cfgs_feats(owner_info); - goto exit_unlock; - } - config_descs[i]->load_owner = owner_info; - i++; - } - } + /* first load and add to the lists */ + err = cscfg_load_owned_cfgs_feats(config_descs, feat_descs, owner_info); + if (err) + goto err_clean_load; /* add the load owner to the load order list */ list_add_tail(&owner_info->item, &cscfg_mgr->load_order_list); if (!list_is_singular(&cscfg_mgr->load_order_list)) { /* lock previous item in load order list */ err = cscfg_owner_get(list_prev_entry(owner_info, item)); - if (err) { - cscfg_unload_owned_cfgs_feats(owner_info); - list_del(&owner_info->item); - } + if (err) + goto err_clean_owner_list; } + /* + * make visible to configfs - configfs manipulation must occur outside + * the list mutex lock to avoid circular lockdep issues with configfs + * built in mutexes and semaphores. This is safe as it is not possible + * to start a new load/unload operation till the current one is done. + */ + mutex_unlock(&cscfg_mutex); + + /* create the configfs elements */ + err = cscfg_fs_register_cfgs_feats(config_descs, feat_descs); + mutex_lock(&cscfg_mutex); + + if (err) + goto err_clean_cfs; + + /* mark any new configs as available for activation */ + cscfg_set_configs_available(config_descs); + goto exit_unlock; + +err_clean_cfs: + /* cleanup after error registering with configfs */ + cscfg_fs_unregister_cfgs_feats(owner_info); + + if (!list_is_singular(&cscfg_mgr->load_order_list)) + cscfg_owner_put(list_prev_entry(owner_info, item)); + +err_clean_owner_list: + list_del(&owner_info->item); + +err_clean_load: + cscfg_unload_owned_cfgs_feats(owner_info); + exit_unlock: + cscfg_mgr->load_state = CSCFG_NONE; mutex_unlock(&cscfg_mutex); return err; } @@ -543,6 +649,9 @@ EXPORT_SYMBOL_GPL(cscfg_load_config_sets); * 1) no configurations are active. * 2) the set being unloaded was the last to be loaded to maintain dependencies. * + * Once the unload operation commences, we disallow any configuration being + * made active until it is complete. + * * @owner_info: Information on owner for set being unloaded. */ int cscfg_unload_config_sets(struct cscfg_load_owner_info *owner_info) @@ -551,6 +660,13 @@ int cscfg_unload_config_sets(struct cscfg_load_owner_info *owner_info) struct cscfg_load_owner_info *load_list_item = NULL; mutex_lock(&cscfg_mutex); + if (cscfg_mgr->load_state != CSCFG_NONE) { + mutex_unlock(&cscfg_mutex); + return -EBUSY; + } + + /* unload op in progress also prevents activation of any config */ + cscfg_mgr->load_state = CSCFG_UNLOAD; /* cannot unload if anything is active */ if (atomic_read(&cscfg_mgr->sys_active_cnt)) { @@ -571,7 +687,12 @@ int cscfg_unload_config_sets(struct cscfg_load_owner_info *owner_info) goto exit_unlock; } - /* unload all belonging to load_owner */ + /* remove from configfs - again outside the scope of the list mutex */ + mutex_unlock(&cscfg_mutex); + cscfg_fs_unregister_cfgs_feats(owner_info); + mutex_lock(&cscfg_mutex); + + /* unload everything from lists belonging to load_owner */ cscfg_unload_owned_cfgs_feats(owner_info); /* remove from load order list */ @@ -582,6 +703,7 @@ int cscfg_unload_config_sets(struct cscfg_load_owner_info *owner_info) list_del(&owner_info->item); exit_unlock: + cscfg_mgr->load_state = CSCFG_NONE; mutex_unlock(&cscfg_mutex); return err; } @@ -759,8 +881,15 @@ static int _cscfg_activate_config(unsigned long cfg_hash) struct cscfg_config_desc *config_desc; int err = -EINVAL; + if (cscfg_mgr->load_state == CSCFG_UNLOAD) + return -EBUSY; + list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { if ((unsigned long)config_desc->event_ea->var == cfg_hash) { + /* if we happen upon a partly loaded config, can't use it */ + if (config_desc->available == false) + return -EBUSY; + /* must ensure that config cannot be unloaded in use */ err = cscfg_owner_get(config_desc->load_owner); if (err) @@ -1022,8 +1151,10 @@ struct device *cscfg_device(void) /* Must have a release function or the kernel will complain on module unload */ static void cscfg_dev_release(struct device *dev) { + mutex_lock(&cscfg_mutex); kfree(cscfg_mgr); cscfg_mgr = NULL; + mutex_unlock(&cscfg_mutex); } /* a device is needed to "own" some kernel elements such as sysfs entries. */ @@ -1042,6 +1173,14 @@ static int cscfg_create_device(void) if (!cscfg_mgr) goto create_dev_exit_unlock; + /* initialise the cscfg_mgr structure */ + INIT_LIST_HEAD(&cscfg_mgr->csdev_desc_list); + INIT_LIST_HEAD(&cscfg_mgr->feat_desc_list); + INIT_LIST_HEAD(&cscfg_mgr->config_desc_list); + INIT_LIST_HEAD(&cscfg_mgr->load_order_list); + atomic_set(&cscfg_mgr->sys_active_cnt, 0); + cscfg_mgr->load_state = CSCFG_NONE; + /* setup the device */ dev = cscfg_device(); dev->release = cscfg_dev_release; @@ -1056,17 +1195,73 @@ create_dev_exit_unlock: return err; } -static void cscfg_clear_device(void) +/* + * Loading and unloading is generally on user discretion. + * If exiting due to coresight module unload, we need to unload any configurations that remain, + * before we unregister the configfs intrastructure. + * + * Do this by walking the load_owner list and taking appropriate action, depending on the load + * owner type. + */ +static void cscfg_unload_cfgs_on_exit(void) { - struct cscfg_config_desc *cfg_desc; + struct cscfg_load_owner_info *owner_info = NULL; + /* + * grab the mutex - even though we are exiting, some configfs files + * may still be live till we dump them, so ensure list data is + * protected from a race condition. + */ mutex_lock(&cscfg_mutex); - list_for_each_entry(cfg_desc, &cscfg_mgr->config_desc_list, item) { - etm_perf_del_symlink_cscfg(cfg_desc); + while (!list_empty(&cscfg_mgr->load_order_list)) { + + /* remove in reverse order of loading */ + owner_info = list_last_entry(&cscfg_mgr->load_order_list, + struct cscfg_load_owner_info, item); + + /* action according to type */ + switch (owner_info->type) { + case CSCFG_OWNER_PRELOAD: + /* + * preloaded descriptors are statically allocated in + * this module - just need to unload dynamic items from + * csdev lists, and remove from configfs directories. + */ + pr_info("cscfg: unloading preloaded configurations\n"); + break; + + case CSCFG_OWNER_MODULE: + /* + * this is an error - the loadable module must have been unloaded prior + * to the coresight module unload. Therefore that module has not + * correctly unloaded configs in its own exit code. + * Nothing to do other than emit an error string as the static descriptor + * references we need to unload will have disappeared with the module. + */ + pr_err("cscfg: ERROR: prior module failed to unload configuration\n"); + goto list_remove; + } + + /* remove from configfs - outside the scope of the list mutex */ + mutex_unlock(&cscfg_mutex); + cscfg_fs_unregister_cfgs_feats(owner_info); + mutex_lock(&cscfg_mutex); + + /* Next unload from csdev lists. */ + cscfg_unload_owned_cfgs_feats(owner_info); + +list_remove: + /* remove from load order list */ + list_del(&owner_info->item); } + mutex_unlock(&cscfg_mutex); +} + +static void cscfg_clear_device(void) +{ + cscfg_unload_cfgs_on_exit(); cscfg_configfs_release(cscfg_mgr); device_unregister(cscfg_device()); - mutex_unlock(&cscfg_mutex); } /* Initialise system config management API device */ @@ -1074,20 +1269,16 @@ int __init cscfg_init(void) { int err = 0; + /* create the device and init cscfg_mgr */ err = cscfg_create_device(); if (err) return err; + /* initialise configfs subsystem */ err = cscfg_configfs_init(cscfg_mgr); if (err) goto exit_err; - INIT_LIST_HEAD(&cscfg_mgr->csdev_desc_list); - INIT_LIST_HEAD(&cscfg_mgr->feat_desc_list); - INIT_LIST_HEAD(&cscfg_mgr->config_desc_list); - INIT_LIST_HEAD(&cscfg_mgr->load_order_list); - atomic_set(&cscfg_mgr->sys_active_cnt, 0); - /* preload built-in configurations */ err = cscfg_preload(THIS_MODULE); if (err) diff --git a/drivers/hwtracing/coresight/coresight-syscfg.h b/drivers/hwtracing/coresight/coresight-syscfg.h index 9106ffab4833..66e2db890d82 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.h +++ b/drivers/hwtracing/coresight/coresight-syscfg.h @@ -12,6 +12,17 @@ #include "coresight-config.h" +/* + * Load operation types. + * When loading or unloading, another load operation cannot be run. + * When unloading configurations cannot be activated. + */ +enum cscfg_load_ops { + CSCFG_NONE, + CSCFG_LOAD, + CSCFG_UNLOAD +}; + /** * System configuration manager device. * @@ -30,6 +41,7 @@ * @cfgfs_subsys: configfs subsystem used to manage configurations. * @sysfs_active_config:Active config hash used if CoreSight controlled from sysfs. * @sysfs_active_preset:Active preset index used if CoreSight controlled from sysfs. + * @load_state: A multi-stage load/unload operation is in progress. */ struct cscfg_manager { struct device dev; @@ -41,6 +53,7 @@ struct cscfg_manager { struct configfs_subsystem cfgfs_subsys; u32 sysfs_active_config; int sysfs_active_preset; + enum cscfg_load_ops load_state; }; /* get reference to dev in cscfg_manager */ diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 4ac5c081af93..6c2fd6cc5a98 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -18,6 +18,7 @@ * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and * directly use below macros as config bits. */ +#define ETM_OPT_BRANCH_BROADCAST 8 #define ETM_OPT_CYCACC 12 #define ETM_OPT_CTXTID 14 #define ETM_OPT_CTXTID2 15 @@ -25,6 +26,7 @@ #define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ +#define ETM4_CFG_BIT_BB 3 #define ETM4_CFG_BIT_CYCACC 4 #define ETM4_CFG_BIT_CTXTID 6 #define ETM4_CFG_BIT_VMID 7 |