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path: root/drivers/clk/socfpga/clk-pll-s10.c
AgeCommit message (Expand)Author
2022-03-11clk: socfpga: cleanup spdx tagsTom Rix
2022-01-05clk: socfpga: remove redundant assignment on divisionColin Ian King
2021-04-07clk: socfpga: remove redundant initialization of variable divColin Ian King
2021-03-30clk: socfpga: Convert to s10/agilex/n5x to use clk_hwDinh Nguyen
2021-02-12clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen
2020-05-26clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen
2020-05-26clk: socfpga: add const to _ops data structuresDinh Nguyen
2020-05-26clk: socfpga: remove clk_ops enable/disable methodsDinh Nguyen
2020-05-26clk: socfpga: stratix10: use new parent data schemeDinh Nguyen
2020-02-12clk: socfpga: stratix10: simplify parameter passingDinh Nguyen
2020-02-12clk: stratix10: use do_div() for 64-bit calculationDinh Nguyen
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd
2019-01-11clk: socfpga: stratix10: fix rate calculation for pll clocksDinh Nguyen
2018-04-06clk: socfpga: stratix10: add clock driver for Stratix10 platformDinh Nguyen
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-14 18:04:49 +0000