diff options
| author | Marek Vasut | 2018-08-18 16:00:31 +0200 |
|---|---|---|
| committer | Marek Vasut | 2018-08-24 12:05:20 +0200 |
| commit | 331c37221057e6a1291b6e14d9f033a7a90051f1 (patch) | |
| tree | 8c3e682027c195195aa513165d1bef60ed5a1e2a | |
| parent | cca9af63a32220e0a270ac62fa9c46a0ed4ca0ce (diff) | |
ARM: socfpga: Convert Arria10 to timer framework
Switch the Arria10 from ad-hoc hardcoded timer to timer framework
and the DW APB timer driver. This allows the A10 to extract timer
information, like timer rate, from clock framework and thus DT
instead of having it hardcoded in U-Boot configuration files.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| -rw-r--r-- | arch/arm/mach-socfpga/Makefile | 1 | ||||
| -rw-r--r-- | configs/socfpga_arria10_defconfig | 3 | ||||
| -rw-r--r-- | include/configs/socfpga_common.h | 2 |
3 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 654999cdf68..e66720447f8 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -26,7 +26,6 @@ obj-y += clock_manager_arria10.o obj-y += misc_arria10.o obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o -obj-y += timer.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 4b0d47489aa..a5040355476 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -39,4 +39,7 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y CONFIG_USE_TINY_PRINTF=y diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 440a918fc7c..2330143cf1c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -86,11 +86,13 @@ /* * L4 OSC1 Timer 0 */ +#ifndef CONFIG_TIMER /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) #define CONFIG_SYS_TIMER_RATE 25000000 +#endif /* * L4 Watchdog |