rockchip: rk3128-cru: sync the clock dt-binding header from Linux

In order to update the DT for rk3128
sync the clock dt-binding header.
This is the state as of v6.0 in Linux.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

3 files changed, 160 insertions, 76 deletions

diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
index 5d2499c1324..3c5f54f6406 100644
--- a/arch/arm/dts/rk3128.dtsi
+++ b/arch/arm/dts/rk3128.dtsi
@@ -172,7 +172,7 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
-			clocks = <&cru ACLK_DMAC2>;
+			clocks = <&cru ACLK_DMAC>;
 			clock-names = "apb_pclk";
 		};
 	};
@@ -530,8 +530,8 @@
 		pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
 		rockchip,spi-src-clk = <0>;
 		num-cs = <2>;
-		clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>;
-		clock-names = "spi","pclk_spi0";
+		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+		clock-names = "spiclk", "apb_pclk";
 		dmas = <&pdma 8>, <&pdma 9>;
 		#dma-cells = <2>;
 		dma-names = "tx", "rx";
diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
index d5b2b63dd79..13e176cdad1 100644
--- a/drivers/clk/rockchip/clk_rk3128.c
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -438,7 +438,7 @@ static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
 			     VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
 			     (src_clk_div - 1) << VIO1_DIV_SHIFT);
 		break;
-	case DCLK_LCDC:
+	case DCLK_VOP:
 		if (pll_para_config(hz, &cpll_config))
 			return -1;
 		rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
@@ -471,7 +471,7 @@ static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
 		div = (con >> 8) & 0x1f;
 		parent = GPLL_HZ;
 		break;
-	case DCLK_LCDC:
+	case DCLK_VOP:
 		con = readl(&cru->cru_clksel_con[27]);
 		div = (con >> 8) & 0xfff;
 		parent = rkclk_pll_get_rate(cru, CLK_CODEC);
@@ -497,7 +497,7 @@ static ulong rk3128_clk_get_rate(struct clk *clk)
 		return rk3128_peri_get_pclk(priv->cru, clk->id);
 	case SCLK_SARADC:
 		return rk3128_saradc_get_clk(priv->cru);
-	case DCLK_LCDC:
+	case DCLK_VOP:
 	case ACLK_VIO0:
 	case ACLK_VIO1:
 		return rk3128_vop_get_rate(priv->cru, clk->id);
@@ -515,7 +515,7 @@ static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
 	switch (clk->id) {
 	case 0 ... 63:
 		return 0;
-	case DCLK_LCDC:
+	case DCLK_VOP:
 	case ACLK_VIO0:
 	case ACLK_VIO1:
 		new_rate = rk3128_vop_set_clk(priv->cru,
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index cfb3afbb285..6a47825dac5 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 /*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
+ * Author: Elaine <zhangqing@rock-chips.com>
  */
 
 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
@@ -9,30 +10,31 @@
 /* core clocks */
 #define PLL_APLL		1
 #define PLL_DPLL		2
-#define PLL_GPLL		3
-#define ARMCLK			4
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define ARMCLK			5
+#define PLL_GPLL_DIV2		6
+#define PLL_GPLL_DIV3		7
 
 /* sclk gates (special clocks) */
-#define SCLK_GPU		64
-#define SCLK_SPI		65
+#define SCLK_SPI0		65
+#define SCLK_NANDC		67
 #define SCLK_SDMMC		68
 #define SCLK_SDIO		69
 #define SCLK_EMMC		71
-#define SCLK_NANDC		76
 #define SCLK_UART0		77
 #define SCLK_UART1		78
 #define SCLK_UART2		79
-#define SCLK_I2S		82
+#define SCLK_I2S0		80
+#define SCLK_I2S1		81
 #define SCLK_SPDIF		83
 #define SCLK_TIMER0		85
 #define SCLK_TIMER1		86
 #define SCLK_TIMER2		87
 #define SCLK_TIMER3		88
+#define SCLK_TIMER4		89
+#define SCLK_TIMER5		90
 #define SCLK_SARADC		91
-#define SCLK_OTGPHY0		93
-#define SCLK_LCDC		100
-#define SCLK_HDMI		109
-#define SCLK_HEVC		111
 #define SCLK_I2S_OUT		113
 #define SCLK_SDMMC_DRV		114
 #define SCLK_SDIO_DRV		115
@@ -40,115 +42,173 @@
 #define SCLK_SDMMC_SAMPLE	118
 #define SCLK_SDIO_SAMPLE	119
 #define SCLK_EMMC_SAMPLE	121
-#define SCLK_PVTM_CORE          123
-#define SCLK_PVTM_GPU           124
-#define SCLK_PVTM_VIDEO         125
-#define SCLK_MAC		151
-#define SCLK_MACREF		152
-#define SCLK_SFC		160
+#define SCLK_VOP		122
+#define SCLK_MAC_SRC		124
+#define SCLK_MAC		126
+#define SCLK_MAC_REFOUT		127
+#define SCLK_MAC_REF		128
+#define SCLK_MAC_RX		129
+#define SCLK_MAC_TX		130
+#define SCLK_HEVC_CORE		134
+#define SCLK_RGA		135
+#define SCLK_CRYPTO		138
+#define SCLK_TSP		139
+#define SCLK_OTGPHY0		142
+#define SCLK_OTGPHY1		143
+#define SCLK_DDRC		144
+#define SCLK_PVTM_FUNC		145
+#define SCLK_PVTM_CORE		146
+#define SCLK_PVTM_GPU		147
+#define SCLK_MIPI_24M		148
+#define SCLK_PVTM		149
+#define SCLK_CIF_SRC		150
+#define SCLK_CIF_OUT_SRC	151
+#define SCLK_CIF_OUT		152
+#define SCLK_SFC		153
+#define SCLK_USB480M		154
 
-#define DCLK_LCDC		190
+/* dclk gates */
+#define DCLK_VOP		190
+#define DCLK_EBC		191
 
 /* aclk gates */
-#define ACLK_DMAC2		194
-#define ACLK_VIO0		197
-#define ACLK_VIO1		203
-#define ACLK_VCODEC		208
-#define ACLK_CPU		209
+#define ACLK_VIO0		192
+#define ACLK_VIO1		193
+#define ACLK_DMAC		194
+#define ACLK_CPU		195
+#define ACLK_VEPU		196
+#define ACLK_VDPU		197
+#define ACLK_CIF		198
+#define ACLK_IEP		199
+#define ACLK_LCDC0		204
+#define ACLK_RGA		205
 #define ACLK_PERI		210
+#define ACLK_VOP		211
+#define ACLK_GMAC		212
+#define ACLK_GPU		213
 
 /* pclk gates */
 #define PCLK_SARADC		318
+#define PCLK_WDT		319
 #define PCLK_GPIO0		320
 #define PCLK_GPIO1		321
 #define PCLK_GPIO2		322
 #define PCLK_GPIO3		323
+#define PCLK_VIO_H2P		324
+#define PCLK_MIPI		325
+#define PCLK_EFUSE		326
+#define PCLK_HDMI		327
+#define PCLK_ACODEC		328
 #define PCLK_GRF		329
 #define PCLK_I2C0		332
 #define PCLK_I2C1		333
 #define PCLK_I2C2		334
 #define PCLK_I2C3		335
-#define PCLK_SPI		338
+#define PCLK_SPI0		338
 #define PCLK_UART0		341
 #define PCLK_UART1		342
 #define PCLK_UART2		343
+#define PCLK_TSADC		344
 #define PCLK_PWM		350
 #define PCLK_TIMER		353
-#define PCLK_HDMI		360
-#define PCLK_CPU		362
+#define PCLK_CPU		354
 #define PCLK_PERI		363
-#define PCLK_DDRUPCTL		364
-#define PCLK_WDT		368
+#define PCLK_GMAC		367
+#define PCLK_PMU_PRE		368
+#define PCLK_SIM_CARD		369
 
 /* hclk gates */
-#define HCLK_OTG0		449
-#define HCLK_OTG1		450
+#define HCLK_SPDIF		440
+#define HCLK_GPS		441
+#define HCLK_USBHOST		442
+#define HCLK_I2S_8CH		443
+#define HCLK_I2S_2CH		444
+#define HCLK_VOP		452
 #define HCLK_NANDC		453
 #define HCLK_SDMMC		456
 #define HCLK_SDIO		457
 #define HCLK_EMMC		459
-#define HCLK_I2S		462
-#define HCLK_LCDC		465
-#define HCLK_ROM		467
-#define HCLK_VIO_BUS		472
-#define HCLK_VCODEC		476
-#define HCLK_CPU		477
+#define HCLK_CPU		460
+#define HCLK_VEPU		461
+#define HCLK_VDPU		462
+#define HCLK_LCDC0		463
+#define HCLK_EBC		465
+#define HCLK_VIO		466
+#define HCLK_RGA		467
+#define HCLK_IEP		468
+#define HCLK_VIO_H2P		469
+#define HCLK_CIF		470
+#define HCLK_HOST2		473
+#define HCLK_OTG		474
+#define HCLK_TSP		475
+#define HCLK_CRYPTO		476
 #define HCLK_PERI		478
 
 #define CLK_NR_CLKS		(HCLK_PERI + 1)
 
 /* soft-reset indices */
-#define SRST_CORE0		0
-#define SRST_CORE1		1
-#define SRST_CORE0_DBG		4
-#define SRST_CORE1_DBG		5
-#define SRST_CORE0_POR		8
-#define SRST_CORE1_POR		9
-#define SRST_L2C		12
-#define SRST_TOPDBG		13
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+#define SRST_TOPDBG		12
+#define SRST_ACLK_CORE		13
 #define SRST_STRC_SYS_A		14
-#define SRST_PD_CORE_NIU	15
+#define SRST_L2C		15
 
-#define SRST_TIMER2		16
-#define SRST_CPUSYS_H		17
-#define SRST_AHB2APB_H		19
-#define SRST_TIMER3		20
+#define SRST_CPUSYS_H		18
+#define SRST_AHB2APBSYS_H	19
+#define SRST_SPDIF		20
 #define SRST_INTMEM		21
 #define SRST_ROM		22
 #define SRST_PERI_NIU		23
-#define SRST_I2S		24
-#define SRST_DDR_PLL		25
-#define SRST_GPU_DLL		26
-#define SRST_TIMER0		27
-#define SRST_TIMER1		28
-#define SRST_CORE_DLL		29
+#define SRST_I2S_2CH		24
+#define SRST_I2S_8CH		25
+#define SRST_GPU_PVTM		26
+#define SRST_FUNC_PVTM		27
+#define SRST_CORE_PVTM		29
 #define SRST_EFUSE_P		30
 #define SRST_ACODEC_P		31
 
 #define SRST_GPIO0		32
 #define SRST_GPIO1		33
 #define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_MIPIPHY_P		36
 #define SRST_UART0		39
 #define SRST_UART1		40
 #define SRST_UART2		41
 #define SRST_I2C0		43
 #define SRST_I2C1		44
 #define SRST_I2C2		45
+#define SRST_I2C3		46
 #define SRST_SFC		47
 
-#define SRST_PWM0		48
+#define SRST_PWM		48
+#define SRST_DAP_PO		50
 #define SRST_DAP		51
 #define SRST_DAP_SYS		52
+#define SRST_CRYPTO		53
 #define SRST_GRF		55
-#define SRST_PERIPHSYS_A	57
-#define SRST_PERIPHSYS_H	58
-#define SRST_PERIPHSYS_P	59
+#define SRST_GMAC		56
+#define SRST_PERIPH_SYS_A	57
+#define SRST_PERIPH_SYS_H	58
+#define SRST_PERIPH_SYS_P       59
+#define SRST_SMART_CARD		60
 #define SRST_CPU_PERI		61
 #define SRST_EMEM_PERI		62
 #define SRST_USB_PERI		63
 
-#define SRST_DMA2		64
-#define SRST_MAC		66
+#define SRST_DMA		64
+#define SRST_GPS		67
 #define SRST_NANDC		68
 #define SRST_USBOTG0		69
 #define SRST_OTGC0		71
@@ -156,34 +216,58 @@
 #define SRST_OTGC1		74
 #define SRST_DDRMSCH		79
 
-#define SRST_MMC0		81
+#define SRST_SDMMC		81
 #define SRST_SDIO		82
 #define SRST_EMMC		83
-#define SRST_SPI0		84
+#define SRST_SPI		84
 #define SRST_WDT		86
 #define SRST_SARADC		87
 #define SRST_DDRPHY		88
 #define SRST_DDRPHY_P		89
 #define SRST_DDRCTRL		90
 #define SRST_DDRCTRL_P		91
+#define SRST_TSP		92
+#define SRST_TSP_CLKIN		93
+#define SRST_HOST0_ECHI		94
 
 #define SRST_HDMI_P		96
+#define SRST_VIO_ARBI_H		97
+#define SRST_VIO0_A		98
 #define SRST_VIO_BUS_H		99
+#define SRST_VOP_A		100
+#define SRST_VOP_H		101
+#define SRST_VOP_D		102
 #define SRST_UTMI0		103
 #define SRST_UTMI1		104
 #define SRST_USBPOR		105
+#define SRST_IEP_A		106
+#define SRST_IEP_H		107
+#define SRST_RGA_A		108
+#define SRST_RGA_H		109
+#define SRST_CIF0		110
+#define SRST_PMU		111
 
 #define SRST_VCODEC_A		112
 #define SRST_VCODEC_H		113
 #define SRST_VIO1_A		114
-#define SRST_HEVC		115
+#define SRST_HEVC_CORE		115
 #define SRST_VCODEC_NIU_A	116
-#define SRST_LCDC1_A		117
-#define SRST_LCDC1_H		118
-#define SRST_LCDC1_D		119
+#define SRST_PMU_NIU_P		117
+#define SRST_LCDC0_S		119
 #define SRST_GPU		120
 #define SRST_GPU_NIU_A		122
+#define SRST_EBC_A		123
+#define SRST_EBC_H		124
 
-#define SRST_DBG_P		131
+#define SRST_CORE_DBG		128
+#define SRST_DBG_P		129
+#define SRST_TIMER0		130
+#define SRST_TIMER1		131
+#define SRST_TIMER2		132
+#define SRST_TIMER3		133
+#define SRST_TIMER4		134
+#define SRST_TIMER5		135
+#define SRST_VIO_H2P		136
+#define SRST_VIO_MIPI_DSI	137
 
 #endif