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authorKever Yang2016-08-12 17:57:05 +0800
committerSimon Glass2016-09-22 07:57:02 -0600
commit4f0b8efa50a543efd407fb8b2e9ad0de49467a15 (patch)
tree7058ea6792f789249abd63266e5fb0bb51c6d798
parent5e79f443550a0aac1a4a118d956a48177972aa51 (diff)
clk: rk3288: add PWM clock get rate
This patch add clk_get_rate for PWM device. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
-rw-r--r--drivers/clk/rockchip/clk_rk3288.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index c07203d84b9..bd71a969278 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -695,6 +695,8 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
case PCLK_I2C4:
case PCLK_I2C5:
return gclk_rate;
+ case PCLK_PWM:
+ return PD_BUS_PCLK_HZ;
default:
return -ENOENT;
}