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authorTom Rini2019-04-08 10:11:29 -0400
committerTom Rini2019-04-08 10:11:29 -0400
commitc48b07a9fde187540630ff756cbba1101eb17310 (patch)
treec37c2bca522cc66a8d2b445d67248b86a9c2a3dd
parentccd063e9812a2bdcbeafbbcd8dcb062bfc290f24 (diff)
parente82fa10b3ef745ea08d5dac8ff088553846c2ca1 (diff)
Merge tag 'fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-staging
- i.MX8QXP-MEK ethernet fix
-rw-r--r--arch/arm/dts/fsl-imx8qxp-mek.dts1
-rw-r--r--drivers/net/fec_mxc.c11
-rw-r--r--drivers/net/fec_mxc.h1
3 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index 41f7ec17636..4f35fbe31db 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -224,6 +224,7 @@
status = "okay";
phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
+ phy-reset-post-delay = <150>;
mdio {
#address-cells = <1>;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index f991b40b385..84f010d8057 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1309,6 +1309,8 @@ static void fec_gpio_reset(struct fec_priv *priv)
dm_gpio_set_value(&priv->phy_reset_gpio, 1);
mdelay(priv->reset_delay);
dm_gpio_set_value(&priv->phy_reset_gpio, 0);
+ if (priv->reset_post_delay)
+ mdelay(priv->reset_post_delay);
}
}
#endif
@@ -1468,6 +1470,15 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev)
/* property value wrong, use default value */
priv->reset_delay = 1;
}
+
+ priv->reset_post_delay = dev_read_u32_default(dev,
+ "phy-reset-post-delay",
+ 0);
+ if (priv->reset_post_delay > 1000) {
+ printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
+ /* property value wrong, use default value */
+ priv->reset_post_delay = 0;
+ }
#endif
return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index e9a661f0a1d..e5f2dd75c59 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -258,6 +258,7 @@ struct fec_priv {
#ifdef CONFIG_DM_GPIO
struct gpio_desc phy_reset_gpio;
uint32_t reset_delay;
+ uint32_t reset_post_delay;
#endif
#ifdef CONFIG_DM_ETH
u32 interface;