Convert CONFIG_SYS_FSL_CPC et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_FSL_CPC
   CONFIG_SYS_CPC_REINIT_F

Signed-off-by: Tom Rini <trini@konsulko.com>

52 files changed, 50 insertions, 15 deletions

diff --git a/README b/README
index ed8e807c8f3..dae467a4da0 100644
--- a/README
+++ b/README
@@ -371,10 +371,6 @@ The following options need to be configured:
 		In this mode, a single differential clock is used to supply
 		clocks to the sysclock, ddrclock and usbclock.
 
-		CONFIG_SYS_CPC_REINIT_F
-		This CONFIG is defined when the CPC is configured as SRAM at the
-		time of U-Boot entry and is required to be re-initialized.
-
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 5971ec5df4e..d3ebbff43be 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -16,6 +16,7 @@ config CHAIN_OF_TRUST
 	select SHA_HW_ACCEL
 	select SHA_PROG_HW_ACCEL
 	select ENV_IS_NOWHERE
+	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
 	select CMD_EXT4 if ARM
 	select CMD_EXT4_WRITE if ARM
 	imply CMD_BLOB
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 9c5b1af8b59..915e28e1108 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1221,6 +1221,15 @@ config SYS_BOOK3E_HV
 	bool "Category E.HV is supported"
 	depends on BOOKE
 
+config SYS_CPC_REINIT_F
+	bool
+	help
+	  The CPC is configured as SRAM at the time of U-Boot entry and is
+	  required to be re-initialized.
+
+config SYS_FSL_CPC
+	bool "Corenet Platform Cache support"
+
 config SYS_MPC85XX_NO_RESETVEC
 	bool "Discard resetvec section and move bootpg section up"
 	depends on MPC85xx
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index a96a1ac5d77..3e707600f28 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -21,9 +21,6 @@
 	defined(CONFIG_TARGET_T1042D4RDB) || \
 	defined(CONFIG_TARGET_T1042RDB_PI) || \
 	defined(CONFIG_ARCH_T1024)
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_CPC_REINIT_F
-#endif
 #undef CONFIG_SYS_INIT_L3_ADDR
 #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
 #endif
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 459b9e6c544..4c453a7cd94 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -9,6 +9,7 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 6ff6a428306..b5f920b013e 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -9,6 +9,7 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index a5872faa474..ecf63e59c6b 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 247db8e0fef..e609dfcbf21 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 91ad3ee3051..59fdc33ad47 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -9,6 +9,7 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 6ca91fe77ed..17aa980518d 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -9,6 +9,7 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 13857b8208f..2be600a5847 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index b587d525a26..f22719558fe 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index c88a869bc8f..2aba2228947 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -9,6 +9,7 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index a627475420f..9bfb0a88f11 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 82371ea9897..1d5f00d1c8b 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index be3d388484f..741adc51622 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -9,6 +9,7 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 4dcdb391e40..c10c94849e0 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -9,6 +9,7 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 7620f4879a7..111ca1d4877 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 68573a5c982..fd94afa762f 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index d10799f83cf..d44f0625585 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 22c404e27c2..fdff32c2d2d 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -15,6 +15,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 2f1e9ca46ef..fdfbdd2ec04 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -17,6 +17,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 5c30e9fe376..9f1599fb633 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_T1024RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 00ea2175a77..aca69b32160 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -13,6 +13,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index c738e9c4133..fcf530d44f1 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index bc38fa68b2f..3e0239edf3d 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index af7df9ee91c..3063157a7f6 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -9,6 +9,7 @@ CONFIG_TARGET_T1042D4RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index e7ce3631e0a..8cb38f2d11f 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -20,6 +20,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index a2a2c589d7c..5691ba5fc09 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -21,6 +21,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 4f35dbd945f..ee7edd5af99 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_NXP_ESBC=y
 CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
 CONFIG_PCIE1=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index b02939f679c..53a50514931 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -23,6 +23,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 6caffde6d4e..5deb88da225 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -10,6 +10,7 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SRIO_PCIE_BOOT_SLAVE=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 4ec70d678c0..4969909504a 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -11,6 +11,7 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index f382288ebbb..af66fd2013a 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -17,6 +17,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 5837b3d26da..41956d8d3df 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -18,6 +18,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index ab191c702f1..0811b18fb6e 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -20,6 +20,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index fff8a26b323..b8b66d41180 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -13,6 +13,7 @@ CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index c5ab7af3351..48711c5c947 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -17,6 +17,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index 83f47250094..bd98910c003 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -18,6 +18,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
 <<<<<<< HEAD
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index 0c5365217ee..04ef733621f 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -20,6 +20,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
 <<<<<<< HEAD
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index 66a9d5dcadb..25ee845627d 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -13,6 +13,7 @@ CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_T2080RDB_REV_D=y
 <<<<<<< HEAD
 =======
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 639cb80e8e9..6141f558e7f 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -18,6 +18,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 6f403619d67..7fc4dc951eb 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -13,6 +13,7 @@ CONFIG_TARGET_T4240RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 38d33c20dc9..bcecb88e4d1 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -12,6 +12,7 @@ CONFIG_TARGET_KMCENT2=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
+CONFIG_SYS_FSL_CPC=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_PCIE1=y
 CONFIG_KM_DEF_NETDEV="eth2"
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 72dd39d2306..27889e3033c 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -30,7 +30,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 #define CONFIG_SYS_SRIO
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index a93e9d0b58a..aa80d400bd9 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -15,7 +15,6 @@
 
 /* High Level Configuration Options */
 
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 #ifdef CONFIG_RAMBOOT_PBL
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 365640dffc1..2fb181090b5 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -58,7 +58,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 /*
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 2faec638e2d..84dfc894819 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -22,7 +22,6 @@
 
 /* High Level Configuration Options */
 
-#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
 
 #ifdef CONFIG_RAMBOOT_PBL
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 5ed9e1badb3..716e9c3d556 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -17,7 +17,6 @@
 
 /* High Level Configuration Options */
 
-#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
 
 #ifdef CONFIG_RAMBOOT_PBL
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 96e8ff4842b..e697d8490c9 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -39,7 +39,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 /*
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 66bd5cb9c0f..d1a5d866d2d 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -33,7 +33,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 /*
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index eafdc35c27b..ff9d7d59a39 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -137,7 +137,6 @@
 
 #define CONFIG_RESET_VECTOR_ADDRESS	0xebfffffc
 
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 /* Environment in parallel NOR-Flash */