WIP: Sniper support

8 files changed, 519 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index b32a6b0e5f5..02b4ccf2a33 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -114,6 +114,10 @@ config TARGET_OMAP3_CAIRO
 	select DM_SERIAL
 	select DM_GPIO
 
+config TARGET_SNIPER
+	bool "Sniper"
+	select SUPPORT_SPL
+
 endchoice
 
 config SYS_SOC
@@ -142,5 +146,6 @@ source "board/nokia/rx51/Kconfig"
 source "board/technexion/tao3530/Kconfig"
 source "board/technexion/twister/Kconfig"
 source "board/quipos/cairo/Kconfig"
+source "board/lge/sniper/Kconfig"
 
 endif
diff --git a/board/lge/sniper/Kconfig b/board/lge/sniper/Kconfig
new file mode 100644
index 00000000000..f7a682e0a71
--- /dev/null
+++ b/board/lge/sniper/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SNIPER
+
+config SYS_BOARD
+	default "sniper"
+
+config SYS_VENDOR
+	default "lge"
+
+config SYS_CONFIG_NAME
+	default "sniper"
+
+endif
diff --git a/board/lge/sniper/MAINTAINERS b/board/lge/sniper/MAINTAINERS
new file mode 100644
index 00000000000..0e7baa515b4
--- /dev/null
+++ b/board/lge/sniper/MAINTAINERS
@@ -0,0 +1,6 @@
+SNIPER BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	board/lge/sniper/
+F:	include/configs/sniper.h
+F:	configs/sniper_defconfig
diff --git a/board/lge/sniper/Makefile b/board/lge/sniper/Makefile
new file mode 100644
index 00000000000..94897160f98
--- /dev/null
+++ b/board/lge/sniper/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= sniper.o
diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c
new file mode 100644
index 00000000000..68539e6e155
--- /dev/null
+++ b/board/lge/sniper/sniper.c
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2014
+ * Paul Kocialkowski <contact@paulk.fr>
+ *
+ * Based on the OMAP3 Pandora code:
+ * (C) Copyright 2008
+ * Grazvydas Ignotas <notasas@gmail.com>
+ *
+ * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <lp8720.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "sniper.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"Sniper",
+	"MMC",
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+	timings->ctrla = HYNIX_V_ACTIMA_200;
+	timings->ctrlb = HYNIX_V_ACTIMB_200;
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+	timings->mr = MICRON_V_MR_165;
+/*
+	timings->mcfg = (0x02584019|(2<<6));
+	timings->ctrla = 0x92E1C4C6;
+	timings->ctrlb = 0x0002121C;
+	timings->rfr_ctrl = 0x0005e601;
+	timings->mr = 0x00000032;
+*/
+}
+#endif
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_SNIPER();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	ret = omap_mmc_init(0, 0, 0, -1, -1);
+	if (ret)
+		return ret;
+
+	ret = omap_mmc_init(1, 0, 0, SNIPER_GPIO_MICROSD_DET_N, -1);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+int board_mmc_power_init(void)
+{
+	/*
+	 * In order to boot from MMC1 (microsd card), the LP8720 LDO1 (3.0V_MMC)
+	 * regulator has to be enabled. The LP8720 is accessed through I2C3.
+	 *
+	 * Enabling TWL4030 VAUX2 (3.0V_MOTION) and TWL4030 VDAC
+	 * (1.8V_MOTION_VIO) is required to power the sensors that are slaves
+	 * on I2C3. When not powered, these sensors cause I2C3 SCK to stay low.
+	 */
+
+	i2c_set_bus_num(0);
+
+	/* TWL4030 VAUX2 (3.0V_MOTION) to 2.8V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+				TWL4030_PM_RECEIVER_VAUX2_VSEL_28,
+				TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	/* TWL4030 VDAC (1.8V_MOTION_VIO) to 1.8V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
+				TWL4030_PM_RECEIVER_VDAC_VSEL_18,
+				TWL4030_PM_RECEIVER_VDAC_DEV_GRP,
+				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	mdelay(100);	/* ramp-up delay from Linux code */
+
+	i2c_set_bus_num(2);
+
+	lp8720_init(SNIPER_GPIO_CAM_SUBPM_EN, LP8720_CHIP_IDSEL_GND);
+
+	/* LP8720 LDO1 (3.0V_MMC) to 3.0V */
+	lp8720_ldo_voltage(LP8720_LDO1_SETTINGS, LP8720_LDO1235_V_30,
+				LP8720_DELAY_0);
+	lp8720_ldo_enable(LP8720_LDO1_EN);
+
+	i2c_set_bus_num(0);
+
+	/* TWL4030 VMMC2 to 3.2V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+				TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+				TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	mdelay(100);	/* ramp-up delay from Linux code */
+
+	return 0;
+}
+#endif
diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h
new file mode 100644
index 00000000000..aff9109d529
--- /dev/null
+++ b/board/lge/sniper/sniper.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2014
+ * Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SNIPER_H_
+#define _SNIPER_H_
+
+#define SNIPER_GPIO_CAM_SUBPM_EN	37
+#define SNIPER_GPIO_MICROSD_DET_N	10
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN	- Pull type selection is active
+ * M0	- Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_SNIPER() \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) /* MMC1_CLK */\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /* MMC1_DAT4 */\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /* MMC1_DAT5 */\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /* MMC1_DAT6 */\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /* MMC1_DAT7 */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /* MMC2_CLK */\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /* MMC2_CMD */\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /* MMC2_DAT0 */\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /* MMC2_DAT1 */\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /* MMC2_DAT2 */\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /* MMC2_DAT3 */\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M0)) /* MMC2_DAT4 */\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M0)) /* MMC2_DAT5 */\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M0)) /* MMC2_DAT6 */\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M0)) /* MMC2_DAT7 */\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /* UART3_CTS_RCTX */\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /* UART3_RTS_SD */\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /* UART3_RX_IRRX */\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /* UART3_TX_IRTX */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | DIS | M0)) /* I2C3_SCL */\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | DIS | M0)) /* I2C3_SDA */ \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTU | DIS | M4)) /* GPIO_10: MICROSD_DET_N */
+
+#endif
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
new file mode 100644
index 00000000000..e7bc224be0b
--- /dev/null
+++ b/configs/sniper_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
++S:CONFIG_TARGET_SNIPER=y
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
new file mode 100644
index 00000000000..dcf1197de91
--- /dev/null
+++ b/include/configs/sniper.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2014
+ * Paul Kocialkowski <contact@paulk.fr>
+ *
+ * Based on the OMAP3 Pandora code:
+ * (C) Copyright 2008-2010
+ * Gražvydas Ignotas <notasas@gmail.com>
+ *
+ * Configuration settings for Sniper, LGE P970 aka Optimus Black.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/*
+ * Platform configuration
+ */
+
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_OMAP_GPIO
+#define CONFIG_SDRC
+
+/*
+ * Board configuration
+ */
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * Clocks
+ */
+
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_FRAMEWORK
+
+/* Addresses */
+#define CONFIG_SPL_TEXT_BASE		0x40200000
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		(512 * 1024)	/* 512 KB */
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(1024 * 1024)
+
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+/* Board-specific */
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+
+/* Support */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+
+/* Boot */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PART		2
+
+/* Thats boot-related */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_OF_LIBFDT		1
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 + CONFIG_ENV_SIZE)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+#define CONFIG_SYS_DEVICE_NULLDEV	1
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+
+/*
+ * NS16550 Configuration
+ */
+
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * Serial console configuration
+ */
+
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_EFI_PARTITION		1
+/*
+ * Commands
+ */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_CACHE	/* Cache control		*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * TWL4030
+ */
+
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+#define CONFIG_LP8720_POWER		1
+#define CONFIG_OMAP3_GPIO_2
+/*
+ * Environment
+ */
+
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"usbtty=cdc_acm\0" \
+	"setcon=setenv stdin ${con};" \
+		"setenv stdout ${con};" \
+		"setenv stderr ${con}\0" \
+	"usbcon=setenv con usbtty; run setcon\0" \
+	"loadaddr=0x82000000\0" \
+	"bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
+		"rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"run usbcon"
+
+#define CONFIG_AUTO_COMPLETE	1
+
+#define MTDPARTS_DEFAULT
+
+/*
+ * Display CPU and Board information
+ */
+
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"Sniper # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_NOWHERE		1
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#endif				/* __CONFIG_H */