diff options
| author | Weijie Gao | 2022-09-09 19:59:33 +0800 |
|---|---|---|
| committer | Tom Rini | 2022-09-23 15:09:15 -0400 |
| commit | bc15e30346e9ed181b74045e64fc496f9c4ce086 (patch) | |
| tree | 742011a9fe47481f043f1c61f13d8ceab3fafd7c | |
| parent | 3b17f2e2c2a93b5a0809c782c5bb7ed1b3f68ec1 (diff) | |
arm: dts: mt7622: force high-speed mode for uart
The input clock for uart is too slow (25MHz) which introduces frequent data
error on both receiving and transmitting even if the baudrate is 115200.
Using high-speed can significantly solve this issue.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| -rw-r--r-- | arch/arm/dts/mt7622.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 0127474c95d..fb6c1b71549 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -175,6 +175,7 @@ status = "disabled"; assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + mediatek,force-highspeed; }; mmc0: mmc@11230000 { |