diff options
author | Mario Six | 2018-08-06 10:23:45 +0200 |
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committer | Simon Glass | 2018-09-18 08:12:21 -0600 |
commit | 19fbdca47b3d847824ada3ab2ed575019c88516e (patch) | |
tree | 6498222d45f3cb1c6fb39b47b9cd0186884e9e46 /Documentation | |
parent | fa44b53398d3a7f5ed28cb83493a70cde11f8188 (diff) |
cpu: Add MPC83xx CPU driver
Add a CPU driver for the MPC83xx architecture.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt b/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt new file mode 100644 index 00000000000..ac563d906ac --- /dev/null +++ b/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt @@ -0,0 +1,34 @@ +MPC83xx CPU devices + +MPC83xx SoCs contain a e300 core as their main processor. + +Required properties: +- compatible: must be one of "fsl,mpc83xx", + "fsl,mpc8308", + "fsl,mpc8309", + "fsl,mpc8313", + "fsl,mpc8315", + "fsl,mpc832x", + "fsl,mpc8349", + "fsl,mpc8360", + "fsl,mpc8379" +- clocks: has to have two entries, which must be the core clock at index 0 and + the CSB (Coherent System Bus) clock at index 1. Both are given by a suitable + "fsl,mpc83xx-clk" device + +Example: + +socclocks: clocks { + compatible = "fsl,mpc8315-clk"; + #clock-cells = <1>; +}; + +cpus { + compatible = "cpu_bus"; + + PowerPC,8315@0 { + compatible = "fsl,mpc8315"; + clocks = <&socclocks MPC83XX_CLK_CORE + &socclocks MPC83XX_CLK_CSB>; + }; +}; |