diff options
| author | Ran Wang | 2017-09-04 18:46:48 +0800 |
|---|---|---|
| committer | York Sun | 2017-09-11 08:01:06 -0700 |
| commit | 2ab1553f08b1cb4a76764b1a67f75f77554860e3 (patch) | |
| tree | 7d97351a29a6626eedbf4dc141419676fcbd8710 /arch/arm/cpu | |
| parent | 9a609a88004e5be73d873e229f1b61bd52c749f7 (diff) | |
armv8: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 23 |
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 82d61600e12..64eadfd25ae 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -16,6 +16,7 @@ config ARCH_LS1043A select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009660 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009929 @@ -39,6 +40,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 @@ -100,6 +102,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008514 select SYS_FSL_ERRATUM_A008585 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009635 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009801 @@ -248,6 +251,9 @@ config LS_PPA_ESBC_HDR_SIZE endmenu +config SYS_FSL_ERRATUM_A009008 + bool "Workaround for USB PHY erratum A009008" + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a3b9f6baa45..b9e3a2075ac 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -54,6 +54,27 @@ bool soc_has_aiop(void) return false; } +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) +{ + scfg_clrsetbits32(scfg + offset / 4, + 0xF << 6, + SCFG_USB_TXVREFTUNE << 6); +} + +static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); +#elif defined(CONFIG_ARCH_LS2080A) + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -200,6 +221,7 @@ void fsl_lsch3_early_init_f(void) #endif erratum_a008514(); erratum_a008336(); + erratum_a009008(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -478,6 +500,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009929(); erratum_a009660(); erratum_a010539(); + erratum_a009008(); } #endif |