Merge tag 'u-boot-at91-2023.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2023.04 cycle:

This feature set includes the new DM-based NAND flash driver (old non-DM
driver is still kept for backwards compatibility), and the move to DM
NAND flash driver for sam9x60ek board. Feature set also includes
devicetree alignment for sama7g5 with Linux, devicetree alignment on USB
with Linux for all boards (sama5, sam9x60), chip id for sama7g5, minor
configs and tweaks.

3 files changed, 112 insertions, 1 deletions

diff --git a/arch/arm/mach-at91/armv7/sama7g5_devices.c b/arch/arm/mach-at91/armv7/sama7g5_devices.c
index 0b702c7fb76..6f2c1fc9142 100644
--- a/arch/arm/mach-at91/armv7/sama7g5_devices.c
+++ b/arch/arm/mach-at91/armv7/sama7g5_devices.c
@@ -4,7 +4,31 @@
  *		      Eugen Hristev <eugen.hristev@microchip.com>
  */
 
+#include <asm/arch/sama7g5.h>
+
 char *get_cpu_name(void)
 {
-	return "SAMA7G5";
+	unsigned int extension_id = get_extension_chip_id();
+
+	if (cpu_is_sama7g5())
+		switch (extension_id) {
+		case ARCH_EXID_SAMA7G51:
+			return "SAMA7G51";
+		case ARCH_EXID_SAMA7G52:
+			return "SAMA7G52";
+		case ARCH_EXID_SAMA7G53:
+			return "SAMA7G53";
+		case ARCH_EXID_SAMA7G54:
+			return "SAMA7G54";
+		case ARCH_EXID_SAMA7G54_D1G:
+			return "SAMA7G54 1Gb DDR3L SiP";
+		case ARCH_EXID_SAMA7G54_D2G:
+			return "SAMA7G54 2Gb DDR3L SiP";
+		case ARCH_EXID_SAMA7G54_D4G:
+			return "SAMA7G54 4Gb DDR3L SiP";
+		default:
+			return "Unknown CPU type";
+		}
+	else
+		return "Unknown CPU type";
 }
diff --git a/arch/arm/mach-at91/include/mach/sama7-sfr.h b/arch/arm/mach-at91/include/mach/sama7-sfr.h
new file mode 100644
index 00000000000..a987ff54652
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama7-sfr.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Microchip SFR (Special Function Registers) registers for SAMA7 family.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Cristian Birsan <cristian.birsan@microchip.com>
+ */
+
+#ifndef _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H
+#define _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H
+
+#define SAMA7_SFR_OHCIICR	0x00	/* OHCI INT Configuration Register */
+#define SAMA7_SFR_OHCIISR	0x04	/* OHCI INT Status Register */
+/* 0x08 ~ 0xe3: Reserved */
+#define SAMA7_SFR_WPMR		0xe4	/* Write Protection Mode Register */
+#define SAMA7_SFR_WPSR		0xe4	/* Write Protection Status Register */
+/* 0xec ~ 0x200b: Reserved */
+#define SAMA7_SFR_DEBUG		0x200c	/* Debug Register */
+
+/* 0x2010 ~ 0x2027: Reserved */
+#define SAMA7_SFR_EHCIOHCI	0x2020  /* EHCI OHCI Clock Configuration Reg */
+
+#define SAMA7_SFR_HSS_AXI_QOS	0x2028	/* HSS AXI QOS Register */
+#define SAMA7_SFR_UDDRC		0x202c  /* UDDRC Register */
+#define SAMA7_SFR_CAN_SRAM_SEL	0x2030	/* CAN SRAM Select. Register */
+/* 0x2034 ~ 0x203f: Reserved */
+
+#define SAMA7_SFR_UTMI0		0x2040
+#define SAMA7_SFR_UTMI0R(x)	(SAMA7_SFR_UTMI0 + 4 * (x))
+
+#define SAMA7_SFR_UTMI0R0	0x2040	/* UTMI0 Configuration Register */
+#define SAMA7_SFR_UTMI0R1	0x2044	/* UTMI1 Configuration Register */
+#define SAMA7_SFR_UTMI0R2	0x2048	/* UTMI2 Configuration Register */
+
+/* Field definitions */
+#define SAMA7_SFR_OHCIICR_ARIE			BIT(0)
+#define SAMA7_SFR_OHCIICR_APPSTART		BIT(1)
+#define SAMA7_SFR_OHCIICR_USB_SUSP(x)		BIT(8 + (x))
+#define SAMA7_SFR_OHCIICR_USB_SUSPEND		GENMASK(10, 8)
+
+#define SAMA7_SFR_OHCIISR_RIS(x)		BIT(x)
+
+#define SAMA7_SFR_WPMR_WPEN			BIT(0)
+#define SAMA7_SFR_WPMR_KEY			0x53465200 /* SFR in ASCII*/
+#define SAMA7_SFR_WPMR_WPKEY_MASK		GENMASK(31, 8)
+
+#define SAMA7_SFR_WPSR_WPSRC_MASK		GENMASK(23, 8)
+#define SAMA7_SFR_WPSR_WPVS_MASK		BIT(0)
+
+#define SAMA7_SFR_CAN_SRAM_UPPER(x)		BIT(x)
+
+#define SAMA7_SFR_UTMI_RX_VBUS			BIT(25) /* VBUS Valid bit */
+#define SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X	BIT(23) /* TXPREEMPAMPTUNE 1x */
+#define SAMA7_SFR_UTMI_COMMONON			BIT(3)  /* PLL Common ON bit */
+
+#define SAMA7_SFR_EHCIOHCI_PHYCLK		BIT(1)  /* Alternate PHY Clk */
+
+#endif /* _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H */
diff --git a/arch/arm/mach-at91/include/mach/sama7g5.h b/arch/arm/mach-at91/include/mach/sama7g5.h
index ae43e8700be..621a26f6eba 100644
--- a/arch/arm/mach-at91/include/mach/sama7g5.h
+++ b/arch/arm/mach-at91/include/mach/sama7g5.h
@@ -67,7 +67,35 @@
 
 #define ATMEL_BASE_PIT64BC	ATMEL_BASE_PIT64B0
 
+/* SAMA7G5 series chip id definitions */
+#define ARCH_ID_SAMA7G5		0x80162100
+#define ARCH_EXID_SAMA7G51	0x00000003
+#define ARCH_EXID_SAMA7G52	0x00000002
+#define ARCH_EXID_SAMA7G53	0x00000001
+#define ARCH_EXID_SAMA7G54	0x00000000
+#define ARCH_EXID_SAMA7G54_D1G	0x00000018
+#define ARCH_EXID_SAMA7G54_D2G	0x00000020
+#define ARCH_EXID_SAMA7G54_D4G	0x00000028
+
+#define cpu_is_sama7g5()	(get_chip_id() == ARCH_ID_SAMA7G5)
+#define cpu_is_sama7g51()	(cpu_is_sama7g5() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA7G51))
+#define cpu_is_sama7g52()	(cpu_is_sama7g5() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA7G52))
+#define cpu_is_sama7g53()	(cpu_is_sama7g5() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA7G53))
+#define cpu_is_sama7g54()	(cpu_is_sama7g5() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA7G54))
+#define cpu_is_sama7g54d1g()	(cpu_is_sama7g5() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA7G54_D1G))
+#define cpu_is_sama7g54d2g()	(cpu_is_sama7g5() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA7G54_D2G))
+#define cpu_is_sama7g54d4g()	(cpu_is_sama7g5() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA7G54_D4G))
+
 #ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
 char *get_cpu_name(void);
 #endif